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clk: qcom: gcc-sm6115: Add missing PLL config properties

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When the driver was ported upstream, PLL ctl register values were omitted.
Add them to ensure the PLLs are fully configured like we expect them to.

Fixes: cbe63bfdc5 ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Iskren Chernev <me@iskren.info>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230601-topic-alpha_ctl-v1-2-b6a932dfcf68@linaro.org
This commit is contained in:
Konrad Dybcio 2023-06-01 11:39:08 +02:00 committed by Bjorn Andersson
parent 5016243394
commit e88c533d8a
1 changed files with 8 additions and 0 deletions
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8
drivers/clk/qcom/gcc-sm6115.c
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@ -119,6 +119,8 @@ static const struct alpha_pll_config gpll10_config = {
.vco_mask = GENMASK(21, 20),
.main_output_mask = BIT(0),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_mask = 0x1,
};
static struct clk_alpha_pll gpll10 = {
@ -170,6 +172,8 @@ static const struct alpha_pll_config gpll11_config = {
.vco_val = 0x2 << 20,
.vco_mask = GENMASK(21, 20),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_mask = 0x1,
};
static struct clk_alpha_pll gpll11 = {
@ -362,6 +366,8 @@ static const struct alpha_pll_config gpll8_config = {
.post_div_val = 0x1 << 8,
.post_div_mask = GENMASK(11, 8),
.config_ctl_val = 0x4001055b,
.test_ctl_hi1_val = 0x1,
.test_ctl_hi_mask = 0x1,
};
static struct clk_alpha_pll gpll8 = {
@ -413,6 +419,8 @@ static const struct alpha_pll_config gpll9_config = {
.post_div_mask = GENMASK(9, 8),
.main_output_mask = BIT(0),
.config_ctl_val = 0x00004289,
.test_ctl_mask = GENMASK(31, 0),
.test_ctl_val = 0x08000000,
};
static struct clk_alpha_pll gpll9 = {