- Fix 'function-mask' referring to TRM (Omap 36xx) Section 13.4.4:
"Pad Functional Multiplexing and Configuration".
- Fix 'omap3_pmx_wkup' referring to TRM Table 13-6:
"Wkup Control Module Pad Configuration Register Fields".
Note that these fixes are not critical currently as we
are not yet using the missing range of pinmux registers
at this point.
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
[tony@atomide.com: updated comments]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add device-tree node for the 128MB NOR on the OMAP3430-SDP board.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add device-tree node for the 64MB NOR on the OMAP2420-H4 board.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The GPMC timing properties for device-tree have been updated by adding
a "-ns" or "-ps" suffix to indicate the units of time the property
represents (as suggested by Rob Herring). Therefore, update the timing
property names for the OMAP3430 SDP NAND and ONENAND devices.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add the "ti,gpio-always-on" property to the appropriate GPIO banks to
indicate which banks are always powered and will never lose logic state.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Update the DMTIMER compatibility property to reflect the register level
compatibilty between devices and update the various OMAP/AM timer
bindings with the appropriate compatibility string.
By doing this we can add platform specific data applicable to specific
timer versions to the driver. For example, errata flags can be populated
for the timer versions that are impacted.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
DT field of "interrupts" was mentioned wrongly as "interrupt" in SPI
node. This went unnoticed as spi-omap2 driver not making use of
interrupt. Fixes the typo.
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add DT OPP table for OMAP4460 family of devices. This data is
decoded by OF with of_init_opp_table() helper function.
OPP data here is based on existing opp4xxx_data.c
This is in preparation to use generic cpufreq-cpu0 driver for device
tree enabled boot. Legacy non device tree enabled boot continues to
use omap-cpufreq.c and opp4xxx_data.c.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
PandaBoard, PandaBoard-A4 revisions use OMAP4430.
PandaBoard-ES version of the board uses OMAP4460.
Move the original panda dts file into a common dtsi used by all panda
variants. This allows us to introduce SoC variation for PandaBoard ES
without impacting other PandaBoard versions that are supported.
As part of this change, since OMAP4460 adds on to OMAP4430, add
omap4.dtsi to omap4460.dtsi.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add DT OPP table for OMAP443x family of devices. This data is
decoded by OF with of_init_opp_table() helper function.
OPP data here is based on existing opp4xxx_data.c
Since the omap4460 OPP tables would be different from OMAP443x,
introduce an new omap443x.dtsi for 443x specific entries and use
existing omap4.dtsi as the common dtsi file for all OMAP4 platforms.
This is in preparation to use generic cpufreq-cpu0 driver for device
tree enabled boot. Legacy non device tree enabled boot continues to
use omap-cpufreq.c and opp4xxx_data.c.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Define VDD1 regulator in twl4030 DT and mark it as the supply for the
various OMAP34xx/35xx/36xx/37xx platforms (all use TWL4030 variants with
VDD1 supplying the CPU).
NOTE: This currently will use I2C1 bus communication path to set the
voltage in device tree boot. In the legacy non device tree boot, we
continue to use twl-common.c which bypasses I2C1 bus communication path
and uses I2C4 bus path using OMAP voltage libraries. We should
eventually be able to use I2C4 path once we have voltage regulator for
OMAP which is capable of using the voltage controller/voltage processor
IP blocks.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add DT OPP table for OMAP36xx/37xx family of devices. This data is
decoded by OF with of_init_opp_table() helper function.
OPP data here is based on existing opp3xxx_data.c
This is in preparation to use generic cpufreq-cpu0 driver for device
tree enabled boot. Legacy non device tree enabled boot continues to
use omap-cpufreq.c and opp3xxx_data.c.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add DT OPP table for OMAP34xx/35xx family of devices. This data is
decoded by OF with of_init_opp_table() helper function.
OPP data here is based on existing opp3xxx_data.c
Since the omap36xx OPP tables would be different from OMAP34xx/35xx,
introduce an new omap34xx.dtsi for 34xx/35xx specific entries and use
existing omap3.dtsi as the common dtsi file for all OMAP3 platforms.
This is in preparation to use generic cpufreq-cpu0 driver for device
tree enabled boot. Legacy non device tree enabled boot continues to
use omap-cpufreq.c and opp3xxx_data.c.
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add l3-noc node for OMAP4 and OMAP5 devices.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[jon-hunter@ti.com: Fix the problem caused by adding 32 to the interrupt
number for the L3 interrupts to account for per processor interrupts (PPI)
and software generated interrupts (SGI) which typically are mapped to the
first 32 interrupts in the ARM GIC. This is not necessary because the first
parameter of the ARM GIC interrupt property specifies the GIC interrupt
type (ie. SGI, PPI, etc). Hence, fix the interrupt number for the L3
interrupts by substracting 32]
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
To be able to run kernel in HYP mode, virtual timer
and GIC node information needs to be populated.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
GIC is not part of OCP space so move the gic DT node
out of ocp DT address space.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Specify both secure as well as nonsecure PPI IRQ for arch
timer. This fixes the following errors seen on DT OMAP5 boot..
[ 0.000000] arch_timer: No interrupt available, giving up
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
It has been decided to not duplicate banked modules dt nodes and that is
how the current arch timer dt extraction code is.
Update the OMAP5 DT file accordingly.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
On OMAP5 to detect invalid/bad memory accesses, 16MB of DDR is used as a trap.
Hence available memory for linux OS is 2032 MB on boards popullated with 2 GB
memory.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add the needed sections to enable audio support on
Devkit8000 when booted with DT blob.
Signed-off-by: Anil Kumar <anilk4.v@gmail.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
DevKit8000 is a beagle board clone from Timll, sold by
armkits.com. The DevKit8000 has RS232 serial port, LCD, DVI-D,
S-Video, Ethernet, SD/MMC, keyboard, camera, SPI, I2C, USB and
JTAG interface.
Add the basic DT support for devkit8000. It includes:
- twl4030 (PMIC)
- MMC1
- I2C1
- leds
Signed-off-by: Anil Kumar <anilk4.v@gmail.com>
Tested-by: Thomas Weber <thomas@tomweber.eu>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Adds basic device-tree support for OMAP3430 SDP board which has 256MB
of RAM, 128MB ONENAND flash, 256MB NAND flash and uses the TWL4030
power management IC.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The OMAP3 gpio bindings are currently missing the reg and interrupt
properties and so add these properties.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
The OMAP gpio binding documention [1] states that the #interrupts-cells
property for gpio controllers should be 2. Currently, for OMAP3+ devices
the #interrupt-cells is set to 1. By setting this property to 2, it
allows clients to pass a 2nd parameter indicating the sensitivity (level
or edge) and polarity (high or low) of the interrupt. The OMAP gpio
controllers support these options and so update the #interrupt-cells
property for OMAP3+ devices to 2.
[1] Documentation/devicetree/bindings/gpio/gpio-omap.txt
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add the device-tree node for GPMC on OMAP2, OMAP4 and OMAP5 devices.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add SDMA controller binding for OMAP2+ devices and populate DMA client
information for SPI and MMC peripheral on OMAP3+ devices. Please note
that OMAP24xx devices do not have SPI and MMC bindings available yet and
so DMA client information is not populated.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add PMU nodes for OMAP2, OMAP3 and OMAP4460 devices.
Please note that the node for OMAP4460 has been placed in a separate
header file for OMAP4460, because the node is not compatible with
OMAP4430. The node for OMAP4430 is not included because PMU is not
currently supported on OMAP4430 due to the absence of a cross-trigger
interface driver.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add dwc3 omap glue data to the omap5 dt data file.
The information about the dt node added here is available @
Documentation/devicetree/bindings/usb/omap-usb.txt.
Also added dwc3 core dt data as a subnode to dwc3 omap glue
data in omap5 dt data file.
The information for the entered data node is available @
Documentation/devicetree/bindings/usb/dwc3.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add omap-usb3 and omap-usb2 data node in OMAP5 device tree file.
The information for the node added here is available @
Documentation/devicetree/bindings/usb/usb-phy.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add ocp2scp data node in omap5 device tree file.
The information for the node added here can be found @
Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add omap control usb data in OMAP5 device tree file.
This will have the register address of registers to
power on the USB2 PHY and USB3 PHY.
The information for the node added here is available in
Documentation/devicetree/bindings/usb/omap-usb.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add usb otg data node in omap4/omap3 device tree file. Also update
the node with board specific setting in omapx-<board>.dts file.
The dt data specifies among others the interface type (ULPI or UTMI),
mode which is mostly OTG, power that specifies the amount of power
this can supply when in host mode.
The information about usb otg node is available @
Documentation/devicetree/bindings/usb/omap-usb.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add omap-usb2 data node in omap4 device tree file. Since omap-usb2
is connected to ocp2scp, omap-usb2 dt data is added as a child node
of ocp2scp. The information about this data node is availabe @
Documentation/devicetree/bindings/usb/usb-phy.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add omap control usb data in omap4 device tree file. This will have the
register address of registers to power on the PHY and to write to
mailbox. The information about this data node is available @
Documentation/devicetree/bindings/usb/omap-usb.txt
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Currently the OMAP General-Purpose Memory Controller (GPMC) device
node maps 16 MB of address space for its hardware registers.
This is because the OMAP Technical Reference Manual says that the
GPMC module register address space size is 16 MB. But in practice
the maximum address offset used by a GPMC register is 0x02d0.
So, there is no need to map such a big address space for GPMC regs.
This change was suggested by Jon Hunter [1].
[1]: https://patchwork.kernel.org/patch/2057111/
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add device-tree support for the GPMC controller on the OMAP3.
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Booting 3.8-rc6 on omap4 panda results in the following error
[ 0.444427] omap_i2c 48070000.i2c: did not get pins for i2c error: -19
[ 0.445770] omap_i2c 48070000.i2c: bus 0 rev0.11 at 400 kHz
[ 0.473937] omap_i2c 48072000.i2c: did not get pins for i2c error: -19
[ 0.474670] omap_i2c 48072000.i2c: bus 1 rev0.11 at 400 kHz
[ 0.474822] omap_i2c 48060000.i2c: did not get pins for i2c error: -19
[ 0.476379] omap_i2c 48060000.i2c: bus 2 rev0.11 at 100 kHz
[ 0.477294] omap_i2c 48350000.i2c: did not get pins for i2c error: -19
[ 0.477996] omap_i2c 48350000.i2c: bus 3 rev0.11 at 400 kHz
[ 0.483398] Switching to clocksource 32k_counter
This happens because omap4 panda dts file is not adapted to use i2c through
pinctrl framework. Populating i2c pinctrl data to get rid of the error.
Tested on omap4460 panda with 3.8-rc6 kernel.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reported-by: Luciano Coelho <coelho@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Booting 3.8-rc6 on omap 5430evm results in the following error
omap_i2c 48070000.i2c: did not get pins for i2c error: -19
[ 1.024261] omap_i2c 48070000.i2c: bus 0 rev0.12 at 100 kHz
[ 1.030181] omap_i2c 48072000.i2c: did not get pins for i2c error: -19
[ 1.037384] omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz
[ 1.043762] omap_i2c 48060000.i2c: did not get pins for i2c error: -19
[ 1.050964] omap_i2c 48060000.i2c: bus 2 rev0.12 at 100 kHz
[ 1.056823] omap_i2c 4807a000.i2c: did not get pins for i2c error: -19
[ 1.064025] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz
This happens because omap5 dts file is not adapted to use i2c through pinctrl
framework. Populating i2c pinctrl data to get rid of the error.
Tested on omap5430 evm with 3.8-rc6 kernel.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add the needed sections to enable audio support on Overo.
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Booting 3.8-rc6 on omap 4430sdp results in the following error
omap_i2c 48070000.i2c: did not get pins for i2c error: -19
[ 1.024261] omap_i2c 48070000.i2c: bus 0 rev0.12 at 100 kHz
[ 1.030181] omap_i2c 48072000.i2c: did not get pins for i2c error: -19
[ 1.037384] omap_i2c 48072000.i2c: bus 1 rev0.12 at 400 kHz
[ 1.043762] omap_i2c 48060000.i2c: did not get pins for i2c error: -19
[ 1.050964] omap_i2c 48060000.i2c: bus 2 rev0.12 at 100 kHz
[ 1.056823] omap_i2c 4807a000.i2c: did not get pins for i2c error: -19
[ 1.064025] omap_i2c 4807a000.i2c: bus 3 rev0.12 at 400 kHz
This happens because omap4 dts file is not adapted to use i2c through pinctrl
framework. Populating i2c pinctrl data to get rid of the error.
Tested on omap4430 sdp with 3.8-rc6 kernel.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reported-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Convert the on-board LED connected to the TWL4030 (LEDB) to use
pwm-leds.
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Section to describe the backlight for the LCD panels.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Sections to describe the pwm-leds in the system.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
We have proper driver stack to handle the pmu_stat LED which is connected
PWMB of twl4030.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Enable support for the PWMs and LED as PWM drivers.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Enable support for the PWMs and LEDs as PWM drivers.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add a new address space/memory resource to d_can device tree node. D_CAN
RAM initialization is achieved through RAMINIT register which is part of
AM33XX control module address space. D_CAN RAM init or de-init should be
done by writing instance corresponding value to control module register.
Till we have a separate control module driver to write to control module,
d_can driver will handle the register writes to control module by itself.
So a new address space to represent this control module register is added
to d_can driver.
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add d_can instances to aliases node to get the D_CAN instance number
from the driver. To initialize D_CAN message RAM, corresponding instance
number is required.
To initialize instance 0 message RAM then 0x1 should be written and for
instance 1 message RAM, 0x2 should be written to control module register.
With device-tree framework ip instance number is "-1" by default for all
instances. To get device id/instance number then modules should be added
to DT "aliases" node. of_alias_get_id() gives the device id number based
on number of alias nodes present in "aliases node".
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
This is a follow-up to Javier Martinez effort adding initial
device tree support to IGEP technology devices [1].
It adds uart1 and uart2 bindings to the generic dtsi for the IGEP boards.
[1] http://www.spinics.net/lists/linux-omap/msg83409.html
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
ISEE IGEP COM Module is an TI OMAP3 SoC computer on module.
This patch adds an initial device tree support to boot an
IGEP COM Module from the MMC/SD.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Enric Balletbo i Serra <eballetbo@gmail.com>
[b-cousson@ti.com: Update the Makefile for 3.8-rc2]
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
ISEE IGEPv2 is an TI OMAP3 SoC based embedded board.
This patch adds an initial device tree support to boot
an IGEPv2 from the MMC/SD.
Currently is working everything that is supported by DT
on OMAP3 SoCs (MMC/SD, GPIO LEDs, EEPROM, TWL4030 audio).
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Enric Balletbo i Serra <eballetbo@gmail.com>
[benoit.cousson@linaro.org: Update the Makefile for 3.8-rc2]
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Add a generic .dtsi device tree source file for the
common characteristics across IGEP Technology devices.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Tested-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Rename I2C and GPIO nodes according to AM33XX TRM. According to
AM33XX TRM device instances are starting from "0" like i2c0, i2c1
and i2c3.
Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
[panto@antoniou-consulting.com: initial patch by pantelis's]
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
In the early days, the A10 and A13 shared quite some code. Nowadays it
shares less and less code, the A31 diverging even more, so it doesn't
make much sense to continue to maintain this structure, just use one
DTSI for every SoC, and that's it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
- Rename the clock compatible introduced in the first pull request for 3.10
- Complete the UART support for A13 and A10
- Adds clock gates support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRXwBbAAoJEBx+YmzsjxAgDf8P/A3i6dGQe2DMnLRzJ8fwAsvj
VXqoC6YKEszelVSeQuqDE/pytoUfb1+1xEklkj95sHS4ds7fV6qVLM2Lp3TrBBEk
oGdwC6cS97BeNZxnnkTXUNWHlXdlFbkI7D0bd/GC4LLjrpUzu299BPdQ3zoXUEqf
xlm32aydivW87MX/1BfwdQPqA05x6/ZvOcxkWK6qQvXNl/iBoksJRjjQQdrCDxqz
fe34XbflblgQv3cmiONpi7BCFWzKVZcvDD1pHdgdNXiahpZjNMnFH7DEUhc24tTX
DHGwMwhvGDvjD/gp6h6xvCswYxMyLmFUZp2TKJ4ffd04/jncvPIUuSYzkeyUOGav
ZVBBik41Pxk+aKOX75vYffhHSb+AtmQqaORHLXidIOVC1UlnlHOj6RMODs2Z+JzG
kLhdy0fmLSaf6rKDvFAyqjR16apiaeRwxd581jKoFDn10P/c1Fg+R2FvrE8DA2fP
tiKDPrdO3U1CUq8PVYJFuN2D7SfkOSRz72tcMaFuBFnk7E0pmcgwzkvD7VqFexA4
Qf55VjSITMpVBX4L+TLCMgckp4OjcBQtwEgYQjwTNjtVRpr5BQUwBTHKCgRZt7jo
WaO8P4FLg4rka9aV52hNCka+O7qTeLOkfC08mZZGUkkfQ0gb4U8EAhdPRNsSiOHj
qtiLCwLX7X+WEIWs8vfo
=ErkU
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-for-3.10-2' of git://github.com/mripard/linux into next/dt
From Maxime Ripard <maxime.ripard@free-electrons.com>:
ARM: sunxi: dt additions for 3.10, take 2
- Rename the clock compatible introduced in the first pull request for 3.10
- Complete the UART support for A13 and A10
- Adds clock gates support
* tag 'sunxi-dt-for-3.10-2' of git://github.com/mripard/linux:
arm: sunxi: Add clock to pinctrl node
arm: sunxi: use the right clock phandles for UARTs
arm: sunxi: Add clock definitions for AXI, AHB, APB0, APB1 gates
ARM: sunxi: cubieboard: Add UART muxing
ARM: sunxi: hackberry: Add UART muxing
ARM: sunxi: dt: Add A10 UARTs to the dtsi.
ARM: sunxi: dt: Add uart3 dt node
ARM: sunxi: dt: Move uart0 to sun4i-a10.dtsi
ARM: sunxi: Rename uart nodes to serial
ARM: sunxi: dt: Use clocks property instead of clock-frequency for the UARTs
arm: sunxi: rename clock compatible strings
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This branch adds two devices to the BCM2835 SoC device tree: the SPI
controller and the HW random number generator.
The SPI controller isn't actually instantiated in the Raspberry Pi
device tree, since there are no on-board SPI devices; it's up to the
end-user to modify their own device-tree to describe whatever they
have attached.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRXiScAAoJEJuNpwkmVCGckMkP/RFLV7a4QQORyO9HhZkqaMGD
iwHtHFiFgbFmrc76oe/DxJrnJieSWdreVSWXc5NpAv6uZqMx7Lc11dGV399R+v0C
IaB7z7lMHBOk2IOmjIwVby8vrrHX5Ui7vweYxjk9k117U7ZN/syAcaPQsj32W6Lr
wKn+CpmyIzU0iB0kyydLfS18znW7gd17WFOu8tYB3qqf+avJNzcOfNHaIlafG0s6
+qn/gBWPRNg/ceyV94kPyjsPoLqv1q3YJER1P9Tvyb9MQecwpBd/ZmZjWr14hMf0
SvjsHD2uLV8UO0Wq/R5+VnC1YybsrOAvbgZz06Ai+SDa33diHXp4/uXqJ0soWTT8
hG4a2V965LfCUNVHFmAGL8ZcZk/HaL4FLucKceDavcorFuN7rtK+q6rAoYk0cR8j
bYi0xIIPctd28Mkpx1ArifeAa9+jeAxwC79H3jn9xzdYBdVJkV6SgSBZPQFbQviP
eFJu+Rh2QOA2Icm2dLOr6aZXdGWFO8DBF9LSLzXaX5yOaUYsGNKLBl7JOY+0MA47
P6TMokbHRULKqSfgUJxf+jCcXKl8hOB/obSw3SX1sTVxaAmi2IL39salwIQXloIz
/1Wjgbv2eVxtSbM9XResvpsTxE6RdZuz0uE5BKgXIvI6fwdZ9uQaAWvxphn0MvXt
Qz0aMbTD0wEIANE6j/u4
=4Sjv
-----END PGP SIGNATURE-----
Merge tag 'bcm2835-for-3.10-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi into next/dt
From Stephen Warren <swarren@wwwdotorg.org>:
ARM: bcm2835: device tree updates
This branch adds two devices to the BCM2835 SoC device tree: the SPI
controller and the HW random number generator.
The SPI controller isn't actually instantiated in the Raspberry Pi
device tree, since there are no on-board SPI devices; it's up to the
end-user to modify their own device-tree to describe whatever they
have attached.
* tag 'bcm2835-for-3.10-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi:
ARM: bcm2835: add Broadcom BCM2835 RNG to the device tree
ARM: bcm2835: add SPI device to DT
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This series consists mainly of clean-ups for clockevents and
clocksource timers on OMAP2+ devices. The most significant change
in functionality comes from the 5th patch which is changing the
selection of the clocksource timer for OMAP3 and AM335x devices
when gptimers are used for clocksource.
Note that this series depends on 7185684 (ARM: OMAP: use
consistent error checking) in RMK's tree and 960cba6 (ARM:
OMAP5: timer: Update the clocksource name as per clock data)
in omap-for-v3.10/fixes-non-critical. So this branch is based
on a merge of 7185684 and omap-for-v3.10/fixes-non-critical
to avoid non-trivial merge conflicts.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRXGvCAAoJEBvUPslcq6VzKRQQAIedi+lXSAQk/0t2wythB+Es
94oGmo5g2In+A7FE3gt7IOkSn/k334AwgizcCVRJewvJYii+8vvttVzBqlnyxGAG
VVu0lJ5rwpCd8R4bmcl+dg5jnKreC3doE51D9M0NtU+GW4gln5m3dCq22cbz3sET
GzGPSBJeWpHin2xHmIGR9210KdY8LT2yP6nIcwFLK6EiQNS/XFj1akaehgnnGjMB
9qqi06iRpBszJTEHXfEUfD6UMA4Tml7HQUuqjEt+oMod+Ucu98XhgfpCJr+WN67g
xHxoR8bitVVhReU6WmWNLuSl3CX/fBG81RTxagA7SSVCg93NEd0lPX1K+U8jy5hR
V+/wcgb0t0W0us+yuBwPvmlJ+E2t64NjUBXr7rDEwQGk/QSmd3kzQlSpLwnamDx4
hqnpXPpt5tbCUl6Ubqn4hLnsqz2VJAFw6QWZl+UhkvQMd0RNOg3faJSxjUdzo5n9
2IKx0ZWAXXNIKKp8eBh7w3z4qlWiK0Xfsq/GuSfHx49ybFRGkX38FI34I9eUYbH8
14vAfQkb0Tv+X0U3O03rNY6cpOz7nXG3FACBxOp+upYQKN+rFfM3DP+jPrWaLeJg
KFfJT1kVEuOi09X2jAFmuj7E2pFamGujFqm7eZ7Vj9NT0NXGI5s87nlpobrOXL2V
blRJmn0JBqFE+R6udU5+
=5kiA
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.10/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers
From Tony Lindgren <tony@atomide.com>:
Clean-up for omap2+ timers from Jon Hunter <jon-hunter@ti.com>:
This series consists mainly of clean-ups for clockevents and
clocksource timers on OMAP2+ devices. The most significant change
in functionality comes from the 5th patch which is changing the
selection of the clocksource timer for OMAP3 and AM335x devices
when gptimers are used for clocksource.
Note that this series depends on 7185684 (ARM: OMAP: use
consistent error checking) in RMK's tree and 960cba6 (ARM:
OMAP5: timer: Update the clocksource name as per clock data)
in omap-for-v3.10/fixes-non-critical. So this branch is based
on a merge of 7185684 and omap-for-v3.10/fixes-non-critical
to avoid non-trivial merge conflicts.
* tag 'omap-for-v3.10/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP4+: Fix sparse warning in system timers
ARM: OMAP2+: Store ID of system timers in timer structure
ARM: OMAP3: Update clocksource timer selection
ARM: OMAP2+: Simplify system timers definitions
ARM: OMAP2+: Simplify system timer clock definitions
ARM: OMAP2+: Remove hard-coded test on timer ID
ARM: OMAP2+: Display correct system timer name
ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS"
ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD"
ARM: OMAP: dpll: enable bypass clock only when attempting dpll bypass
ARM: OMAP2+: powerdomain: avoid testing whether an unsigned char is less than 0
ARM: OMAP2+: hwmod: Remove unused _HWMOD_WAKEUP_ENABLED flag
ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk
ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
These are needed for the USB PHY support, and are based on
commit 1f0972f5 from Felipe Balbi's tree as agreed on the
mailing lists.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRWxNHAAoJEBvUPslcq6VzFVEP/2Lr3RULnqiQbGx03SGySeXB
bS/CuVYjiWEK7bJC4glx2BzQYF612N0cx60TYtrErbiU99pyFmhHNp9VWBjgmHBl
GGuLWcwUgp4skzgk18SFDqSC/80VP/eGnuD3UBPfNRSL43qvutHg32OPrunvEVRQ
ojRZ8o8Dw9Tn2lcfev0dXu7/nYKrlREKGfU0nMrUBbBMKfwc9o4t1y4KdFIq9agx
FBJ8LsKKIQh5UsmE6jOApobVkiuUfSVqHS5x3SYdiPvX5FMP3TX5xTIGBeeXWgsx
/fp46X0h3PXNrruF/+KO8FlZ00EZBsZ8/FCKYyiTjHI/bHE9SLh/3Udi3MvUyI2S
xUN9G5vZFIzD9c7MIWVriml8luN1PsTK2R+FVJ0bXKXQixPylVrQRHIFKj2nby7m
gHog6KNBvWNKW7MGPOq3YG3bhBCNCj1pC/IHpChB9cBRcPNTdwXVRB6sZ+KkHlYK
N0myjweYLwxk/spm2IzmAFHje0T0039KD/ouGnnt3HO6a1V1TZfZBbn6ZUJqAZ/+
bHwEimvc1lU8FscvFqEHwd2IT6yQTfq2l6W8Su4oxpwiWkNiwbqwpbOGdYnMUmgI
YcNlGtw4ivjbCqu+O/8o1I/YUnv3z7NtCvjZGAUUccjbadJ3744b7BNWqmwOdflD
eARubcN0jNnnBO5wyaPi
=TU3y
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.10/usb-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers
From Tony Lindgren <tony@atomide.com>:
EHCI platform data related changes for v3.10 merge window.
These are needed for the USB PHY support, and are based on
commit 1f0972f5 from Felipe Balbi's tree as agreed on the
mailing lists.
* tag 'omap-for-v3.10/usb-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits)
ARM: dts: omap3-beagle: Add USB Host support
ARM: dts: OMAP3: Add HS USB Host IP nodes
ARM: dts: OMAP4: Add HS USB Host IP nodes
ARM: OMAP: zoom: Adapt to ehci-omap changes
ARM: OMAP3: overo: Adapt to ehci-omap changes
ARM: OMAP3: omap3touchbook: Adapt to ehci-omap changes
ARM: OMAP3: omap3stalker: Adapt to ehci-omap changes
ARM: OMAP3: omap3pandora: Adapt to ehci-omap changes
ARM: OMAP3: omap3evm: Adapt to ehci-omap changes
ARM: OMAP3: igep0020: Adapt to ehci-omap changes
ARM: OMAP: devkit8000: Adapt to ehci-omap changes
ARM: OMAP3: cm-t3517: Adapt to ehci-omap changes
ARM: OMAP3: cm-t35: Adapt to ehci-omap changes
ARM: OMAP: AM3517evm: Adapt to ehci-omap changes
ARM: OMAP: AM3517crane: Adapt to ehci-omap changes
ARM: OMAP3: 3630SDP: Adapt to ehci-omap changes
ARM: OMAP3: 3430SDP: Adapt to ehci-omap changes
ARM: OMAP3: Beagle: Adapt to ehci-omap changes
ARM: OMAP2+: omap4panda: Adapt to ehci-omap changes
ARM: OMAP2+: omap-usb-host: Add usbhs_init_phys()
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch adds a arm-pmu node to bind device tree for exynos4210.
The exynos4210 and 4212 have two cpus which includes a pmu. In contrast, the
exynos4412 has 4 cpus and pmus. We need to define two more pmus for this type
board. However, supporting arm-pmu for the exynos4412 will handle it later
because there is no dts support for 4412 based board.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch enables arm-pmu to bind device tree for exynos5250. The exynos5250
has two pmus which have combiner irq type.
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
From Michal Simek <michal.simek@xilinx.com>:
This branch is based on zynq/clksrc/cleanup parts because
there are some dependencies on moving timer to generic location.
I could based it on standard Linux tagged version but you will get
several conflicts you will have to resolve.
If you are OK to resolving these problems, please let me know
I will create another branch with core-smp changes which are not based
on zynq/clksrc/cleanup branch.
* 'zynq/core-smp' of git://git.xilinx.com/linux-xlnx:
arm: zynq: Add hotplug support
arm: zynq: Add smp support
arm: zynq: Add smp_twd timer
arm: zynq: Get rid of xilinx function prefix
arm: zynq: Add support for system reset
arm: zynq: Move slcr initialization to separate file
arm: zynq: Load scu baseaddress at run time
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
PDMA0@0x121000 changes are added into the architecture DTS file.
Signed-off-by: Subash Patel <subash.rp@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add cpufreq controller device node for Exynos5440 SoC for passing
parameters like controller base address, interrupt and cpufreq
table. This node is added outside cpu0 as this driver is now a platform
driver and a new device structure is needed.
Cc: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The Exynos5440 common clock driver has changed the clock ID's for
some of the clocks. Fix the gmac clock entries in Exynos5440 dtsi
file accordingly.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Updated the bootargs to boot the system with rootfs in /dev/sda2
instead of ramdisk.
Signed-off-by: Subash Patel <subash.rp@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
PMU in exynos5440 generates one interrupt per core and needs to be
passed from DT to GIC to register it.
Signed-off-by: Subash Patel <subash.rp@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds node for GMAC for exynos5440 SoC supported by GMAC
driver.
Signed-off-by: Byungho An <bh74.an@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Exynos5440 pin-controller generates eight interrupts to support
gpio interrupts. List those interrupt numbers in the pin-controller
node.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds FIMD related nodes for the Origen Quad board.
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds a common FIMD device node for all Exynos4 SoCs.
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds device tree node for the SYSREG registers block
found in Samsung S5P/Exynos SoC series. The SYSREG module
generates control signals for the ARM CPU and various IP blocks
and buses. SYSREG block registers are exposed through APB bus
interface. A sysreg device tree node is to be associated with
mfd syscon driver and all SYSREG clients should use regmap
interface it provides. It allows to eliminate any possible races
and conflicts should different drivers attempt to concurrently
access same register.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This adds common FIMD device node for all Exynos5 SoCs
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Exynos5440 has GIC which has virtualization support
in them. These are used by KVM.
Signed-off-by: Giridhar Maruthy <giridhar.m@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This is a fixup to two device tree nodes that have already landed but
without clock nodes since the transition to common clock happened at
the same time.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
[gautam.vivek@samsung.com: tested on smdk5250]
Tested-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The exynos 5250 SoC supports A15 style architected timers. Indicate
this through the device tree.
This is required by KVM.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The GIC in the exynos5250 SoC is A15 compliant. Show this through
the device tree, so that we can use the GIC for KVM.
Also add the respective A15 memory regions and interrupt links.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Added HDMI hot plug and regulator nodes to Arndale DT file.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
From Michal Simek <michal.simek@xilinx.com>:
It enables pmu support for zynq.
* 'zynq/core' of git://git.xilinx.com/linux-xlnx:
arm: zynq: Add support for pmu
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Michal Simek <michal.simek@xilinx.com>:
* 'zynq/clksrc/cleanup' of git://git.xilinx.com/linux-xlnx:
arm: zynq: Move timer to generic location
arm: zynq: Do not use xilinx specific function names
arm: zynq: Move timer to clocksource interface
arm: zynq: Use standard timer binding
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This series adds support for the pinctrl/gpio module on all arch-vt8500
supported SoCs.
As part of the review process, some tidy up is also done to
drivers/of/base.c to remove some code that is being constantly duplicated.
Also, a patch for the bcm2835 pinctrl driver is included to take advantage
of the new of/base.c code.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJRXQtJAAoJEAKiPfwuf9N/a/8H/3qun+1PnkDIGmC0amZDDrXD
tF8pruxccwOjh4Wug+UUzAwsBgej4NB193/ljFc35em9yFlZAcXBo0tLUd1gTxSd
nOkNWjYtFCK3hdmsE29Le9bRkCxn7g07uEkOKWSw79aYWrTRy63FDnr0p45YZvih
C4+ry92c50SJoW5kp+L6lS0aQjeBGXRCRcvuRBdwGPLYQXX/gEJfJrvU40ZrPByr
KJqhNOPoNS99OaVMPWDP4HCjCd/XVHBqd8Qz6M2uEIo2EBS0DnOt5IGoaRfTvEXM
Qx/y769v8/ndcdLAXFdPo+1ZgrrCXm7SozJhwAtMm3ruCxIN8u9LB6ZjMV2uaBo=
=+Y/Z
-----END PGP SIGNATURE-----
Merge tag 'vt8500/pinctrl' of git://server.prisktech.co.nz/git/linuxwmt into next/drivers
From Tony Prisk <linux@prisktech.co.nz>:
arm: vt8500: Add pinctrl driver for arch-vt8500
This series adds support for the pinctrl/gpio module on all arch-vt8500
supported SoCs.
As part of the review process, some tidy up is also done to
drivers/of/base.c to remove some code that is being constantly duplicated.
Also, a patch for the bcm2835 pinctrl driver is included to take advantage
of the new of/base.c code.
* tag 'vt8500/pinctrl' of git://server.prisktech.co.nz/git/linuxwmt: (606 commits)
pinctrl: bcm2835: make use of of_property_read_u32_index()
gpio: vt8500: Remove arch-vt8500 gpio driver
arm: vt8500: Remove gpio devicetree nodes
arm: dts: vt8500: Update Wondermedia SoC dtsi files for pinctrl driver
pinctrl: gpio: vt8500: Add pincontrol driver for arch-vt8500
arm: vt8500: Increase available GPIOs on arch-vt8500
of: Remove duplicated code for validating property and value
of: Add support for reading a u32 from a multi-value property.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Added S5M8767 PMIC DT nodes for Arndale board. Only the used
LDO's/BUCK are defined here. Also the nodes describe the default/reset
state LDO's and no power mangement tuning is implemented. The usage
desription can be found in s5m8767 device tree binding documentation.
Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This is required to keep the existing functionality of having no
write protect pin on Arndale board.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add default pin state information for all client nodes that require
pin configuration support using pinctrl interface.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add default pin state information for all client nodes that require
pin configuration support using pinctrl interface.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
of these fixes are needed to support omap5 es2 version that includes
PM features while the earlier version es1 did not.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRWwn7AAoJEBvUPslcq6Vztp4QAKWN2Tv218cf21Qfa3gjjAk4
I45+cBvsNqyMo3HoXrHLXM5QyI7p3g3ixdYdak5QxZ+eiyJaigNVRCD/bsmEzC0W
aYU2uwgLJOCkWdilPFvNsHpIm/9Ecfv6Ss3TVHIp5XpJQhoZ466tfmiWlpR9xEPZ
BBIYr1NSvnb19AKL/CjOwM2xNuIJOjFF4cMiltRpXy96vdtnrPLzLlz4NrD9LhdW
iT0ZGLKb0T6N1awwcmdKgJNudk3i4uc5XbvQoloL62EVPc6PHH6tOG3skjI283nw
W4kiyZzVy6FLzyNz/7pZ22IZdxZ4h8cBnBz8nBrdav65tPzukWghdWvlwJdpxfkh
BT512Fg+a4i2LMZDdUCCeY7lUVYr7Z3ckl0RObqlWBf210aEUiq5FfrvDYxX2xZm
P9TR7uajfDr4HqoI/kBYjZe/sHhesugWxdKxzDPf9wF6vuQC1cpwucT92ybtRbJn
aiTNi6s1k2QuDgAor26mMoIctZt+uZOYfkAtpp/nvWj8vUAcRWb9eHVmcm2uHI8/
ijMwlPxsQ846K/ztTlTlAw0wvOdvmXXf8PNT2wKsNTmcwbLK+2uCGTR4q2O7WOFo
lKFB93/zJA3mL52bhSkEkEFrbRv6XsRfSc4tcVdueEQAfjZD3hsngpzS5PsDczbo
MLm0q7WCBHhS0CRqOFEE
=mjWl
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.10/fixes-non-critical-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical
From Tony Lindgren <tony@atomide.com>:
Non critical omap fixes for v3.10 merge window. A big chunk
of these fixes are needed to support omap5 es2 version that includes
PM features while the earlier version es1 did not.
* tag 'omap-for-v3.10/fixes-non-critical-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS"
ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD"
ARM: OMAP: dpll: enable bypass clock only when attempting dpll bypass
ARM: OMAP2+: powerdomain: avoid testing whether an unsigned char is less than 0
ARM: OMAP2+: hwmod: Remove unused _HWMOD_WAKEUP_ENABLED flag
ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk
ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry
Contains an update to 3.9-rc5
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- A couple mxs boards that run I2C at 400 kHz experience some unstable
issue occasionally. Slow down the clock speed to have I2C work
reliably.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJRXCXBAAoJEFBXWFqHsHzOqg4H/irUyWQkIfch7us/vnMQnntr
y67TFoq1ucfHDA4/Okd5YxeUWjh0vaFJTVu5JLKfuT7HGTzSeqG4sFCp/A6/i9F9
ZGbcmTUSgG3erjpzN0R+PLxWO5iqjT8Mg3/cyK83SguKtf4u/MVJq8jpTyc0JJ9R
UNj4OaKN5n7tvPGAkj8ypWDpQwlczRRie6v+Nt1qWP1K7T7Ez9ZMkhOvd7WLUi4T
H7HcWo5IOUBzLvf7JmBAQwTCTdl7BJglBO5FjTn7ao0uaMEHLJOwzPWdXs08Agzh
qMVJcWqVCcQQmB5nuDDb08mlXXEYrt/92qL3LUejJaX76bPH+lzfCnvrDGUIuvo=
=Towm
-----END PGP SIGNATURE-----
Merge tag 'mxs-fixes-3.9-4' of git://git.linaro.org/people/shawnguo/linux-2.6 into fixes
From Shawn Guo <shawn.guo@linaro.org>:
The mxs fixes for 3.9, take 4:
- A couple mxs boards that run I2C at 400 kHz experience some unstable
issue occasionally. Slow down the clock speed to have I2C work
reliably.
* tag 'mxs-fixes-3.9-4' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: mxs: Slow down the I2C clock speed
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Instead of using a custom binding for retrieving the GPIO that activates the
LCD from devicetree, use a standard regulator.
This approach has the advantage to be more generic.
For example: in the case of a board that has a PMIC supplying the LCD voltage,
the current approach would not work, as it only searches for a GPIO pin.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The recent dtc+cpp support allows header files and C pre-processor
defines/macros to be used when compiling device tree files. These
headers will typically define various constants that are part of the
device tree bindings.
The original patch which set up the dtc+cpp include path only considered
using those headers from device tree files. However, most are also
useful for kernel code which needs to interpret the device tree.
In both the DT files and the kernel, I'd like to include the DT-related
headers in the same way, for example, <dt-bindings/gpio/tegra-gpio.h>.
That will simplify any text which discusses the DT header locations.
Creating a <dt-bindings/> for kernel source to use is as simple as
placing files into include/dt-bindings/.
However, when compiling DT files, the include path should be restricted
so that only the dt-bindings path is available; arbitrary kernel headers
shouldn't be exposed. For this reason, create a specific include
directory for use by dtc+cpp, and symlink dt-bindings from there to the
actual location of include/dt-bindings/. For want of a better location,
place this "include chroot" into the existing dts/ directory.
arch/*/boot/dts/include/dt-bindings -> ../../../../../include/dt-bindings
Some headers used by device tree files may not be useful to the kernel;
they may be used simply to aid in constructing the DT file (e.g. macros
to create a node), but not define any information that the kernel needs
to share. These may be placed directly into arch/*/boot/dts/ along with
the DT files themselves.
Acked-by: Michal Marek <mmarek@suse.cz>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
"ip" and "root" settings are useful for development
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: split into separate driver and device-tree patches]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Adding the PM configuration of PMC when the platform support suspend
function.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch adds "non-removable" property of MMC host where the eMMC device
is for Tegra platform.
And the "keep-power-in-suspend" property was used for the SDIO device that
need this to go into suspend mode (e.g. BRCM43xx series).
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This adds the power gpio key to DT and enable the wakeup of the gpio key
for the device. The Seaboard and paz00 already had the power gpio key
binding and the power key of Whistler was on KBC. So these boards' device
tree didn't include in this patch.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Set "regulator-always-on" for the SD slot on Dalmore, so that SD cards
work. This used to work, since this regulator is on by default, but was
broken by commit "ARM: tegra: dalmore: add TPS65090 node", since that
didn't specify always-on for this regulator.
In the long run, the regulators should all be hooked up to the SDHCI
device nodes. However, we haven't done that for any of the Tegra boards
yet, so to be consistent, this patch simply forces the regulator on,
rather than hooking it up and making it work differently to other boards.
Reported-by: Rhyland Klein <rklein@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Audio-related clocks need to be represented in the device tree. Update
bindings to describe which clocks are needed, and DT files to include
those clocks.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Audio-related clocks need to be represented in the device tree. Update
bindings to describe which clocks are needed, and DT files to include
those clocks.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
NVIDIA's Tegra114 reference platform Dalmore has voltage switch
regulators which are controlled by the Tegra GPIOs.
Add DT node for fixed regulators.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
NVIDIA's Tegra114 reference platform, Dalmore, uses the TPS65090 as
secondary PMICs which is mainly act as voltage switch regulator
controlled by i2c communication.
Add DT node for TPS65090.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: remove unit-address from node name since it's unique already]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Dalmore uses the TPS51632 as CPU regulator. The device is connected
on I2C5.
Add DT node for TPS51632.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch adds the node for the bq20z45 I2C gas gauge which is
compatible with the sbs-battery power supply driver.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[swarren: remove unit-address from node name since it's unique already]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
NVIDIA's Tegra114 has 6 SPI controllers. These controllers are
redesign on T114 with different register interface.
Add DT entry for spi controllers and make it compatible with
"nvidia,tegra114-spi", since they are a new incompatible design.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: fixed reg property for 3rd SPI controller]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
NVIDIA's Tegra114 SoCs have the matrix keyboard controller which
supports 11x8 type of matrix. The number of rows and columns
are configurable.
Add DT entry for KBC controller with compatibility as "nvidia,tegra114-kbc".
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add APB DMA requestor and serial aliases for serial controller.
There are two serial drivers i.e. 8250 based simple serial driver
and APB DMA based serial driver for higher baudrate and performace.
The simple serial driver is selected by compatible value
"nvidia,tegra114-uart", "nvidia,tegra20-uart", and the APB DMA based
driver is selected by compatible value "nvidia,tegra114-hsuart",
"nvidia,tegra30-hsuart".
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
NVIDIA's Tegra114 has 5 I2C controllers. These controllers have the
following changes which makes incompatible with previous hardware:
- Single clock source to I2C controller.
- Interrupt support for per packet transfer.
Add DT entry for I2C controllers and make it compatible with
"nvidia,tegra114-i2c".
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: fixed location of status property for consistency]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
NVIDIA's Tegra114 has 32 channels APB DMA controller. Add DT entry for
APB DMA controllers and make it compatible with "nvidia,tegra114-apbdma".
Tegra114 DMA controller is not compatible with Tegra30/Tegra20 DMA
controller driver as in Tegra114, the global pause also clock gate the
DMA register and hence it iw not possible to write the DMA register
with global pause.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: fixed DT node order]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch adds a device tree node for the four PWM controllers present
on Tegra114.
Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
We should be defining the PWM nodes with status as "disabled" in the
chip-specific dtsi file, since we don't know whether specific boards
will use the PWM or not. This patch fixes the PWM node status for
Tegra20 and Tegra30.
Also fixed the one user of PWM, which is the Tegra20 medcom-wide board,
so that PWM is set to "okay" in the board-specific dts file.
Signed-off-by: Andrew Chew <achew@nvidia.com>
[swarren: in medcom-wide: fixed node sort order, removed duplicate pwm:
label, fixed syntax error]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Dalmore has a built-in eMMC device and a user-accessible SD card slot.
Add device tree nodes to enable these.
Based on changes by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[swarren: added commit description, fixed DT node sort order]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This patch adds in the SDHCI nodes for the busses supported on Tegra114
boards.
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
[Rhyland added clk refs to & reordered sdhci nodes and removed spaces]
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
[swarren: fixed DT node sort order]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The USB PHY nodes are all grouped together rather than being sorted based
on reg address like all other nodes fix this.
I apologize for the churn; I should have noticed this during review of the
patches that caused this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add references to tegra_car clocks for the basic device nodes. Also remove
the clock-frequency property of the serial node as the UART driver can now
use the clock framework to obtain the frequency.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The port controller needs the apb0_pio clock enabled to be able to
work. This commit declares that on the device tree.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
All the UARTs are connected to clock gates; now that our clock driver
is able to handle them, make the switch.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit adds the corresponding DT bindings for all the AXI,
AHB, APB0 and APB1 gates.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add the ADC low and high resolution configuration and which one to use.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Macb0 node cannot be activated in generic sam9x5ek.dtsi file
as the sam9g15 does not have one.
Move the macb0 & macb1 activation in board .dts file that
support them.
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Move display timing configurations into device tree, so that the
auxdata for mxsfb driver can be killed.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Put the clock to the devicetree, so the driver can take care of it
later. Then, we don't have to do the enabling as a workaround in board
init.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
[shawn.guo: add enet_out into imx28.dtsi and overwrite it for m28evk]
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Now that a display timing binding is available, convert our almost identical
binding to use the standard binding.
This patch converts the vt8500 and wm8505 framebuffer drivers and
associated dts/dtsi files to use the standard binding as defined in
bindings/video/display-timing.txt.
There are two side-effects of making this conversion:
1) The fb node should now be in the board file, rather than the soc file as
the display-timing node is a child of the fb node.
2) We still require a bits per pixel property to initialize the framebuffer
for the different lcd panels. Rather than including this as part of the
display timing, it is moved into the framebuffer node.
I have also taken the opportunity to alphabetise the includes of each
driver to avoid double-ups.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
The zynq has a Cortex-A9 with the corresponding smp_twd timers. Use them.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Zynq is standard PMU with 2 interrupt per core.
There is also access via register which is not used right now.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Use cdns,ttc because this driver is Cadence Rev06
Triple Timer Counter and everybody can use it
without xilinx specific function name or probing.
Also use standard dt description for timer
and also prepare for moving to clocksource
initialization.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove the gpio related devicetree nodes as these are no longer required
with the move to a combined pinctrl/gpio driver.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
This patch adds pinctrl nodes to the VIA VT8500 and Wondermedia SoC dtsi
files to support the pinctrl driver.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Highlights:
* Add Lager board support
* Add ape6evm board support
* Add Bock-W board support
* Mackerel MMCIF/SDHI clean ups
* Add ethernet support to kzm9g-reference
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux2-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-boards2-for-v3.10
The merge with renesas-pinmux2-for-v3.10 was made to provide
run-time dependencies for the following changes:
ARM: shmobile: APE6EVM LAN9220 support
ARM: shmobile: APE6EVM PFC support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRW4ucAAoJENfPZGlqN0++oHQP/jpJ6AAAwuFfcfPSnpWIkJY6
cidxxBwf445EcW1OXAKez4Ki4gJ8+AcYBp39dm5nm1HUSrmJgOVgbeQ/benakUi/
5/Qgj0Hi4HmiYzrDuZo1SgBu3iHZy38KzbzpUFwBXYJW3snlM4WYET08FHzun/3j
hvWI5fEgYC4FBzbU68Vc6R1aCZM+yio1wezRz+zMjkSJ2f6dGwM16oXbh0nLgWKk
VdvAOTmNbzFIs/3frATcozBI956SJPha7SMq7YUSE0MRIcjpTtvhGnnWFyq3NQH6
JeSs7qKcXBJ8foOE333J+KGyXpMp/FgJxQo0C3N3/fbaiPH6+eE0gkRL27MUPdRy
EES9FPGSzuDEe6WPG9pUOJEbkD3BjBUuokC8LDCPrFK1jXdPtz2yAeNOAz+sLDLe
oYpmlE2D8dG7DbxrFNRrhFGgujHI4gV9I54IM58xEq3+MpzK0GS4GYYf3+Qas7ob
P5qDenAIEC5b+Ox578iRyy35kP8cwbm9BV7zLAXCLVTjWEjcAWPRi+6r9TYt7DV1
/FzW2csVqyN/ec6WljJblImty1tvV1GuuHPQ8azu6ZHlxXQDPAo5KIROTVW/ud7m
daReu65vkGwN8PMPpT/jMh38b8wGBkR9TgI2vCLOQ95PTY1UVdkyZIynUkMV5jX8
PxkEzDA3qHoMDI4/XPbD
=Zhif
-----END PGP SIGNATURE-----
Merge tag 'renesas-boards3-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards2
Third round of Renesas ARM SoC board updates for v3.10
Highlights:
* Add Lager board support
* Add ape6evm board support
* Add Bock-W board support
* Mackerel MMCIF/SDHI clean ups
* Add ethernet support to kzm9g-reference
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux2-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-boards2-for-v3.10
The merge with renesas-pinmux2-for-v3.10 was made to provide
run-time dependencies for the following changes:
ARM: shmobile: APE6EVM LAN9220 support
ARM: shmobile: APE6EVM PFC support
* tag 'renesas-boards3-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (307 commits)
ARM: shmobile: mackerel: clean up MMCIF vs. SDHI1 selection
ARM: shmobile: mackerel: add interrupt names for SDHI0
ARM: shmobile: mackerel: switch SDHI and MMCIF interfaces to slot-gpio
ARM: shmobile: mackerel: remove OCR masks, where regulators are used
ARM: shmobile: mackerel: SDHI resources do not have to be numbered
ARM: shmobile: Initial r8a7790 Lager board support
ARM: shmobile: APE6EVM LAN9220 support
ARM: shmobile: APE6EVM PFC support
ARM: shmobile: APE6EVM base support
ARM: shmobile: kzm9g-reference: add ethernet support
ARM: shmobile: add R-Car M1A Bock-W platform support
sh-pfc: r8a73a4: Remove unused GPIO bias data
ARM: shmobile: r8a73a4: Remove all GPIO enums
sh-pfc: r8a73a4: Remove function GPIOs
ARM: shmobile: r8a73a4: Remove IRQC function GPIOs
ARM: shmobile: r8a73a4: Remove SCIF function GPIOs
sh-pfc: r8a73a4: Remove IRQC function GPIOS
sh-pfc: r8a73a4: Remove SCIF function GPIOS
sh-pfc: r8a73a4: Add IRQC pin groups and functions
sh-pfc: r8a73a4: Add SCIF pin groups and functions
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds a device tree binding for random number generator present on
Broadcom BCM2835 SoC, used in Raspberry Pi and Roku 2 devices.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Highlights:
* Compilation fixes for sh7269 and for when CONFIG_BUG is not set
* sh-pfc Support for r8a73a4 SoC
* Move GPIOs handling from the PFC device to separate GPIO devices on the r8a7779 SoC
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRW4oIAAoJENfPZGlqN0++W6MP/2+++lzClm3iPneAhigO5UAB
IF0/CSLYAHjxlMW4CZWquJE6t9x5MptcAi2GmBwPwRFsQWjz6jFIHSmtEavX81IU
0k0zBf2QEHED+PhEx50V3TvDyLAf6pAWWWN/Fp5r8isLrUXAoZhY2eY6vaddFQkY
a98NC7c8t911stOs0BDeiQ9TjsR8P1uRYIPang473NOOQ8w6vf5CPh7ihcG4026A
R5AomkOZgNukF55gxi1BfUfaXpVsuBhRb5PfdzPXbNB3fOybaPSEc+rnFoCwe5DY
teQbpldHFp0wHMFYOZ+mlGqToDitLyqk1D98U7KNNAKnzX74VW4ta15pkK+Pmed+
m4a/eeJIv4y1Xfk06wwj78SvT7uW+u24iUW0mppuH/x5gGjPD9q56rA4ylguV0XF
AeVeBiA/cMlDK2k5lw087fyORvvVX4tDY5P7X7BxLCVuZRFynoNJLkXyvE/0yI3R
UvrxlajIEUVXtK1uMh4ULLbP4OiA2SMhqrLqG+JvibeFFWLY0mxj+IDRuv34/UqR
iQUMkCIjOJ2Xxcs5rWr9fRHiuUL66Xy8+FE1jL/Wkb6qldmbtcBbn9le2CUucPQ7
McXa3R8x46qMaG40b5wCxAv7W6zOcpHNl0YnwNh7ClD+BctjF2JpVLmJQZsQqyyn
FKPpzmdXD3eIL1g3R58L
=vwDo
-----END PGP SIGNATURE-----
Merge tag 'renesas-pinmux2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc2
Second round of Renesas ARM and SH based SoC pinmux updates for v3.10
Highlights:
* Compilation fixes for sh7269 and for when CONFIG_BUG is not set
* sh-pfc Support for r8a73a4 SoC
* Move GPIOs handling from the PFC device to separate GPIO devices on the r8a7779 SoC
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10
* tag 'renesas-pinmux2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (185 commits)
sh-pfc: r8a73a4: Remove unused GPIO bias data
ARM: shmobile: r8a73a4: Remove all GPIO enums
sh-pfc: r8a73a4: Remove function GPIOs
ARM: shmobile: r8a73a4: Remove IRQC function GPIOs
ARM: shmobile: r8a73a4: Remove SCIF function GPIOs
sh-pfc: r8a73a4: Remove IRQC function GPIOS
sh-pfc: r8a73a4: Remove SCIF function GPIOS
sh-pfc: r8a73a4: Add IRQC pin groups and functions
sh-pfc: r8a73a4: Add SCIF pin groups and functions
sh-pfc: r8a73a4: Add bias (pull-up/down) pinconf support
sh-pfc: r8a73a4: GPIO IRQ support
sh-pfc: r8a73a4: Support sparse GPIO numbers
sh-pfc: Add r8a73a4 pinmux support
sh-pfc: r8a7779: Split DU input and output pixel clocks
sh-pfc: r8a7779: Remove GPIO data
ARM: shmobile: r8a7779: Register GPIO devices
sh-pfc: Configure pins as GPIOs at request time when handled externally
sh-pfc: Skip gpiochip registration when no GPIO resource is found
sh-pfc: Make GPIO support optional
sh-pfc: Make function GPIOs support optional
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Some Highlights:
* Add r8a7790 SoC
* Add r8a73a4 SoC
* Migrate r8a7740 SoC from INTC to GIC
* Add thermal driver support to r8a73a4 SoC
* Add irqpin DT nodes to sh73a0 SoC
* Add SCIF support to r8a7778 SoC
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-intc-external-irq2-for-v3.10
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRWmXUAAoJENfPZGlqN0++r7YQAI47GqgjuqQsE4XUGaM12Rxz
vTpJ4l9AfDcZxnLbRG80QuMYUInhiBExH1MA3wtAmgLRNpFOOUH12rM54Y8M5oLy
AbN/rvf7ReM0eQBlBlu7TUAUxPLRMzTyo1auBXIFM3Qjp5udf5bd3eFWBduQhaIA
ltr+7czw96KpHtprbeRjR5qelFXATF9kW0rI8E9CRb6lLrHQ6BS7HO6UH5AcnB5V
8iVj/hWFV11KKsiP+BJDa8pXqFJUjAeYipYJ7wA0cTqKz3IgHnHnEcsyGmSmjHoX
NOxPZWB9b5zYNn5dXdyTlpHC592hdS4EPGuzlHceiphxFvJ5Ay83b3braU5SUd0O
ArzDg/acR2Uov35wWYPoiAkQMaf1U97TEUw4q5+bO4r+12SIt+iuevQkYx72YZjR
qVcCK895y0sMyfRafcz9Apoy8Rnimjfc+dMOebt2lHE33tXCZ4KxD+YVTeNm5OIG
/QqVZuqi4DzSpQgJwpYf9DlRCNg2PKA8r+0pBT+xRDDj+MPbw10IMHjx/ZNJthvX
r9yyupNEsa1goT7wbDHq5bJw41D5JGldYlKZz6Tz0h7eQFPdSkE6F1Usa74fMKSF
VcAlvKmb7rR/ZRWILKGrPKTAzZKedSY6RYmhJEgSxnYQYt2fmUu6bAIu09s9J6BC
XEC7K7rRuQh1C6vu/t/D
=jivx
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc2
Second round of Renesas ARM SoC updates for v3.10
Some Highlights:
* Add r8a7790 SoC
* Add r8a73a4 SoC
* Migrate r8a7740 SoC from INTC to GIC
* Add thermal driver support to r8a73a4 SoC
* Add irqpin DT nodes to sh73a0 SoC
* Add SCIF support to r8a7778 SoC
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-intc-external-irq2-for-v3.10
* tag 'renesas-soc2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (88 commits)
ARM: shmobile: r8a7790 SoC 64-bit DT support
ARM: shmobile: r8a73a4 SoC 64-bit DT support
ARM: shmobile: r8a7790 PFC support
ARM: shmobile: r8a7790 IRQC support
ARM: shmobile: r8a7790 SCIF support
ARM: shmobile: Initial r8a7790 SoC support
ARM: shmobile: r8a7779: move global functions to r8a7779.h
ARM: shmobile: r8a7740: move global functions to r8a7740.h
ARM: shmobile: sh73a0: move global functions to sh73a0.h
ARM: shmobile: sh7372: move global functions to sh7372.h
ARM: shmobile: r8a7779: remove DIV4 clocks and use fixed ratio clock
ARM: shmobile: r8a7740: use fixed ratio clock
ARM: shmobile: r8a7740: tidyup comment/implementation mismatch
ARM: shmobile: sh73a0: use fixed ratio clock
ARM: shmobile: sh7372: use fixed ratio clock
ARM: shmobile: add struct clk_ratio and fixed ratio clock macro
ARM: shmobile: sh7372: remove DIV4_ZT* clocks
ARM: shmobile: sh73a0: remove DIV4_ZT* clocks
ARM: shmobile: sh73a0: add a TWD clock
ARM: shmobile: r8a7740: Migrate from INTC to GIC
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Add tps6507x regulator device tree data to da850-evm by
adding regulator consumers with tightened constraints
and regulator-name.TPS6507x regulator handle can be obtained
by using this regulator name.
Regulator constraints are added as per da850 board file.
Regulator names are given as per maximum output voltage the
regulator is capable to provide.
for e.g. regulator name for dcdc1 is "VDCDC1_3.3V".
Also, add tps6507x PMIC I2C slave device under I2C0 node.
Tested on da850-evm.
Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Add device tree data for tps6507x regulator by adding
all tps6507x regulator nodes. Regulators are initialized
based on compatible name provided in tps6507x DT file.
All tps6507x PMIC regulator device tree nodes are placed
in a separate device tree include file (tps6507x.dtsi).
tps6507x.dtsi file is created using datasheet
http://www.ti.com/lit/ds/symlink/tps65070.pdf
Tested on da850-evm.
Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This patch adds support for the thermal controller available in
all Armada 370 boards. This controller has two 4-byte registers:
one to read the thermal sensor, the other for sensor initialization.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This patch adds support for the thermal controller available in
all Armada XP boards. This controller has two 4-byte registers:
one to read the thermal sensor, the other for sensor initialization.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Lager base board support making use of 2 GiB of memory,
the r8a7790 SoC with the SCIF0 serial port and CA15 with
ARM architected timer.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add LAN9220 support to the APE6EVM board using C and DT.
At this point the PFC driver lacks DT bindings so to
configure the PFC we use PINCTRL in C board code.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
V3 of APE6EVM base board support making use of
1 GiB of memory, the SCIFA0 serial port and
ARM architected timer.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a DT node for the SMSC 9221 ethernet chip, found on kzm9g, to its
reference implementation.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add basic Bock-W board support
More devices will be added on top of this patch after
PICNTRL and clock framework are in better shape.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Highlights:
* Compilation fixes for sh7269 and for when CONFIG_BUG is not set
* sh-pfc Support for r8a73a4 SoC
* Move GPIOs handling from the PFC device to separate GPIO devices on the r8a7779 SoC
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRW4oIAAoJENfPZGlqN0++W6MP/2+++lzClm3iPneAhigO5UAB
IF0/CSLYAHjxlMW4CZWquJE6t9x5MptcAi2GmBwPwRFsQWjz6jFIHSmtEavX81IU
0k0zBf2QEHED+PhEx50V3TvDyLAf6pAWWWN/Fp5r8isLrUXAoZhY2eY6vaddFQkY
a98NC7c8t911stOs0BDeiQ9TjsR8P1uRYIPang473NOOQ8w6vf5CPh7ihcG4026A
R5AomkOZgNukF55gxi1BfUfaXpVsuBhRb5PfdzPXbNB3fOybaPSEc+rnFoCwe5DY
teQbpldHFp0wHMFYOZ+mlGqToDitLyqk1D98U7KNNAKnzX74VW4ta15pkK+Pmed+
m4a/eeJIv4y1Xfk06wwj78SvT7uW+u24iUW0mppuH/x5gGjPD9q56rA4ylguV0XF
AeVeBiA/cMlDK2k5lw087fyORvvVX4tDY5P7X7BxLCVuZRFynoNJLkXyvE/0yI3R
UvrxlajIEUVXtK1uMh4ULLbP4OiA2SMhqrLqG+JvibeFFWLY0mxj+IDRuv34/UqR
iQUMkCIjOJ2Xxcs5rWr9fRHiuUL66Xy8+FE1jL/Wkb6qldmbtcBbn9le2CUucPQ7
McXa3R8x46qMaG40b5wCxAv7W6zOcpHNl0YnwNh7ClD+BctjF2JpVLmJQZsQqyyn
FKPpzmdXD3eIL1g3R58L
=vwDo
-----END PGP SIGNATURE-----
Merge tag 'renesas-pinmux2-for-v3.10' into boards-base
Second round of Renesas ARM and SH based SoC pinmux updates for v3.10
Highlights:
* Compilation fixes for sh7269 and for when CONFIG_BUG is not set
* sh-pfc Support for r8a73a4 SoC
* Move GPIOs handling from the PFC device to separate GPIO devices on the r8a7779 SoC
This pull request is based on a merge of:
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10
This merge is made to supply run-time dependencies for the following
patches that will bea added on top:
ARM: shmobile: APE6EVM LAN9220 support
ARM: shmobile: APE6EVM PFC support
Slow down the I2C clock speed on M28 and SPS1 as it turns out the
I2C block in i.MX28 can not operate stable enough with the bus
running at 400kHz. Note that the driver used by Freescale runs
the bus at 250kHz when 400kHz speed is selected, but the mainline
Linux kernel runs the bus at actual 400kHz and that's where it is
occasionally unstable. Play safe and run the bus at 100kHz.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This adds support for the Broadcom timer, used in the following SoCs:
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155
Updates from V6:
- Split DT portion into a separate patch
Updates from V5:
- Rebase to latest arm-soc/for-next
Updates from V4:
- Switch code to use CLOCKSOURCE_OF_DECLARE
Updates from V3:
- Migrate to 3.9 timer framework updates
Updates from V2:
- prepend static fns + fields with kona_
Updates from V1:
- Rename bcm_timer.c to bcm_kona_timer.c
- Pull .h into bcm_kona_timer.c
- Make timers static
- Clean up comment block
- Switched to using clockevents_config_and_register
- Added an error to the get_timer loop if it repeats too much
- Added to Documentation/devicetree/bindings/arm/bcm/bcm,kona-timer.txt
- Added missing readl to timer_disable_and_clear
Note: bcm,kona-timer was kept as the 'compatible' field to make it
specific enough for when there are multiple bcm timers (bcm,timer is
too generic).
Signed-off-by: Christian Daudt <csd@broadcom.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: John Stultz <john.stultz@linaro.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Introduction of new Atmel Cortex-A5: SAMA5D3 family.
- Modify AT91 Kconfig to plit ARMv4/5 and ARMv7 arch
- Modify PMC driver (clocks)
- Core SAMA5 support
- Board file, DT files and defconfig
* tag 'at91-soc' of git://github.com/at91linux/linux-at91:
ARM: at91: add defconfig for SAMA5
ARM: at91: dt: add device tree files for SAMA5D3 family
ARM: at91: introduce SAMA5 support
ARM: at91: introduce the core type choice to split ARMv4/5 and ARMv7 arch
ARM: at91: add AT91_SAM9_TIME entry to select at91sam926x_time.c compilation
ARM: at91: change name template in AT91_SOC_START macro
ARM: at91: renamme rm9200 dt file
ARM: at91: rename board-dt to more specific name board-dt-sam9
ARM: at91: move non DT Kconfig to Kconfig.non_dt
Signed-off-by: Olof Johansson <olof@lixom.net>
Provide RESET and Power regulators for the USB PHY,
the USB Host port mode and the PHY device.
Also provide pin multiplexer information for USB host
pins.
CC: Benoît Cousson <b-cousson@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
After a quiet set of fixes for 3.9-rc4, a lot of people woke up and sent
urgent fixes for 3.9. I pushed back on a number of them that got
deferred to 3.10, but these are the ones that seemed important.
Regression in 3.9:
- Multiple regressions in OMAP2+ clock cleanup
- SH-Mobile frame buffer bug fix that merged here because of maintainer MIA
- ux500 prcmu changes broke DT booting
- MMCI duplicated regulator setup on ux500
- New ux500 clock driver broke ethernet on snowball
- Local interrupt driver for mvebu broke ethernet
- MVEBU GPIO driver did not get set up right on Orion DT
- incorrect interrupt number on Orion crypto for DT
Long-standing bugs, including candidates for stable:
- Kirkwood MMC needs to disable invalid card detect pins
- MV SDIO pinmux was wrong on Mirabox
- GoFlex Net board file needs to set NAND chip delay
- MSM timer restart race
- ep93xx early debug code broke in 3.7
- i.MX CPU hotplug race
- Incorrect clock setup for OMAP1 USB
- Workaround for bad clock setup by some old OMAP4 boot loaders
- Static I/O mappings on cns3xxx since 3.2
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIVAwUAUVrxWGCrR//JCVInAQLsoQ/+IQKk3v3xOhsvLaPxYjpO1dZqwxmWHwCz
ujmpnsUabYwuVfVL982k3RTSry5brgOB75CdztOyYsnckF1ZJ3zPjBN+TQM7G/aF
1lpfUTdCEQFgWFb69G6Lr5ZIDk7co3nRJk1GFS/xi/EAlnmUY/tC1Epco2Y0z0g4
dWz34sor22lxwWkUTdgXKwynoxmmjBzZIJOhtSOeednVPxN2qUe9IDAy9qk43U3a
Xg8j4OQT59TTmAZgAB7DLlJ3BGpFvTFAeZ4sDwrCCnibmB5E9LiaYwS9vrk9SQB1
D8CYIUqcP+cGKnftCCIzgjXHYvJw8fa7NKBUw9CzusIuk+c5AbE28KZRIL4D24Oq
ImlFV4Neec3Iab6IWfD0+PQK6PkwqnvPd5IBSFO4zUv2adafl7sTASlMnNPZtWbo
gV+GNVlCyab3l1KYBPo+CQGup3UpIAs5trQoCUh7BRf4HEsL+HILr/SFRQk3GQ6H
B+3HgSleiipT8n81VDFiWY1o5KuXmjUd2qpbc0a45VtM6EFBONwqBaKew93NkDYa
oIhI6yS8aIMYPXC6ZP5R2OvKUuL+mypKKXlt9BMCnDG9mrGMks8BLumcHco+Jmkt
9p6DChibxsaH6QArAi16shFPm0VqFUI6cidgTUcY024bZSiXpBMF52mIu6SEf0/S
agIwGxpuXFg=
=oQbL
-----END PGP SIGNATURE-----
Merge tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC bug fixes from Arnd Bergmann:
"After a quiet set of fixes for 3.9-rc4, a lot of people woke up and
sent urgent fixes for 3.9. I pushed back on a number of them that got
deferred to 3.10, but these are the ones that seemed important.
Regression in 3.9:
- Multiple regressions in OMAP2+ clock cleanup
- SH-Mobile frame buffer bug fix that merged here because of
maintainer MIA
- ux500 prcmu changes broke DT booting
- MMCI duplicated regulator setup on ux500
- New ux500 clock driver broke ethernet on snowball
- Local interrupt driver for mvebu broke ethernet
- MVEBU GPIO driver did not get set up right on Orion DT
- incorrect interrupt number on Orion crypto for DT
Long-standing bugs, including candidates for stable:
- Kirkwood MMC needs to disable invalid card detect pins
- MV SDIO pinmux was wrong on Mirabox
- GoFlex Net board file needs to set NAND chip delay
- MSM timer restart race
- ep93xx early debug code broke in 3.7
- i.MX CPU hotplug race
- Incorrect clock setup for OMAP1 USB
- Workaround for bad clock setup by some old OMAP4 boot loaders
- Static I/O mappings on cns3xxx since 3.2"
* tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: cns3xxx: fix mapping of private memory region
arm: mvebu: Fix pinctrl for Armada 370 Mirabox SDIO port.
arm: orion5x: correct IRQ used in dtsi for mv_cesa
arm: orion5x: fix orion5x.dtsi gpio parameters
ARM: Kirkwood: fix unused mvsdio gpio pins
arm: mvebu: Use local interrupt only for the timer 0
ARM: kirkwood: Fix chip-delay for GoFlex Net
ARM: ux500: Enable the clock controlling Ethernet on Snowball
ARM: ux500: Stop passing ios_handler() as an MMCI power controlling call-back
ARM: ux500: Apply the TCPM and TCDM locations and sizes to dbx5x0 DT
fbdev: sh_mobile_lcdc: fixup B side hsync adjust settings
ARM: OMAP: clocks: Delay clk inits atleast until slab is initialized
ARM: imx: fix sync issue between imx_cpu_die and imx_cpu_kill
ARM: msm: Stop counting before reprogramming clockevent
ARM: ep93xx: Fix wait for UART FIFO to be empty
ARM: OMAP4: PM: fix PM regression introduced by recent clock cleanup
ARM: OMAP3: hwmod data: keep MIDLEMODE in force-standby for musb
ARM: OMAP4: clock data: lock USB DPLL on boot
ARM: OMAP1: fix USB host on 1710
Conflicts:
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
This merge is to provide r8a73a4 SoC files, which are added in the
soc branch and depended on by r8a73a4 pfc-changes which are to
be added to the pinmux branch.
The r8a7790 SoC supports LPAE and has memory window up to
0x2ffffffff. Convert to 64-bit addresses by enlarging
#addr-cells and #size-cells to 2.
Signed-off-by: Takashi Yoshii <takashi.yoshii.zj@renesas.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The r8a73a4 SoC supports LPAE and has memory window up to
0x2ffffffff. Convert to 64-bit addresses by enlarging
#addr-cells and #size-cells to 2.
Signed-off-by: Takashi Yoshii <takashi.yoshii.zj@renesas.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add IRQC interrupt controller support to r8a7790 by
hooking up a single IRQC instances to handle 4 external
IRQ signals. The IRQC controller is tied to SPIs of
the GIC. On r8a7790 the external IRQ pins routing is
handled by the PFC which is excluded from this patch.
Both platform devices and DT devices are added in this
patch. The platform device versions are used to provide
a static interrupt map configuration for board code
written in C.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add initial support for the r8a7790 SoC including:
- Single Cortex-A15 CPU Core
- GIC
- Architecture timer
No static virtual mappings are used, all the components
make use of ioremap(). DT_MACHINE_START is still wrapped
in CONFIG_USE_OF to match other mach-shmobile code.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
You can get current thermal by
> cat /sys/class/thermal/thermal_zone?/temp
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add DT nodes for the 4 irqpin interrupt controllers on sh73a0. We add them
to sh73a0.dtsi, which is also used by configurations, doing all their
device instantiation from board the .c code. We rely on the fact, that
such configurations don't instantiate devices from the device-tree.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add initial support for the R8A7778 R-Car M1A SoC.
No static virtual mappings are used, all the components
make use of ioremap().
DT_MACHINE_START is still wrapped
in CONFIG_USE_OF to match other mach-shmobile code.
It is based on v1.0 datasheet
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add IRQC interrupt controller support to r8a73a4 by
hooking up two IRQC instances to handle 58 external
IRQ signals. There IRQC controllers are tied to SPIs
of the GIC. On r8a73a4 exact IRQ pin routing is handled
by the PFC which is excluded from this patch.
Both platform devices and DT devices are added in this
patch. The platform device versions are used to provide
a static interrupt map configuration for board code
written in C.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
V3 of initial support for the r8a73a4 SoC including:
- Single Cortex-A15 CPU Core
- GIC
- Architecture timer
No static virtual mappings are used, all the components
make use of ioremap(). DT_MACHINE_START is still wrapped
in CONFIG_USE_OF to match other mach-shmobile code.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
In the conversion to pinctrl, an error in the pins for the rebuild
LED was introduced. This patch assigns the correct pins and includes
the correct name for the LED in kirkwood-iomega_ix2_200.dts.
Signed-off-by: Nigel Roberts <nigel@nobiscuit.com>
Cc: <stable@vger.kernel.org> # v3.8.x
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Instead of using static address definition, get reset address from
device tree with mapping, so that core_initcall mxs_arch_reset_init()
can be killed.
The "rtc" clock code in mxs_arch_reset_init() seems to be zombie, since
there is no clk lookup defined in clock driver at all. Remove it
together.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Instead of using the static definitions, get clkctrl and digctl base
addresses with mapping from device tree.
Use macro on variable is not nice, but it's done here to save huge
pointless diff stat.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Change call clk_get_sys() to of_clk_get() to look up timrot clock from
device tree, so that the clk_register_clkdev() call for timrot can be
saved in clock driver.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add the three external LED definitions to the device tree file on
the Mirabox.
The Mirabox user guide calls out one as a power LED, and the other
two are defined for WiFi, but as the current mwifiex drivers don't
have LED support, we make them status LEDs.
These have been tested working by writing to the appropriate
/sys/class/leds trigger.
Signed-off-by: Ryan Press <ryan@presslab.us>
Tested-by: Neil Greatorex <neil@fatboyfat.co.uk>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The orion5x SoC includes DMA functionality, so lets enable that
and turn it on by default.
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The orion5x SoC also includes a USB EHCI componment so lets add that
to the dtsi (disable by default incase the pins are not broken out).
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Device tree based guruplug boards still use mvsdio platform_data and
kirkwood_sdio_init to enable sdio. DT support for sdio is already there,
so make use of it.
This also fixes mvsdio accidentially breaking nand by configuring mpp0
to gpio, while used also by nand (nand_io2 on mpp0).
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Soeren Moch <smoch@web.de>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Marvell Armada 370 Reference Design board has a software-controlled
button on the front side, marked as "SW".
This patch adds minimal support for this button.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
We previously relied on the bootloader to do the muxing of the UART for
the Cubieboard. Don't rely on it anymore and use pinctrl.
Also remove uart1, as it is not enabled by default and it's not exposed
on the board headers.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
We previously relied on the bootloader to do the muxing of the UART for
the Hackberry. Don't rely on it anymore and use pinctrl.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Emilio López <emilio@elopez.com.ar>
The Allwinner A10 SoC has 8 available UARTs, which is 6 more than on the
A13, so add the missing UARTs to the sun4i-a10 dtsi.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Emilio López <emilio@elopez.com.ar>
Both A10 and A13 Allwinner SoCs have a Synopsys APB uart3 device
available, so add it to the sunxi.dtsi file
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Emilio López <emilio@elopez.com.ar>
The UART0 is only available on the Allwinner A10 SoCs, and not on the
A13, so move the uart0 node to sun4i-a10.dtsi.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Emilio López <emilio@elopez.com.ar>
Tested-by: Emilio López <emilio@elopez.com.ar>
The other architecture use serial@address for their uart nodes, so
rename our uart dt nodes to be consistent
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
It will be especially useful when we will have the clock definitions in
the device tree.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Emilio López <emilio@elopez.com.ar>
Tested-by: Emilio López <emilio@elopez.com.ar>
- mvebu
- interrupt fix
- DT pinctrl definition for sdio
- kirkwood
- chip-delay for GoFlex Net (fix reading nand)
- set mvsdio unused pins to invalid value for legacy boards (0 is valid)
- orion5x
- fix typo in gpio parameters
- use correct irq in dtsi
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
iQEcBAABAgAGBQJRVIcVAAoJEAi3KVZQDZAev1wH/0oIYEZvAeE8Nh49bn7EKgwH
ef44bin9g/JkEZ/3YndUE+1wqq/4nBaJN2IWGsPmbKGZFWNaoaPG1gFr0VsOepge
GpKdwrxUMAgIzLO+4FtN85Zy3Qe4Jn8YWjJcZXZbl404cyQx5bDID0clYsn0m2jW
F6nWva5ULAbWNBsUpRQ3h8nYfKi9QsWvhOgFxsaAiR3VCpLOk+MKK7Y0cwqpi60K
p2ALUultfXGckqJyFCoZNHwN52dlllsXD09i/lRzM91nT/VEPzwWNhPcoNjwiQwu
qfloTU97Lfq7168G4PTSEq8V7LP/NLbAlwwJ3VW3HCrtVTefSQFdUF9EA9bjl8I=
=EExD
-----END PGP SIGNATURE-----
Merge tag 'mvebu_fixes_for_v3.9_round2' of git://git.infradead.org/users/jcooper/linux into fixes
From Jason Cooper <jason@lakedaemon.net>:
mvebu fixes for v3.9 (round 2)
- mvebu
- interrupt fix
- DT pinctrl definition for sdio
- kirkwood
- chip-delay for GoFlex Net (fix reading nand)
- set mvsdio unused pins to invalid value for legacy boards (0 is valid)
- orion5x
- fix typo in gpio parameters
- use correct irq in dtsi
* tag 'mvebu_fixes_for_v3.9_round2' of git://git.infradead.org/users/jcooper/linux:
arm: mvebu: Fix pinctrl for Armada 370 Mirabox SDIO port.
arm: orion5x: correct IRQ used in dtsi for mv_cesa
arm: orion5x: fix orion5x.dtsi gpio parameters
ARM: Kirkwood: fix unused mvsdio gpio pins
arm: mvebu: Use local interrupt only for the timer 0
ARM: kirkwood: Fix chip-delay for GoFlex Net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add support for NETGEAR ReadyNAS Duo v2 (Hardware specs available
here: http://natisbad.org/NAS/). Almost everything is supported via
provided .dts. A board-readynas.c file is nonetheless required for
device not only converted to DT (Gbit controller).
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Tested-By: Arnaud Ebalard <arno@natisbad.org>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The previous configuration used the wrong "clk" pin. Without this
change mv_sdio worked because the bootloader would set the pin up, but
with a bootloader that does not set the pin, mv_sdio fails to detect any
card.
I have tested this change using a mwifiex_sdio wireless network adapter
over the SDIO interface.
Signed-off-by: Ryan Press <ryan@presslab.us>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The crypto functionality in the orion5x dtsi uses the Ethernet IRQ and
so things do not work and there is much grumbling at boot time.
The IRQ for the crypto should be 28, and not 22, and that is what this
patch corrects.
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
orion5x.dtsi is missing the gpio alias as well as including a typo
('ngpio' instead of 'ngpios') that prevented the orion-gpio driver
from loading. Also missing were the interrupt-controller properties.
This patches resolves those glitches.
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This fixes "Too few good blocks within range" issues on GoFlex Net by setting
chip-delay to 40.
The basic problem was discussed at http://forum.doozan.com/read.php?2,7451
Signed-off-by: Eric Hutter <hutter.eric@gmail.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Cc: <stable@vger.kernel.org> # v3.6.x
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
- Get TCPM and TCDM locations from the device tree
- Skip passing the ios_handler for the MMCI
- Enable the ethernet clock for Snowball
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJRU00yAAoJEEEQszewGV1zZuQQAL5gVamIuoU7QuKPGxISMIyh
qdXZ1+V8qQnw1gg6yRSUgg7e1vGgAsC0jDGue/nC98f5pdibqb4440u59s2xQaDt
JOEw9E4mnP8/AAzszUJ8LLjER3HUT5R39nytSh94/q+uOu0ZwD8IQMCzxBz3euyS
f5Wcn20Rzr1r0mfBDwzbAn+CebiMP/gTjrRxBT1LdIhlTDIwxvcJ14vbH3pzSgeb
Oy+Qq+D3lXn2teX23eZLxRJh+Tw7L9xUapag84lmtn8KaF7MPG2OYIPjpA/F8KNk
Qdbrh3rkEVlDSTNSS0CLheFJN4Ze9D40dOsEvb8N30BbP0Lr6JzeYI5LhV+Whemr
W075XV+YA5UO41sffBuoy7wWPCHoCw7StpCk8ckjzKpHj283trMFQAXwmwJqie4w
8+VCVzg7rgROby3GFP/L/9Tl+aMneEn1FXORUYwrv1gZRQFtmnEoqSohG5VsETr1
LuO6R02/EZ6I1RkKc6xDslkaAHLrV+8Ai9eDqpjhqt3ElINGWZcaAJwBxBCVctDw
ANZGsupGcJxqTaNk6s5bBy+S6GG7c8b6NUUramqd3vMEbjHRw86oEXOx38dlXac+
1lMItIAZMRDROgNMg9OftyzFM40jaBjORxGyhScpxz/h+1fM9DjZp3n/8ySwdeTc
CLVbfFjFlUi9mKp0/yxH
=v6nX
-----END PGP SIGNATURE-----
Merge tag 'ux500-fixes-for-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into fixes
From Linus Walleij <linus.walleij@stericsson.com>:
Fixes boot regressions on Device Tree:
- Get TCPM and TCDM locations from the device tree
- Skip passing the ios_handler for the MMCI
- Enable the ethernet clock for Snowball
* tag 'ux500-fixes-for-v3.9' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: Enable the clock controlling Ethernet on Snowball
ARM: ux500: Stop passing ios_handler() as an MMCI power controlling call-back
ARM: ux500: Apply the TCPM and TCDM locations and sizes to dbx5x0 DT
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
During the introduction of the Allwinner SoC platforms, sunxi was
initially meant as a generic name for all the variants of the Allwinner
SoC.
It was ok at the time of the support of only the A10 and A13 that
look pretty much the same; but it's beginning to be troublesome with
the future addition of the Allwinner A31 (sun6i) that is quite
different, and would introduce some weird logic, where sunxi would
actually mean in some case sun4i and sun5i but without sun6i...
Moreover, it makes the compatible strings naming scheme not consistent
with other architectures, where usually for this kind of compability, we
just use the oldest SoC name that has this IP, so let's do just this.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This fixes a regression introduced by commit:
05ec260 mfd:db8500-prcmu: update resource passing
All DBx5x0 based SoCs have access to two Tightly Coupled Memory
(TCM) locations based on the PRCMU itself. One area from program
memory (TCPM) and one for data memory (TCDM). The PRCMU needs to
know where these are in order to function correctly. However,
these are currently passed though platform device resources, which
can only be obtained if Device Tree booting isn't in use. Thus we
must also support them in DT by supplying them through the PRCMU
node.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Conflicts:
include/net/ipip.h
The changes made to ipip.h in 'net' were already included
in 'net-next' before that header was moved to another location.
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch series covers both ASoC and extcon subsystems and fixes an
interaction between the HPDET function and the headphone outputs - we
really shouldn't run HPDET while the headphone is active. The first
patch is a refactoring to make the extcon side easier.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRUcMYAAoJELSic+t+oim9PkAP/RQWC98LrD3kQgVk22MIDdyk
P7dr37AePy+nMHP/sp3XIVyeD6pwuRWrlf31jAgMsXSb/+8ymJ3oO3t6aPUa9V9+
KsxxoSUW+/ZO+88aK4r/w/Y45XMqMXsoEwllIxZoEpHXhDIxYFyF8wloPBXLzzbw
AALowigrNbeYuijr5R1oV+kUOcT8DpzbamoK0jSbpdBdoPEP3ypD/yJTdi/RSyu/
ELRNZFy4jUw2B3HVOB1YxUeCPpPA63u1oTypFgD7XrQX5v4MDuWyCv5bbBd7KhBk
vbK/PHti5CMvi5RbA2EHbkI+n/Lb1qfnxIggN5BaSOQ1tlqrHnMlHYoSE/Sjterh
TDGyYDNrWU1Wve2NTDJEd8oECPwm+8ABBnRYgwtnth/4D/EFkT+6Pv8FuIlYg1ku
Tj/jwS2q/q26WfssDOph/GfUXtaagMALY99yy/HXM9RPYztOnUyvJIXLzKUUdapT
KluChggzbj5ytsSy3L808BkgDxYTwHxva4q+n0ST4hDIeqe95HyE8gZA8jrYOf7T
oA4tsBL3i0YGkPoPkVhMY9qeV0AOwDVlZioGP9Qcs8EI/Z9Bri8NZ4iW8VWkNoTt
QG7EyuJy90VI/XvGgpITXKXxWQStMZG4+df6pXcn1h47K6ujtDyK/PBBt3t0OPCp
WihSDHwuFQPSDWYULbZQ
=gc7f
-----END PGP SIGNATURE-----
Merge tag 'arizona-extcon-asoc' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc into char-misc-next
Mark writes:
ASoC/extcon: arizona: Fix interaction between HPDET and headphone outputs
This patch series covers both ASoC and extcon subsystems and fixes an
interaction between the HPDET function and the headphone outputs - we
really shouldn't run HPDET while the headphone is active. The first
patch is a refactoring to make the extcon side easier.
Add device tree files for the SAMA5D3 family (SAMA5D31, SAMA5D33, SAMA5D34 and
SAMA5D35).
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The SSBI bus is exclusive to the Qualcomm MSM targets, and all SoCs
using it will be using device tree. Convert this driver to indentify
with device tree.
This makes the bus probing a good bit simpler, since the attaching of
child nodes can be represented directly in the devicetree, rather than
having to be inferred by name.
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Four patches for arm-soc this week:
- Kevin Hilman is no longer reachable under his previous email address.
He submitted the patch earlier, but nobody felt responsible to pick
it up.
- One Tegra fix for an incorect register address in device tree.
- IMX multiplatform support exposes a configuration option that
leads to unbootable kernels on all other machines and that needs
to depend on that platform.
- A nontrivial bug fix for the setup of the mxs video output.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIVAwUAUVBQf2CrR//JCVInAQJwyRAA0qzt+jbn+ezvLpeWvrgdEVLikiAieVyt
HmSex/pEWh2ytIkrX2maHv5Oov9QmX7v4ZEU2WtdvMv5YERsT7/y1hjHaZTLcdmH
11ogfVwTRbrNVWOb41ofdd3rUVgZfgzCGQ0rfEua3wLRK6AetZJxkqsuGXRaqjdm
BBbmgKAmLsLeM3/aBzeuFint1+EDY74WBMxgqkwUretefKFMxzcBaqhoR+FNDIdV
YaYbOocq45LsOa44gxlF6pmJkZsOsB2pqAjoANm5KtZlphTEpDD1C/wXvBaVAOBh
8mCuk2mHEyZsyLrufh/ZywaPcDaUMDwpO1zidATwaRCf6qWOr3jtWiCtQo4FeNYS
o+kkYtELyAEvwDQuljghviq0p+z2vpnk52sYdXkYW8Pgz5TqhK+Gu2ywaeiqeT2B
cbLGG32lVgJnmWOOXI7Z6MjekgKx5arx7z6Br+1pTT/fE44DgE+CtabEsCdcpFWG
ftC7FdxZabDUhfynSaO43tgKhdVv2XpVobG3iW2RYJOWm2dJSxulZg9+jypdxITm
VX3kPar+mjvwyf3svsGIc65SVaayR6pfiLzV8qBtR3trFRbIlrI7vo21d2tFtuS8
PfAR+9VHkeOdjVKDbu1sl7YycWz03xq4cM9XPFhvrobeFXb5OFwDwLWn4DZR5ZWY
iJSMJkaBSww=
=F6UW
-----END PGP SIGNATURE-----
Merge tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC bug fixes from Arnd Bergmann:
"Four patches for arm-soc this week:
- Kevin Hilman is no longer reachable under his previous email
address. He submitted the patch earlier, but nobody felt
responsible to pick it up.
- One Tegra fix for an incorect register address in device tree.
- IMX multiplatform support exposes a configuration option that leads
to unbootable kernels on all other machines and that needs to
depend on that platform.
- A nontrivial bug fix for the setup of the mxs video output."
* tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
MAINTAINERS: update email address for Kevin Hilman
ARM: tegra: fix register address of slink controller
ARM: imx: add dependency check for DEBUG_IMX_UART_PORT
ARM: video: mxs: Fix mxsfb misconfiguring VDCTRL0
The clock frequency of xxti and xusbxti clocks is dependent on the
frequency of the on-board oscillator that is used to generate these
clocks. So allow the frequency of these clocks to be specfied from
device tree.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
For all supported peripheral controllers on Exynos5440, add clock
lookup information.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
For all supported peripheral controllers on Exynos5250, add clock
lookup information.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
For all supported peripheral controllers on Exynos4 SoCs, add clock
lookup information.
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add clock controller nodes for EXYNOS4210, EXYNOS4x12, EXYNOS5250
and EXYNOS5440 SoCs.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJRTWrNAAoJEBx+YmzsjxAgLXoP/ie8pp1hvOAoboeyv3X+S9Q5
Yk3El79Zs6FHQDwLLHyaxNaDCjsJ+jsp6FYpykKibGUnhiSK8pqzurpHEbn3do+d
hNtK4lfday0e+PlI+blWP/78o5MpaSDMSyWUvOofu76xx1lX5Vwlkc7WlxjCksYK
kAUQ4O6Kyz/WTx1Nads82GGvcPSxHddotcR0lwm8/MpaP0sCZ0Y1BHxVuW6/N6QW
S5kv1Sv8cF+xUB8ffDYnDw+HAzb14akSJJyNIHvQWeTyKw5sbO2G8der0YG/UKEX
JLw9Fu5DqKPqXkecFQ2/5c0AUyyd5RsGS9vnXrrK+07Kw3EHYojPMhSGS1m33Dry
9USOADKAMLGtd6LcssA9c1OS/LEa5jBov67e0xEgXOVKJNNhy9zJYmc0z4vQLj4V
ip64aeMkAqhDQwlMYsWzja5NsnpTHYYj0xf7jD8KZ3T0r+CdUYxeIePQ+rChqDwS
wh8AkGxzegC/pm5RWx7fHaY37VT/nyFqG3oEVbKQ/slOdWcyjwu+/MwwqNmwHlAG
0V5DJK+KcGI6mG7+y0ecqLudba5KlquPpaT6uXw93fIjMIizZHuAeL4Es64ePt6e
6JttC9DCXvlMiyDFkPc9qbXxJMg59ayCm6LJiao0HEcRbhgurl9Cl1XDFCpUX12v
3/Fw25lCP7BwNezaLBDZ
=DBFJ
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt-for-3.10' of git://github.com/mripard/linux into next/dt
From Maxime Ripard <maxime.ripard@free-electrons.com>:
Allwinner sunxi DT additions for 3.10
* tag 'sunxi-dt-for-3.10' of git://github.com/mripard/linux:
arm: sunxi: Add clock definitions for the new clock driver
ARM: sunxi: dt: Add support for the PineRiver Mini X-plus
sunxi: a10-cubieboard: Add user LEDs to the device tree
sunxi: a13-olinuxino: Add user LED to the device tree
sunxi: dts: Report the pinctrl nodes as gpio-controllers
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This introduces proper clock definitions on sunxi.dtsi, to be used
with the new clock driver for sunxi.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Fix typo on register address of slink3 controller where register
address is wrongly set as 0x7000d480 but it is 0x7000d800.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The msm timer binding I wrote is bad. First off, the clock
frequency in the binding for the dgt is wrong. Software divides
down the input rate by 4 to achieve the rate listed in the
binding. We also treat each individual timer as a separate
hardware component, when in reality there is one timer block
(that may be duplicated per cpu) with multiple timers within it.
Depending on the version of the hardware there can be one or two
general purpose timers, status and divider control registers, and
an entirely different register layout.
In the next patch we'll need to know about the different register
layouts so that we can properly check the status register after
clearing the count. The current binding makes this complicated
because the general purpose timer's reg property doesn't indicate
where that status register is, and in fact it is beyond the size
of the reg property.
Clean all this up by just having one node for the timer hardware,
and describe all the interrupts and clock frequencies supported
while having one reg property that covers the entire timer
register region. We'll use the compatible field in the future to
determine different register layouts and if we should read the
status registers, etc.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJRRwdkAAoJENfPZGlqN0++O8UP+wUKtVnRxGnVDtOM5MZGUE8N
bJeNmsz/z2On6k8KCyRFUkrw3jhoJnNrz3+fJEMSXASdqix5HO3zXXbMWASIUbiI
y2g/blh6RmnEjogD4V/JxfjgH7Y3WaDqXIbgbetwYd4KmfqzGvNfi5Qmt4FA2iMV
iP1DVgecRQ6tjhSp4oPCZ4o3xhCQfQu/20vkBhBIg1Bsmu7IOfGcLA3XObAopGBW
iYAjs6daD5b3HSxVpeV7c7fYhGpZFRH8k3QqGUjRE6hI8ohpTNd+eEQHWXFHcbg5
lvRSNM+Ic7xk//xxqJh1rle4W4VqTF/8jGWnC1WXI5dXV0kbdwO0D/gQCos7sQDw
NaeEK5mFZQhGfbrlFx4WA/tWJKGJBCiRW1mOLLZ3MSDDKqeuTT7ngnvAWG9o5qBp
jfczsGEiRKt4lySssB8fYg/HAICkFoxABShgmBVZTgjPbHpms0v51Q3fWkvOZpVy
t3AOGBM70NEBiLyfylu8BUAe2ZE3/joPd0IA2rEEeAQESv28p/H00pQIBV1PrmTC
3QNTmVcTOnfU/AsMa8fn2rI4R58ziU2kX854juIi+hadwVo7p1XFcYgiBZCbxtHC
/9eSkYjW7g2TZAnClc3Zm9UNsS1I+zcYPD05Kl5iiw/yegeBLJ5E6PbigYHWlWdP
jdzobzjCd6VlgGxJ17Rq
=s7aA
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
From Simon Horman <horms+renesas@verge.net.au>:
Renesas ARM-based SoC updates for v3.10
* tag 'renesas-soc-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (43 commits)
r8a7779: Add Display Unit clock support
ARM: shmobile: R8A7779: use gic_iid() in SATA IRQ resource
ARM: mach-shmobile: r8a7779: add SATA support
ARM: mach-shmobile: r8a7779: SATA DT configuration
ARM: shmobile: r8a7779: add Thermal support on DT
ARM: shmobile: tidyup chip series definition order for r8a7740/r8a7779
ARM: shmobile: r8a7779: use gic_iid macro
ARM: shmobile: r8a7779: fixup DT machine name
ARM: shmobile: r8a7779: fixup dtsi typo
ARM: shmobile: add gic_iid macro for ICCIAR / interrupt ID
ARM: mach-shmobile: r8a7740: Add DT names to clock list
ARM: shmobile: Remove unused hotplug.c
ARM: shmobile: Rearrange r8a7779 cpu hotplug code
ARM: shmobile: Use sh73a0-specific cpu disable code
ARM: shmobile: Update r8a7779 to use scu_power_mode()
ARM: shmobile: Update r8a7779 to check SCU for hotplug
ARM: shmobile: Use R8A7779_SCU_BASE with TWD
ARM: shmobile: Rework SH73A0_SCU_BASE IOMEM() usage
ARM: shmobile: Fix base address readout in headsmp-scu.S
ARM: shmobile: r8a7779: Remove lan from dtsi
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
I2C. Also some cleanup of some unneeded properties and conflicting
nodes.
One more DT-only board based on at91rm9200.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJRSyP1AAoJEAf03oE53VmQVr4IAJKl8rITnS3rmYYGmFo+cIGl
HkaDM7ljf726hW2bmmcTu1zQLLsdP3EY7qOmuoUN5J8uWSV67Yujc3C0ypqgC2ve
vwWEKuPB8N6utPTWl9eLCvTp+DTKDaq6otfcXFj432tWLWdc0DYKlkaiVfePSChn
hLFFeuIj3XFCIxVJ+Tz14+/b1MC+jswe4TMCvGKE3d4aZ1dgWfS9YhmNjQ0hB1rP
BW0A7RIBW366OUCzvEkKI1NZ8MzKO6ghJMeBpLHuD3I8GJGaF9NhZXi6v7SJVS9i
IdEwXdrYY+TzpllnF9imwhvPK5d6QbcqNVV5Gie+aFwZJTYt4ufPAEIH5rd67jo=
=n+O8
-----END PGP SIGNATURE-----
Merge tag 'at91-dt' of git://github.com/at91linux/linux-at91 into next/dt
From Nicolas Ferre <nicolas.ferre@atmel.com>:
DT modifications for at91rm9200 and at91sam9x5 SoCs, mainly around
I2C. Also some cleanup of some unneeded properties and conflicting
nodes.
One more DT-only board based on at91rm9200.
* tag 'at91-dt' of git://github.com/at91linux/linux-at91:
ARM: at91/at91sam9x5cm: add 1-wire chip on CM board
ARM: at91/at91sam9x5ek: i2c1 and i2c2 conflict with macb and lcd
ARM: at91/dt: gpio-keys: remove address-cells and size-cells properties
ARM: at91: add MPA 1600 DT board
ARM: at91: add pinctrl nodes to i2c-gpio on RM92000 DT
ARM: at91: add TWI bindings to RM9200 DT
ARM: at91: dt: at91sam9x5: add i2c-gpio pinctrl
ARM: at91: dt: at91sam9x5: add i2c pinctrl
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This add the 1-wire chip present on the CM board to the DTS.
As the pin is also used by leds, it's disabled by default.
If the board really wants it, it can be enabled in the board DTS.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
On at91sam9x5ek, macb0 is enabled, so it conflicts with i2c2 (PB4)
same for i2c1, (conflicts with LCD).
Moreover, only i2c0 is used on this board.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Gpio-keys nodes are not using the "reg" property in their sub nodes.
So, there is no need to define #address-cells and #size-cells properties
in gpio-keys nodes: we remove them.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
[nicolas.ferre@atmel.com: remove unneeded address-cells and size-cells to gpio-keys]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
GPIO pins used by i2c-gpio must be set to multi drive
(open drain) to work properly.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
i2c-gpio is sometimes used in place of i2c-at91.
This adds the pin muxes for the gpios.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This adds the at19 i2c controller pin muxes for at91sam9x5 based boards.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Fix several device-tree bindings, that haven't been updated for newest
versions of respective drivers, and device names and pin numbers, left over
from non-DT and old pinctrl versions.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
