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ARM: shmobile: add R8A7778 basis support
Add initial support for the R8A7778 R-Car M1A SoC. No static virtual mappings are used, all the components make use of ioremap(). DT_MACHINE_START is still wrapped in CONFIG_USE_OF to match other mach-shmobile code. It is based on v1.0 datasheet Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Kuninori Morimoto
Simon Horman
parent
7653c318b7
commit
ccb7cc749f
35
arch/arm/boot/dts/r8a7778.dtsi
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35
arch/arm/boot/dts/r8a7778.dtsi
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@ -0,0 +1,35 @@
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/*
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* Device Tree Source for Renesas r8a7778
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* based on r8a7779
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Simon Horman
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "renesas,r8a7778";
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cpus {
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cpu@0 {
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compatible = "arm,cortex-a9";
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};
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};
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gic: interrupt-controller@fe438000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xfe438000 0x1000>,
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<0xfe430000 0x100>;
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};
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};
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@ -33,6 +33,12 @@ config ARCH_R8A7740
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select CPU_V7
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select SH_CLK_CPG
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config ARCH_R8A7778
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bool "R-Car M1 (R8A77780)"
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select CPU_V7
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select SH_CLK_CPG
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select ARM_GIC
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config ARCH_R8A7779
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bool "R-Car H1 (R8A77790)"
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select ARCH_WANT_OPTIONAL_GPIOLIB
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@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
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obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
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obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o
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obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
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obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o
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obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
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obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o
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91
arch/arm/mach-shmobile/clock-r8a7778.c
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91
arch/arm/mach-shmobile/clock-r8a7778.c
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@ -0,0 +1,91 @@
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/*
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* r8a7778 clock framework support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* based on r8a7779
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/io.h>
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#include <linux/sh_clk.h>
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#include <linux/clkdev.h>
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#include <mach/common.h>
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#define MSTPCR0 IOMEM(0xffc80030)
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#define MSTPCR1 IOMEM(0xffc80034)
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#define MSTPCR3 IOMEM(0xffc8003c)
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#define MSTPSR1 IOMEM(0xffc80044)
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#define MSTPSR4 IOMEM(0xffc80048)
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#define MSTPSR6 IOMEM(0xffc8004c)
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#define MSTPCR4 IOMEM(0xffc80050)
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#define MSTPCR5 IOMEM(0xffc80054)
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#define MSTPCR6 IOMEM(0xffc80058)
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/* ioremap() through clock mapping mandatory to avoid
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* collision with ARM coherent DMA virtual memory range.
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*/
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static struct clk_mapping cpg_mapping = {
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.phys = 0xffc80000,
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.len = 0x80,
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};
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static struct clk clkp = {
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.rate = 62500000, /* FIXME: shortcut */
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.flags = CLK_ENABLE_ON_INIT,
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.mapping = &cpg_mapping,
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};
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static struct clk *main_clks[] = {
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&clkp,
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};
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enum {
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MSTP016, MSTP015,
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MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */
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[MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */
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};
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static struct clk_lookup lookups[] = {
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/* MSTP32 clocks */
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CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
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CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
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};
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void __init r8a7778_clock_init(void)
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{
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int k, ret = 0;
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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if (!ret)
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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shmobile_clk_init();
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else
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panic("failed to setup r8a7778 clocks\n");
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}
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28
arch/arm/mach-shmobile/include/mach/r8a7778.h
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28
arch/arm/mach-shmobile/include/mach/r8a7778.h
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@ -0,0 +1,28 @@
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/*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __ASM_R8A7778_H__
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#define __ASM_R8A7778_H__
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extern void r8a7778_add_standard_devices(void);
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extern void r8a7778_add_standard_devices_dt(void);
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extern void r8a7778_init_delay(void);
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extern void r8a7778_init_irq(void);
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extern void r8a7778_init_irq_dt(void);
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extern void r8a7778_clock_init(void);
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#endif /* __ASM_R8A7778_H__ */
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167
arch/arm/mach-shmobile/setup-r8a7778.c
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167
arch/arm/mach-shmobile/setup-r8a7778.c
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@ -0,0 +1,167 @@
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/*
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* r8a7778 processor support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/irqchip.h>
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#include <linux/sh_timer.h>
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#include <mach/irqs.h>
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#include <mach/r8a7778.h>
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#include <mach/common.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/cache-l2x0.h>
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/* TMU */
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static struct resource sh_tmu0_resources[] = {
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DEFINE_RES_MEM(0xffd80008, 12),
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DEFINE_RES_IRQ(gic_iid(0x40)),
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};
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static struct sh_timer_config sh_tmu0_platform_data = {
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.name = "TMU00",
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.channel_offset = 0x4,
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.timer_bit = 0,
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.clockevent_rating = 200,
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};
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static struct resource sh_tmu1_resources[] = {
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DEFINE_RES_MEM(0xffd80014, 12),
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DEFINE_RES_IRQ(gic_iid(0x41)),
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};
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static struct sh_timer_config sh_tmu1_platform_data = {
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.name = "TMU01",
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.channel_offset = 0x10,
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.timer_bit = 1,
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.clocksource_rating = 200,
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};
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#define PLATFORM_INFO(n, i) \
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{ \
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.parent = &platform_bus, \
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.name = #n, \
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.id = i, \
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.res = n ## i ## _resources, \
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.num_res = ARRAY_SIZE(n ## i ##_resources), \
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.data = &n ## i ##_platform_data, \
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.size_data = sizeof(n ## i ## _platform_data), \
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}
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struct platform_device_info platform_devinfo[] = {
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PLATFORM_INFO(sh_tmu, 0),
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PLATFORM_INFO(sh_tmu, 1),
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};
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void __init r8a7778_add_standard_devices(void)
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{
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int i;
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
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if (base) {
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/*
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* Early BRESP enable, Shared attribute override enable, 64K*16way
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* don't call iounmap(base)
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*/
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l2x0_init(base, 0x40470000, 0x82000fff);
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}
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#endif
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for (i = 0; i < ARRAY_SIZE(platform_devinfo); i++)
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platform_device_register_full(&platform_devinfo[i]);
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}
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#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
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#define INT2SMSKCR1 0x8228c /* 0xfe78228c */
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#define INT2NTSR0 0x00018 /* 0xfe700018 */
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#define INT2NTSR1 0x0002c /* 0xfe70002c */
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static void __init r8a7778_init_irq_common(void)
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{
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void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
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BUG_ON(!base);
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/* route all interrupts to ARM */
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__raw_writel(0x73ffffff, base + INT2NTSR0);
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__raw_writel(0xffffffff, base + INT2NTSR1);
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/* unmask all known interrupts in INTCS2 */
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__raw_writel(0x08330773, base + INT2SMSKCR0);
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__raw_writel(0x00311110, base + INT2SMSKCR1);
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iounmap(base);
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}
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void __init r8a7778_init_irq(void)
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{
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void __iomem *gic_dist_base;
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void __iomem *gic_cpu_base;
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gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE);
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gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE);
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BUG_ON(!gic_dist_base || !gic_cpu_base);
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/* use GIC to handle interrupts */
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gic_init(0, 29, gic_dist_base, gic_cpu_base);
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r8a7778_init_irq_common();
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}
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void __init r8a7778_init_delay(void)
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{
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shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
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}
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#ifdef CONFIG_USE_OF
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void __init r8a7778_init_irq_dt(void)
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{
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irqchip_init();
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r8a7778_init_irq_common();
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}
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static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = {
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{},
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};
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void __init r8a7778_add_standard_devices_dt(void)
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{
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of_platform_populate(NULL, of_default_bus_match_table,
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r8a7778_auxdata_lookup, NULL);
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}
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static const char *r8a7778_compat_dt[] __initdata = {
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"renesas,r8a7778",
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NULL,
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};
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DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
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.init_early = r8a7778_init_delay,
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.init_irq = r8a7778_init_irq_dt,
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.init_machine = r8a7778_add_standard_devices_dt,
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.init_time = shmobile_timer_init,
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.dt_compat = r8a7778_compat_dt,
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MACHINE_END
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#endif /* CONFIG_USE_OF */
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