sil24_error_intr logs all error interrupts. ATAPI devices generates
many harmless errors which can be ignored and all serious ones are
reported via sense data by SCSI layer. Don't log device errors from
ATAPI devices.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This patch implements ATAPI support for sil24 and bumps driver version
to 0.23.
Signed-off-by: Tejun Heo <htejun@gmail.com>
--
Jeff, it has been converted to use ->dev_config as pointed out.
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
There seems to be no way to obtain device signature from sil24 after
SATA phy reset and SRST is needed anyway for later port multiplier
suppport. This patch converts sil24_phy_reset to use SRST instaed.
Signed-off-by: Tejun Heo <htejun@gmail.com>
--
Jeff, I didn't remove the 10ms sleep just to be on the safe side. I
think we can live with 10ms sleep on SRST.
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
When an error condition is raised by device via D2H FIS or SDB. sil24
controller should be restarted by setting PORT_CS_INIT and waiting
until PORT_CS_RDY is asserted instead of resetting the controller.
This patch implements sil24_restart_controller for those cases. This
patch also makes sure that PORT_CS_RDY is asserted on
sil24_reset_controller completion.
Signed-off-by: Tejun Heo <htejun@gmail.com>
--
Jeff, delay is reduced to 1us and cnt increased to 10k. My sil3124
turns on PORT_CS_RDY on the second iteration even without any delay.
I think 10k * 1us should be more than enough.
I tried to convert both restart and reset to use msleep's with work
queue, but if we do that, host_set lock should be released after
initiating restart or reset, leading to race condition among
reset/restart, other interrupts and timeout. Implementing
synchronization among those in low-level driver doesn't seem right.
Well, reduced timeout should work for the time being.
Thanks.
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Handle errata (it was unintentional on this h/w, whereas its intentional
on others) whereby the nIEN bit in Device Control is ignored, leading to
a situation where a hardware interrupt completes the qc before the
polling code has a chance to.
This will get fixed The Right Way(tm) once Albert Lee's irq-pio
branch is merged, as the more natural PIO method on this hardware is
interrupt-driven.
- DMA boundary was being handled incorrectly. Copied the code from
ata_fill_sg(), since Marvell has the same DMA boundary needs.
(we can't use ata_fill_sg directly since we have different hardware
descriptors)
- cleaned up the SATA phy reset code, to deal with various errata
ATA devices don't generate many errors, so the preferred method is to
printk() when they occur.
ATAPI devices generate tons of exceptions during the normal course
of operation, so this change skips logging the most common class of
errors.
The following code segment is not functional because the transfer cycle time speficied by
the EIDE device is later overwritten by ata_timing_quantize():
/*
* If the drive is an EIDE drive, it can tell us it needs extended
* PIO/MW_DMA cycle timing.
*/
if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
memset(&p, 0, sizeof(p));
(snip)
ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
<== uninitialized "t" is used here
}
/*
* Convert the timing to bus clock counts.
*/
ata_timing_quantize(s, t, T, UT); <== t is overwritten by quantized s
The patch has been submitted for ide-timing.h before:
http://marc.theaimsgroup.com/?l=linux-ide&m=110820013425454&w=2
Resubmitted for libata.
Changes:
- Minor fix to honor the following transfer cycle time speficied by the device
- id[65]: Minimum Multiword DMA transfer cycle time per word
- id[67]: Minimum PIO transfer cycle time without flow control
- id[68]: Minimum PIO transfer cycle time with IORDY
Signed-off-by: Albert Lee <albertcc@tw.ibm.com>
=======
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Adds constants for ATAPI support to sata_sil24. This patch is
originally from Jeff Garzik <jgarzik@pobox.com>.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
- Fix a regression in command completion, which prevented
the restart of the DMA engine after the device throws
an error.
- Pack more hardware info into the port-reset error message.
- Promote "welcome to our timeout" message from debug msg
to normal printk.
- Move ATAPI check-condition handling out of the timeout handler
- Use multi-qc-issue feature to issue REQUEST SENSE ATAPI PACKET
command upon receiving an ATAPI check-condition.
This cleans things up a lot, and eliminates a nasty recursion bug.
- in ata_dev_identify(), don't assume that all devices are either
ATA or ATAPI. In the future, this code will see port multipliers
and other devices.
- make a debugging printk less verbose
- add new helper ata_qc_reinit()
- add new helper BPRINTK() and port flag ATA_FLAG_DEBUGMSG, for
fine-grained debugging use.
The ATAPI pad-to-next-32bit-boundary code modifies the scatterlist's
length variable, sometimes to zero. x86-64 platform would oops if a
zero-length scatterlist entry was asked to be mapped. Work around this
by ensuring that we never DMA-map a zero length buffer or SG entry.
Needed to get ATAPI working.
- dump hardware error bits, if hardware signals an error
- only reset hardware during timeout if a command was active
- call ata_qc_complete() with a fine-grained error mask.
Needed so that atapi_qc_complete() can distinguish between
device errors and other errors.
sil24_port_stop() is missing call to ata_pad_free() thus leaking pad
buffer when a port is stopped. This patch adds it.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Although according to the documentation this largely only affects
desktop LED control, let's make sure we set the ATAPI bit when we
have an ATAPI device attached to the port.
scsi_wait_req does not exist any more in the SCSI layer. This patch
makes it so libata can compile again.
Signed-off-by: Mike Christie <michaelc@cs.wisc.edu>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This will let me chop the code size of several drivers right down. In
many cases the actual private data is very useful and constant for a
given host controller so being able to just pass it at probe time would
be very useful indeed (eg with the via driver would could pass the udma
clocking and reduce the code size, or with the AMD one the UDMA
multiplier and the offset)
Signed-off-by: Alan Cox <alan@redhat.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Current upstream 'allmodconfig' build is broken. This is the obvious
patch...
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This patch started life as a response to fedora specific ide subsystem changes
that made error handling of my ATAPI tape drive fail; the specifics are in
https://bugzilla.redhat.com/bugzilla/show_bug.cgi?id=160868
The insertion of the statement rq->errors = err; near the end of
ide_end_drive_cmd() in drivers/ide/ide-io.c means that rq->errors does not
contain what it needs to in idescsi_end_request() in drivers/scsi/ide-scsi.c
anymore. Recent mainline kernels now also have this change.
The patch below makes ide-scsi whole.
Signed-off-by: Willem Riede <wrlk@riede.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
A driver must wait 100us before attempting an MMIO operation
to the RISC after a soft-reset has been initiated. A
similar delay was needed with earlier ISPs.
Note: a PCI config-space read is used to flush the MMIO
write to the ISP, since the ISP's state machines are unable
to respond to any MMIO read during the reset process.
Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Correct issue where abort I/O command was not being issued
when the loop-state was down.
Signed-off-by: Ravi Anand <ravi.anand@qlogic.com>
Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
When mulitple initiators are coming up in an FCAL topology.
Signed-off-by: Ravi Anand <ravi.anand@qlogic.com>
Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
On MMIO relaxed-order platforms, it is possible for the
proper delay during NVRAM access to begin before the request
passes through the PCI bus (via a MMIO write) to the ISP.
Thus, causing a subsequent read to the NVRAM part to fail.
Add a MMIO read, after the MMIO write to insure any posted
writes are flushed.
Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Received from Mark Salyzyn.
The return data from a read capacity 16 needs to have RTO_EN and PROT_EN
zeroed out.
Signed-off-by: Mark Haverkamp <markh@osdl.org>
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
