Commit Graph

353 Commits

Author SHA1 Message Date
Mike Turquette
38bf3a7978 Merge branch 'clk-pxa27x' into clk-next 2014-09-30 12:49:42 -07:00
Robert Jarzmik
53f3394a0f clk: dts: document pxa clock binding
Document the device-tree binding of Marvell PXA based SoCs.
PXA clocks are mostly fixed rate and fixed ratio clocks derived from an
external oscillator, and gated by a register set (CKEN or CKEN*).

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-30 12:31:31 -07:00
Mike Turquette
24afc3852e Samsung clock patches for v3.18
1) non-critical fixes (without the need to push to stable)
 
 fa0111be4f clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation
 b511593d71 clk: samsung: exynos4: fix g3d clocks
 c142543001 clk: samsung: exynos4: add missing smmu_g2d clock and update comments
 22842d244a clk: samsung: exynos5260: fix typo in clock name
 e82ba578cc clk: samsung: exynos3250: fix width field of mout_mmc0/1
 59037b92f4 clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock
 5ce37f2666 clk: samsung: exynos3250: fix mout_cam_blk parent list
 
 2) Clock driver extensions
 
 07ccf02ba5 dt-bindings: clk: samsung: Document the DMC domain of Exynos3250 CMU
 d0e73eaf19 ARM: dts: exynos3250: Add CMU node for DMC domain clocks
 e3c3f19bc6 clk: samsung: exynos3250: Register DMC clk provider
 4676f0aab9 clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks
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Merge tag 'for_3.18/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next

Samsung clock patches for v3.18

1) non-critical fixes (without the need to push to stable)

fa0111be4f clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation
b511593d71 clk: samsung: exynos4: fix g3d clocks
c142543001 clk: samsung: exynos4: add missing smmu_g2d clock and update comments
22842d244a clk: samsung: exynos5260: fix typo in clock name
e82ba578cc clk: samsung: exynos3250: fix width field of mout_mmc0/1
59037b92f4 clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock
5ce37f2666 clk: samsung: exynos3250: fix mout_cam_blk parent list

2) Clock driver extensions

07ccf02ba5 dt-bindings: clk: samsung: Document the DMC domain of Exynos3250 CMU
d0e73eaf19 ARM: dts: exynos3250: Add CMU node for DMC domain clocks
e3c3f19bc6 clk: samsung: exynos3250: Register DMC clk provider
4676f0aab9 clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks
2014-09-29 23:43:12 -07:00
Mike Turquette
4dc7ed32f3 Allwinner Clocks Additions for 3.18
The most important part of this serie is the addition of the phase API to
 handle the MMC clocks in the Allwinner SoCs.
 
 Apart from that, the A23 gained a new mbus driver, and there's a fix for a
 incorrect divider table on the APB0 clock.
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Merge tag 'sunxi-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Allwinner Clocks Additions for 3.18

The most important part of this serie is the addition of the phase API to
handle the MMC clocks in the Allwinner SoCs.

Apart from that, the A23 gained a new mbus driver, and there's a fix for a
incorrect divider table on the APB0 clock.
2014-09-27 12:52:33 -07:00
Chen-Yu Tsai
9c8176bfb6 clk: sunxi: Add sun8i MBUS clock support
The MBUS clock on sun8i is slightly different from the old mod0 clocks.
The divider is 3 bits wider, while also needing a divider table for the
higher 4 values, which all set the same divider.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-09-27 09:05:43 +02:00
Maxime Ripard
37e1041f04 clk: sunxi: mod0: Introduce MMC proper phase handling
The MMC clock we thought we had until now are actually not one but three
different clocks.

The main one is unchanged, and will have three outputs:
  - The clock fed into the MMC
  - a sample and output clocks, to deal with when should we output/sample data
    to/from the MMC bus

The phase control we had are actually controlling the two latter clocks, but
the main MMC one is unchanged.

We can adjust the phase with a 3 bits value, from 0 to 7, 0 meaning a 180 phase
shift, and the other values being the number of periods from the MMC parent
clock to outphase the clock of.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27 08:58:04 +02:00
Maxime Ripard
03e29bbf40 clk: sunxi: Introduce mbus compatible
Even though the mbus clock is a regular module clock, given its nature, it
needs to be enabled all the time.

Introduce a new compatible, to differentiate it from the other module clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27 08:58:02 +02:00
Jyri Sarha
c873d14d30 clk: add gpio gated clock
The added gpio-gate-clock is a basic clock that can be enabled and
disabled trough a gpio output. The DT binding document for the clock
is also added. For EPROBE_DEFER handling the registering of the clock
has to be delayed until of_clk_get() call time.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-26 16:51:42 -07:00
Krzysztof Kozlowski
07ccf02ba5 dt-bindings: clk: samsung: Document the DMC domain of Exynos3250 CMU
Document the new compatible for clock in DMC (Dynamic Memory
Controller) domain of Exynos3250 Clock Management Unit (CMU).

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:28:56 +02:00
Javier Martinez Canillas
f82a1d1586 clk: max77802: Add DT binding documentation
Add Device Tree binding documentation for the clocks
outputs in the Maxim 77802 Power Management IC.

Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-09 13:56:04 -07:00
Javier Martinez Canillas
fcd0864cdb clk: max77686: Improve Maxim 77686 PMIC clocks binding
Like most clock drivers, the Maxim 77686 PMIC clock binding
follows the convention that the "#clock-cells" property is
used to specify the number of cells in a clock provider.

But the binding document is not clear enough that it shall
be set to 1 since the PMIC support multiple clocks outputs.

Also, explain that the clocks identifiers are defined in a
header file that can be included by Device Tree source with
client nodes to avoid using magic numbers.

Finally, add "clock-output-names" as an optional property
since now is supported by the clock driver.

Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-09 13:55:53 -07:00
Ulrich Hecht
7466103cc0 ARM: shmobile: r8a7794: document CPG clock support
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 15:03:15 -07:00
Ulrich Hecht
5acb7bbbab ARM: shmobile: r8a7794: document MSTP clock support
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 15:03:14 -07:00
Linus Torvalds
b3345d7c57 ARM: SoC platform changes for 3.17
This is the bulk of new SoC enablement and other platform changes for 3.17:
 
 * Samsung S5PV210 has been converted to DT and multiplatform
 * Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms
 * Kirkwood, one of the popular Marvell platforms, is folded into the
   mvebu platform code, removing mach-kirkwood.
 * Hwmod data for TI AM43xx and DRA7 platforms.
 * More additions of Renesas shmobile platform support
 * Removal of plat-samsung contents that can be removed with S5PV210 being
   multiplatform/DT-enabled and the other two old platforms being removed.
 
 New platforms (most with only basic support right now):
 
 * Hisilicon X5HD2 settop box chipset is introduced
 * Mediatek MT6589 (mobile chipset) is introduced
 * Broadcom BCM7xxx settop box chipset is introduced
 
 + as usual a lot other pieces all over the platform code.
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Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "This is the bulk of new SoC enablement and other platform changes for
  3.17:

   - Samsung S5PV210 has been converted to DT and multiplatform
   - Clock drivers and bindings for some of the lower-end i.MX 1/2
     platforms
   - Kirkwood, one of the popular Marvell platforms, is folded into the
     mvebu platform code, removing mach-kirkwood
   - Hwmod data for TI AM43xx and DRA7 platforms
   - More additions of Renesas shmobile platform support
   - Removal of plat-samsung contents that can be removed with S5PV210
     being multiplatform/DT-enabled and the other two old platforms
     being removed

  New platforms (most with only basic support right now):

   - Hisilicon X5HD2 settop box chipset is introduced
   - Mediatek MT6589 (mobile chipset) is introduced
   - Broadcom BCM7xxx settop box chipset is introduced

  + as usual a lot other pieces all over the platform code"

* tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits)
  ARM: hisi: remove smp from machine descriptor
  power: reset: move hisilicon reboot code
  ARM: dts: Add hix5hd2-dkb dts file.
  ARM: debug: Rename Hi3716 to HIX5HD2
  ARM: hisi: enable hix5hd2 SoC
  ARM: hisi: add ARCH_HISI
  MAINTAINERS: add entry for Broadcom ARM STB architecture
  ARM: brcmstb: select GISB arbiter and interrupt drivers
  ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
  ARM: configs: enable SMP in bcm_defconfig
  ARM: add SMP support for Broadcom mobile SoCs
  Documentation: arm: misc updates to Marvell EBU SoC status
  Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
  ARM: mvebu: fix build without platforms selected
  ARM: mvebu: add cpuidle support for Armada 38x
  ARM: mvebu: add cpuidle support for Armada 370
  cpuidle: mvebu: add Armada 38x support
  cpuidle: mvebu: add Armada 370 support
  cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
  ARM: mvebu: export the SCU address
  ...
2014-08-08 11:14:29 -07:00
Alexander Shiyan
d14c17b235 clk: clps711x: Add DT bindings documentation
This patch adds DT binding documentation for the Cirrus Logic
CLPS711X-based CPUs clock subsystem.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-28 23:30:46 -07:00
Gabriel FERNANDEZ
3414666d34 clk: st: Adds Flexgen clock binding
A Flexgen structure is composed by:
- a clock cross bar (represented by a mux element)
- a pre and final dividers (represented by a divider and gate elements)

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-28 22:36:23 -07:00
Gabriel FERNANDEZ
0268099c89 clk: st: Update ST clock binding documentation
Naming convention was changed in dts file but the
clock binding documentation hasn't been updated.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-28 22:35:17 -07:00
Arnd Bergmann
5be42f334b Merge branch 'clk-rockchip' of git://git.linaro.org/people/mike.turquette/linux into next/soc
This is a dependency for the rk3288 DT updates, the branch should
first get merged through Mike's clk git.

* 'clk-rockchip' of git://git.linaro.org/people/mike.turquette/linux:
  ARM: rockchip: Select ARCH_HAS_RESET_CONTROLLER
  clk: rockchip: add clock controller for rk3288
  dt-bindings: add documentation for rk3288 cru
  clk: rockchip: add clock driver for rk3188 and rk3066 clocks
  dt-bindings: add documentation for rk3188 clock and reset unit
  clk: rockchip: add reset controller
  clk: rockchip: add clock type for pll clocks and pll used on rk3066
  clk: rockchip: add basic infrastructure for clock branches
  clk: composite: improve rate_hw sanity check logic
  clk: composite: allow read-only clocks
  clk: composite: support determine_rate using rate_ops->round_rate + mux_ops->set_parent

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-07-28 14:02:13 +02:00
Arnd Bergmann
39fbf98408 mvebu SoC changes for v3.17 (round 4)
- Armada XP
     - Fix return value check in pmsu code
     - Document URLs for new public datasheets (Thanks, Marvell & free-electrons!)
 
  - Armada 370/38x
     - Add cpuidle support
 
  - mvebu
     - Fix build when no platforms are selected
     - Update EBU SoC status in docs
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Merge tag 'mvebu-soc-3.17-4' of git://git.infradead.org/linux-mvebu into next/soc

Merge "mvebu SoC changes for v3.17 (round 4)" from Jason Cooper:

 - Armada XP
    - Fix return value check in pmsu code
    - Document URLs for new public datasheets (Thanks, Marvell & free-electrons!)

 - Armada 370/38x
    - Add cpuidle support

 - mvebu
    - Fix build when no platforms are selected
    - Update EBU SoC status in docs

* tag 'mvebu-soc-3.17-4' of git://git.infradead.org/linux-mvebu: (21 commits)
  Documentation: arm: misc updates to Marvell EBU SoC status
  Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
  ARM: mvebu: fix build without platforms selected
  ARM: mvebu: add cpuidle support for Armada 38x
  ARM: mvebu: add cpuidle support for Armada 370
  cpuidle: mvebu: add Armada 38x support
  cpuidle: mvebu: add Armada 370 support
  cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
  ARM: mvebu: export the SCU address
  ARM: mvebu: make the snoop disabling optional in mvebu_v7_pmsu_idle_prepare()
  ARM: mvebu: use a local variable to store the resume address
  ARM: mvebu: make the cpuidle initialization more generic
  ARM: mvebu: rename the armada_370_xp symbols to mvebu_v7 in pmsu.c
  ARM: mvebu: use the common function for Armada 375 SMP workaround
  ARM: mvebu: add a common function for the boot address work around
  ARM: mvebu: sort the #include of pmsu.c in alphabetic order
  ARM: mvebu: split again armada_370_xp_pmsu_idle_enter() in PMSU code
  ARM: mvebu: fix return value check in armada_xp_pmsu_cpufreq_init()
  clk: mvebu: extend clk-cpu for dynamic frequency scaling
  ARM: mvebu: extend PMSU code to support dynamic frequency scaling
  ...

Conflicts:
	arch/arm/mach-mvebu/Kconfig
	drivers/cpuidle/cpuidle-armada-370-xp.c

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-07-26 18:17:08 +02:00
Arnd Bergmann
96bda115ec Samsung S5PV210 DT support for v3.17
- support common clock framework for s5pv210 clock
 - add generic PHY driver on s5pv210 to support it via DT
 - add dt support for s5pv210-goni, smdkc110, smdkv210 and torbreck boards
 - remove board files from mach-s5pv210 and unused codes
 - enable multiplatform for s5pv210
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Merge tag 's5pv210-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc

Merge "Samsung S5PV210 DT support for v3.17" from Kukjin Kim:

- support common clock framework for s5pv210 clock
- add generic PHY driver on s5pv210 to support it via DT
- add dt support for s5pv210-goni, smdkc110, smdkv210 and torbreck boards
- remove board files from mach-s5pv210 and unused codes
- enable multiplatform for s5pv210

* tag 's5pv210-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  clk: samsung: s5pv210: Remove legacy board support
  ARM: SAMSUNG: Remove remaining legacy code
  gpio: samsung: Remove legacy support of S5PV210
  ARM: S5PV210: Enable multi-platform build support
  cpufreq: s5pv210: Make the driver multiplatform aware
  ARM: S5PV210: Register cpufreq platform device
  ARM: S5PV210: move debug-macro.S into the common space
  ARM: S5PV210: Untie PM support from legacy code
  ARM: S5PV210: Remove support for board files
  ARM: dts: Add Device tree for s5pc110/s5pv210 boards
  ARM: dts: Add Device tree for s5pv210 SoC
  ARM: S5PV210: Add board file for boot using Device Tree
  phy: Add support for S5PV210 to the Exynos USB 2.0 PHY driver
  clk: samsung: Add S5PV210 Audio Subsystem clock driver
  ARM: SAMSUNG: Remove legacy clock code
  serial: samsung: Remove support for legacy clock code
  cpufreq: s3c24xx: Remove some dead code
  ARM: S5PV210: Migrate clock handling to Common Clock Framework
  clk: samsung: Add clock driver for S5PV210 and compatible SoCs

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-07-26 12:01:27 +02:00
Mike Turquette
3cc5aba415 Allwinner clocks additions for 3.17
This pull request adds support for the clocks found in the newly supported
 Allwinner A23 clocks.
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Merge tag 'sunxi-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next-sunxi

Allwinner clocks additions for 3.17

This pull request adds support for the clocks found in the newly supported
Allwinner A23 clocks.
2014-07-25 17:45:30 -07:00
Mike Turquette
9ae1400588 qcom clock changes for 3.17
These patches add support for a handful of Qualcomm's SoC clock
 controllers: APQ8084 gcc and mmcc, IPQ8064 gcc, and APQ8064.
 There's also a small collection of bug fixes that aren't critical
 -rc worthy regressions because the consumer drivers aren't present
 or using the buggy clocks and one optimization for HDMI.
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Merge tag 'qcom-clocks-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into clk-next-msm

qcom clock changes for 3.17

These patches add support for a handful of Qualcomm's SoC clock
controllers: APQ8084 gcc and mmcc, IPQ8064 gcc, and APQ8064.
There's also a small collection of bug fixes that aren't critical
-rc worthy regressions because the consumer drivers aren't present
or using the buggy clocks and one optimization for HDMI.
2014-07-25 15:41:19 -07:00
Sylwester Nawrocki
86be408bfb clk: Support for clock parents and rates assigned from device tree
This patch adds helper functions to configure clock parents and rates
as specified through 'assigned-clock-parents', 'assigned-clock-rates'
DT properties for a clock provider or clock consumer device.
The helpers are now being called by the bus code for the platform, I2C
and SPI busses, before the driver probing and also in the clock core
after registration of a clock provider.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-25 15:16:27 -07:00
Mike Turquette
09575693a2 Merge branch 'clk-rockchip' into clk-next 2014-07-23 19:41:39 -07:00
Olof Johansson
b40abaf07f The i.MX SoC changes for 3.17:
- Add devicetree support for i.MX1 and i.MX21 clock driver
  - Use CLOCKSOURCE_OF_DECLARE() to initialize timer for DT targets
  - Use of_clk_init() to initialize i.MX25 and i.MX27 clock driver in
    device tree boot
  - Remove i.MX1 camera support
  - Remove i.MX27 IP Camera and Lite-Kit board support
  - Add suspend and cpuidle support for i.mx6sx
  - Clean up unused clk_register_clkdev() lookups
  - Update imx-weim bus driver to support populating devices on a simple
    bus
  - Switch i.MX27 and i.MX6QDL clock driver to use macro for clock IDs
  - Make i.MX51 a DT only platform and clean up the non-DT support code
  - Support disabling supervisor protect via DT
  - Random defconfig updates
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Merge tag 'imx-soc-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc

Merge "ARM: imx: SoC changes for 3.17" from Shawn Guo:

The i.MX SoC changes for 3.17:
 - Add devicetree support for i.MX1 and i.MX21 clock driver
 - Use CLOCKSOURCE_OF_DECLARE() to initialize timer for DT targets
 - Use of_clk_init() to initialize i.MX25 and i.MX27 clock driver in
   device tree boot
 - Remove i.MX1 camera support
 - Remove i.MX27 IP Camera and Lite-Kit board support
 - Add suspend and cpuidle support for i.mx6sx
 - Clean up unused clk_register_clkdev() lookups
 - Update imx-weim bus driver to support populating devices on a simple
   bus
 - Switch i.MX27 and i.MX6QDL clock driver to use macro for clock IDs
 - Make i.MX51 a DT only platform and clean up the non-DT support code
 - Support disabling supervisor protect via DT
 - Random defconfig updates

* tag 'imx-soc-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (69 commits)
  ARM: imx: clk-vf610: fix FlexCAN clock gating
  ARM: i.MX: Use CLOCKSOURCE_OF_DECLARE() for DT targets
  ARM: i.MX53: globally disable supervisor protect
  ARM: i.MX: allow disabling supervisor protect via DT
  ARM: i.MX27 clk: Add 26 MHz oscillator circuit clock gate
  ARM: i.MX27 clk: Remove unused definitions
  ARM: i.MX27 clk: Introduce DT include for clock provider
  ARM: i.MX: Remove Freescale Logic Product Development i.MX27 Lite-Kit board support
  ARM: i.MX: Remove excess symbols ARCH_MX1, ARCH_MX25 and MACH_MX27
  ARM: i.MX: Remove i.MX1 camera support
  ARM: imx: use PTR_ERR_OR_ZERO
  bus: imx-weim: populate devices on a simple bus
  ARM: imx: build cpu_is_imx6sl function conditionally
  ARM: imx: imx6sx uses imx6q cpuidle code
  ARM: imx: drop PL310 errata 588369 and 727915
  ARM: imx_v6_v7_defconfig: add FSL_EDMA and PRINTK_TIME
  ARM: imx: clk-imx6sx: register SSI/SSI_IPG as shared gate clocks
  ARM: imx_v6_v7_defconfig: Enable flexcan driver for can support
  ARM: imx_v6_v7_defconfig: Enable STMPE gpio support
  ARM: imx: mark .dt_compat as const
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-19 11:56:39 -07:00
Tomasz Figa
9978f28f69 clk: samsung: Add S5PV210 Audio Subsystem clock driver
This patch adds a driver for clock controller being a part of Audio
Subsystem present on S5PV210 and compatible SoCs. It is used to provide
clocks for other IP blocks of this subsystem.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-19 04:25:08 +09:00
Mateusz Krawczuk
841586082d clk: samsung: Add clock driver for S5PV210 and compatible SoCs
This patch adds new, Common Clock Framework-based clock driver for Samsung
S5PV210 and compatible SoCs. The driver is just added, without enabling it yet.

Signed-off-by: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[t.figa: Added support for other SoC variants and clock output. Fixed
remaining minor issues.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-07-19 04:24:42 +09:00
Alexander Shiyan
e8e3faa039 ARM: i.MX27 clk: Introduce DT include for clock provider
Use clock defines in order to make devicetrees more human readable.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-18 16:11:38 +08:00
Alexander Shiyan
35bcaf00de ARM: i.MX21 clk: Add devicetree support
This patch adds devicetree support CCM module for i.MX21 CPUs.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-18 16:11:32 +08:00
Shawn Guo
d2d2e54d66 ARM: imx6qdl: switch to use macro for clock ID
Instead of using enum for clock ID, let's switch imx6qdl clock driver to
use macro.  In this case, device tree can reuse these macros to improve
readability.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-18 16:11:23 +08:00
Alexander Shiyan
ac36187b37 ARM: i.MX1 clk: Add devicetree support
This patch adds devicetree support CCM module for i.MX1 (MC9328MX1) CPUs.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-07-18 16:10:03 +08:00
Thomas Petazzoni
ee2d8ea1e9 clk: mvebu: extend clk-cpu for dynamic frequency scaling
This commit extends the existing clk-cpu driver used on Marvell Armada
XP platforms to support the dynamic frequency scaling of the CPU
clock. Non-dynamic frequency change was already supported (and used
before secondary CPUs are started), but the dynamic frequency change
requires a completely different procedure.

In order to achieve this, the clk_cpu_set_rate() function is reworked
to handle two separate cases:

 - The case where the clock is enabled, which is the new dynamic
   frequency change code, implemented in clk_cpu_on_set_rate(). This
   part will be used for cpufreq activities.

 - The case where the clock is disabled, which is the existing
   frequency change code, moved in clk_cpu_off_set_rate(). This part
   is already used to set the clock frequency of the secondary CPUs
   before starting them.

In order to implement the dynamic frequency change function, we need
to access the PMU DFS registers, which are outside the currently
mapped "Clock Complex" registers, so a new area of registers is now
mapped. This affects the Device Tree binding, but we are careful to do
it in a backward-compatible way (by allowing the second pair of
registers to be non-existent, and in this case, ensuring
clk_cpu_on_set_rate() returns an error).

Note that technically speaking, the clk_cpu_on_set_rate() does not do
the entire procedure needed to change the frequency dynamically, as it
involves touching a number of PMSU registers. This is done through a
clock notifier registered by the PMSU driver in followup commits.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404920715-19834-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-16 12:58:38 +00:00
Stephen Boyd
e216ce60a9 clk: qcom: Add support for APQ8064 multimedia clocks
The APQ8064 multimedia clock controller is fairly similar to the
8960 multimedia clock controller, except that gfx2d0/1 has been
removed and the gfx3d frequency is slightly faster when using the
newly introduced PLL15. We also add vcap clocks and a couple new
TV clocks.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-15 16:39:03 -07:00
Kumar Gala
24d8fba44a clk: qcom: Add support for IPQ8064's global clock controller (GCC)
Add a driver for the global clock controller found on IPQ8064 based
platforms. This should allow most non-multimedia device drivers to probe
and control their clocks.

This is currently missing clocks for USB HSIC and networking devices.

Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-15 16:38:58 -07:00
Georgi Djakov
2b46cd23a5 clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) support
Add support for the multimedia clock controller found on the APQ8084
based platforms. This will allow the multimedia device drivers to
control their clocks.

Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
[sboyd: Rework parent mapping to avoid conflicts]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-15 16:38:57 -07:00
Chen-Yu Tsai
6c1d66f0da clk: sunxi: sun6i-a31-apb0-gates: Add A23 APB0 support
This patch adds "allwinner,sun8i-a23-apb0-gates-clk", a A23 specific
compatible to the sun6i-a31-apb0-gates clock driver, along with the
gate bitmap.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-15 08:53:24 +02:00
Heiko Stübner
5775b82e74 dt-bindings: add documentation for rk3288 cru
This adds the dt-binding documentation for the clock and reset unit found on
Rockchip rk3288 SoCs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-13 12:17:09 -07:00
Heiko Stübner
43aea81778 dt-bindings: add documentation for rk3188 clock and reset unit
This add bindings documentation for the clock and reset unit found on
rk3188 and rk3066 SoCs from Rockchip.

Also deprecate the old gate clock binding, as these shouldn't be used
in the future.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-13 12:17:08 -07:00
Georgi Djakov
56097d8df0 clk: qcom: Add APQ8084 Global Clock Controller documentation
Add the compatible string for the APQ8084 global clock controller
to the clock binding documentation.

Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-07-11 13:21:57 -07:00
Chen-Yu Tsai
57a1fbf284 clk: sunxi: Add A23 APB0 divider clock support
The A23 has an almost identical PRCM clock tree. The difference in
the APB0 clock is the smallest divisor is 1, instead of 2.

This patch adds a separate sun8i-a23-apb0-clk driver to support it.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-07 10:46:21 +02:00
Chen-Yu Tsai
515c1a4bdc clk: sunxi: Add A23 clocks support
The clock control unit on the A23 is similar to the one found on the A31.

The AHB1, APB1, APB2 gates on the A23 are almost identical to the ones
on the A31, but some outputs are missing.

The main CPU PLL (PLL1) however is like that on older Allwinner SoCs,
such as the A10 or A20, but the N factor starts from 1 instead of 0.

This patch adds support for PLL1 and all the basic clock muxes and gates.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-07-04 12:05:17 +02:00
Peter Ujfalusi
5974b794cb dt/bindings: Binding documentation for Palmas clk32kg and clk32kgaudio clocks
Palmas class of devices can provide 32K clock(s) to be used by other devices
on the board. Depending on the actual device the provided clocks can be:
CLK32K_KG and CLK32K_KGAUDIO
or only one:
CLK32K_KG (TPS659039 for example)

Use separate compatible flags for the two 32K clock.
A system which needs or have only one of the 32k clock from
Palmas will need to add node(s) for each clock as separate section
in the dts file.
The two compatible property is:
"ti,palmas-clk32kg" for clk32kg clock
"ti,palmas-clk32kgaudio" for clk32kgaudio clock

Apart from the register control of the clocks - which is done via
the clock API there is a posibility to enable the external sleep
control. In this way the clock can be enabled/disabled on demand by the
user of the clock.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-07-01 21:37:57 -07:00
Rob Herring
f27e861f7b dt/bindings: add compatible string for versatile osc clock
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2014-06-24 14:16:03 -05:00
Linus Torvalds
dd1845af24 This pull request contains the second half the of the clk changes for
3.16. They are simply fixes and code refactoring for the OMAP clock
 drivers. The sunxi clock driver changes include splitting out the one
 mega-driver into several smaller pieces and adding support for the A31
 SoC clocks.
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Merge tag 'clk-for-linus-3.16-part2' of git://git.linaro.org/people/mike.turquette/linux

Pull more clock framework updates from Mike Turquette:
 "This contains the second half the of the clk changes for 3.16.

  They are simply fixes and code refactoring for the OMAP clock drivers.
  The sunxi clock driver changes include splitting out the one
  mega-driver into several smaller pieces and adding support for the A31
  SoC clocks"

* tag 'clk-for-linus-3.16-part2' of git://git.linaro.org/people/mike.turquette/linux: (25 commits)
  clk: sunxi: document PRCM clock compatible strings
  clk: sunxi: add PRCM (Power/Reset/Clock Management) clks support
  clk: sun6i: Protect SDRAM gating bit
  clk: sun6i: Protect CPU clock
  clk: sunxi: Rework clock protection code
  clk: sunxi: Move the GMAC clock to a file of its own
  clk: sunxi: Move the 24M oscillator to a file of its own
  clk: sunxi: Remove calls to clk_put
  clk: sunxi: document new A31 USB clock compatible
  clk: sunxi: Implement A31 USB clock
  ARM: dts: OMAP5/DRA7: use omap5-mpu-dpll-clock capable of dealing with higher frequencies
  CLK: TI: dpll: support OMAP5 MPU DPLL that need special handling for higher frequencies
  ARM: OMAP5+: dpll: support Duty Cycle Correction(DCC)
  CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ck
  CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)
  dt:/bindings: DRA7 ATL (Audio Tracking Logic) clock bindings
  ARM: dts: dra7xx-clocks: Correct name for atl clkin3 clock
  CLK: TI: gate: add composite interface clock to OMAP2 only build
  ARM: OMAP2: clock: add DT boot support for cpufreq_ck
  CLK: TI: OMAP2: add clock init support
  ...
2014-06-15 16:02:20 -10:00
Boris BREZILLON
5c89a8b657 clk: sunxi: document PRCM clock compatible strings
Document new compatible strings for clock provided by the PRCM
(Power/Reset/Clock Management) unit.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 10:25:03 +02:00
Emilio López
6d1d14d5ce clk: sunxi: document new A31 USB clock compatible
Support for the USB gates and resets on A31 has been recently added
using a new compatible, so let's document it here.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
2014-06-11 09:58:43 +02:00
Linus Torvalds
c5aec4c76a Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
Pull powerpc updates from Ben Herrenschmidt:
 "Here is the bulk of the powerpc changes for this merge window.  It got
  a bit delayed in part because I wasn't paying attention, and in part
  because I discovered I had a core PCI change without a PCI maintainer
  ack in it.  Bjorn eventually agreed it was ok to merge it though we'll
  probably improve it later and I didn't want to rebase to add his ack.

  There is going to be a bit more next week, essentially fixes that I
  still want to sort through and test.

  The biggest item this time is the support to build the ppc64 LE kernel
  with our new v2 ABI.  We previously supported v2 userspace but the
  kernel itself was a tougher nut to crack.  This is now sorted mostly
  thanks to Anton and Rusty.

  We also have a fairly big series from Cedric that add support for
  64-bit LE zImage boot wrapper.  This was made harder by the fact that
  traditionally our zImage wrapper was always 32-bit, but our new LE
  toolchains don't really support 32-bit anymore (it's somewhat there
  but not really "supported") so we didn't want to rely on it.  This
  meant more churn that just endian fixes.

  This brings some more LE bits as well, such as the ability to run in
  LE mode without a hypervisor (ie. under OPAL firmware) by doing the
  right OPAL call to reinitialize the CPU to take HV interrupts in the
  right mode and the usual pile of endian fixes.

  There's another series from Gavin adding EEH improvements (one day we
  *will* have a release with less than 20 EEH patches, I promise!).

  Another highlight is the support for the "Split core" functionality on
  P8 by Michael.  This allows a P8 core to be split into "sub cores" of
  4 threads which allows the subcores to run different guests under KVM
  (the HW still doesn't support a partition per thread).

  And then the usual misc bits and fixes ..."

[ Further delayed by gmail deciding that BenH is a dirty spammer.
  Google knows.  ]

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (155 commits)
  powerpc/powernv: Add missing include to LPC code
  selftests/powerpc: Test the THP bug we fixed in the previous commit
  powerpc/mm: Check paca psize is up to date for huge mappings
  powerpc/powernv: Pass buffer size to OPAL validate flash call
  powerpc/pseries: hcall functions are exported to modules, need _GLOBAL_TOC()
  powerpc: Exported functions __clear_user and copy_page use r2 so need _GLOBAL_TOC()
  powerpc/powernv: Set memory_block_size_bytes to 256MB
  powerpc: Allow ppc_md platform hook to override memory_block_size_bytes
  powerpc/powernv: Fix endian issues in memory error handling code
  powerpc/eeh: Skip eeh sysfs when eeh is disabled
  powerpc: 64bit sendfile is capped at 2GB
  powerpc/powernv: Provide debugfs access to the LPC bus via OPAL
  powerpc/serial: Use saner flags when creating legacy ports
  powerpc: Add cpu family documentation
  powerpc/xmon: Fix up xmon format strings
  powerpc/powernv: Add calls to support little endian host
  powerpc: Document sysfs DSCR interface
  powerpc: Fix regression of per-CPU DSCR setting
  powerpc: Split __SYSFS_SPRSETUP macro
  arch: powerpc/fadump: Cleaning up inconsistent NULL checks
  ...
2014-06-10 18:54:22 -07:00
Mike Turquette
3f6eec9969 Merge branch 'for-v3.16/ti-clk-drv' of github.com:t-kristo/linux-pm into clk-next 2014-06-10 16:53:25 -07:00
Linus Torvalds
1a5700bc2d The clock framework changes for 3.16 are pretty typical: mostly clock
driver additions and fixes. There are additions to the clock core code
 for some of the basic types (e.g. the common divider type has some fixes
 and featured added to it).
 
 One minor annoyance is a last-minute dependency that wasn't handled
 quite right. ba0fae3 in this pull request depends on
 include/dt-bindings/clock/berlin2.h, which is already in your tree via
 the arm-soc pull request. Building for the berlin platform will break
 when the clk tree is built on it's own, but merged into your master
 branch everything should be fine.
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Merge tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux into next

Pull clock framework updates from Mike Turquette:
 "The clock framework changes for 3.16 are pretty typical: mostly clock
  driver additions and fixes.  There are additions to the clock core
  code for some of the basic types (e.g. the common divider type has
  some fixes and featured added to it).

  One minor annoyance is a last-minute dependency that wasn't handled
  quite right.  Commit ba0fae3b06 ("clk: berlin: add core clock driver
  for BG2/BG2CD") in this pull request depends on
  include/dt-bindings/clock/berlin2.h, which is already in your tree via
  the arm-soc pull request.  Building for the berlin platform will break
  when the clk tree is built on it's own, but merged into your master
  branch everything should be fine"

* tag 'clk-for-linus-3.16' of git://git.linaro.org/people/mike.turquette/linux: (75 commits)
  mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
  clk: export __clk_round_rate for providers
  clk: versatile: free icst on error return
  clk: qcom: Return error pointers for unimplemented clocks
  clk: qcom: Support msm8974pro global clock control hardware
  clk: qcom: Properly support display clocks on msm8974
  clk: qcom: Support display RCG clocks
  clk: qcom: Return highest rate when round_rate() exceeds plan
  clk: qcom: Fix mmcc-8974's PLL configurations
  clk: qcom: Fix clk_rcg2_is_enabled() check
  clk: berlin: add core clock driver for BG2Q
  clk: berlin: add core clock driver for BG2/BG2CD
  clk: berlin: add driver for BG2x complex divider cells
  clk: berlin: add driver for BG2x simple PLLs
  clk: berlin: add driver for BG2x audio/video PLL
  clk: st: Terminate of match table
  clk/exynos4: Fix compilation warning
  ARM: shmobile: r8a7779: Add clock index macros for DT sources
  clk: divider: Fix overflow in clk_divider_bestdiv
  clk: u300: Terminate of match table
  ...
2014-06-07 20:27:30 -07:00
Nishanth Menon
b4be018921 CLK: TI: dpll: support OMAP5 MPU DPLL that need special handling for higher frequencies
MPU DPLL on OMAP5, DRA75x, DRA72x has a limitation on the maximum
frequency it can be locked at. Duty Cycle Correction circuit is used
to recover a correct duty cycle for achieving higher frequencies
(hardware internally switches output to M3 output(CLKOUTHIF) from M2
output (CLKOUT)).

So provide support to setup required data to handle Duty cycle by
the setting up the minimum frequency for DPLL. 1.4GHz is common
for all these devices and is based on Technical Reference Manual
information for OMAP5432((SWPU282U) chapter 3.6.3.3.1 "DPLLs Output
Clocks Parameters", and equivalent information from DRA75x, DRA72x
documentation(SPRUHP2E, SPRUHI2P).

Signed-off-by: Nishanth Menon <nm@ti.com>
[t-kristo@ti.com: updated for latest dpll init API call]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-06-06 20:33:39 +03:00