mirror of
https://github.com/torvalds/linux.git
synced 2024-12-10 13:12:04 +00:00
The i.MX SoC changes for 3.17:
- Add devicetree support for i.MX1 and i.MX21 clock driver
- Use CLOCKSOURCE_OF_DECLARE() to initialize timer for DT targets
- Use of_clk_init() to initialize i.MX25 and i.MX27 clock driver in
device tree boot
- Remove i.MX1 camera support
- Remove i.MX27 IP Camera and Lite-Kit board support
- Add suspend and cpuidle support for i.mx6sx
- Clean up unused clk_register_clkdev() lookups
- Update imx-weim bus driver to support populating devices on a simple
bus
- Switch i.MX27 and i.MX6QDL clock driver to use macro for clock IDs
- Make i.MX51 a DT only platform and clean up the non-DT support code
- Support disabling supervisor protect via DT
- Random defconfig updates
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJTyN58AAoJEFBXWFqHsHzO6WUH/2d/ZYyXS94Iw/kPm1FEweDg
0wtHVb+Fs/Sjj961xASATNepBwOzpQ1ykI++kvZ1TQXk+FdaYEcB9idmTPycAp9j
QcEmhvxjPmGJtjmTzc/zogL7tTf8TVKX0zGbFGhdpT5tmulY8NA6skAQpB0HAt+s
I95O5t+adwNTl7hAcQWGxOb8E+CA2gJCPdnJ5rdPHr2nzw6B7SjjnjeC90vIbDdh
b6jtfePLvbRUIif0kZuVMXWvebNYa+iRsXsvpoV95q3VJhoR2wPN+H4xnfNviJPb
h+nzibRgrPTyxMWWZ3jtUjw4YIvNdrJWaulC2incOAIQTb7zxrn5w5qxxP3Uj4k=
=RGCO
-----END PGP SIGNATURE-----
Merge tag 'imx-soc-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
Merge "ARM: imx: SoC changes for 3.17" from Shawn Guo:
The i.MX SoC changes for 3.17:
- Add devicetree support for i.MX1 and i.MX21 clock driver
- Use CLOCKSOURCE_OF_DECLARE() to initialize timer for DT targets
- Use of_clk_init() to initialize i.MX25 and i.MX27 clock driver in
device tree boot
- Remove i.MX1 camera support
- Remove i.MX27 IP Camera and Lite-Kit board support
- Add suspend and cpuidle support for i.mx6sx
- Clean up unused clk_register_clkdev() lookups
- Update imx-weim bus driver to support populating devices on a simple
bus
- Switch i.MX27 and i.MX6QDL clock driver to use macro for clock IDs
- Make i.MX51 a DT only platform and clean up the non-DT support code
- Support disabling supervisor protect via DT
- Random defconfig updates
* tag 'imx-soc-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (69 commits)
ARM: imx: clk-vf610: fix FlexCAN clock gating
ARM: i.MX: Use CLOCKSOURCE_OF_DECLARE() for DT targets
ARM: i.MX53: globally disable supervisor protect
ARM: i.MX: allow disabling supervisor protect via DT
ARM: i.MX27 clk: Add 26 MHz oscillator circuit clock gate
ARM: i.MX27 clk: Remove unused definitions
ARM: i.MX27 clk: Introduce DT include for clock provider
ARM: i.MX: Remove Freescale Logic Product Development i.MX27 Lite-Kit board support
ARM: i.MX: Remove excess symbols ARCH_MX1, ARCH_MX25 and MACH_MX27
ARM: i.MX: Remove i.MX1 camera support
ARM: imx: use PTR_ERR_OR_ZERO
bus: imx-weim: populate devices on a simple bus
ARM: imx: build cpu_is_imx6sl function conditionally
ARM: imx: imx6sx uses imx6q cpuidle code
ARM: imx: drop PL310 errata 588369 and 727915
ARM: imx_v6_v7_defconfig: add FSL_EDMA and PRINTK_TIME
ARM: imx: clk-imx6sx: register SSI/SSI_IPG as shared gate clocks
ARM: imx_v6_v7_defconfig: Enable flexcan driver for can support
ARM: imx_v6_v7_defconfig: Enable STMPE gpio support
ARM: imx: mark .dt_compat as const
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
b40abaf07f
26
Documentation/devicetree/bindings/clock/imx1-clock.txt
Normal file
26
Documentation/devicetree/bindings/clock/imx1-clock.txt
Normal file
@ -0,0 +1,26 @@
|
||||
* Clock bindings for Freescale i.MX1 CPUs
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx1-ccm".
|
||||
- reg: Address and length of the register set.
|
||||
- #clock-cells: Should be <1>.
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
|
||||
for the full list of i.MX1 clock IDs.
|
||||
|
||||
Examples:
|
||||
clks: ccm@0021b000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "fsl,imx1-ccm";
|
||||
reg = <0x0021b000 0x1000>;
|
||||
};
|
||||
|
||||
pwm: pwm@00208000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx1-pwm";
|
||||
reg = <0x00208000 0x1000>;
|
||||
interrupts = <34>;
|
||||
clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
28
Documentation/devicetree/bindings/clock/imx21-clock.txt
Normal file
28
Documentation/devicetree/bindings/clock/imx21-clock.txt
Normal file
@ -0,0 +1,28 @@
|
||||
* Clock bindings for Freescale i.MX21
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,imx21-ccm".
|
||||
- reg : Address and length of the register set.
|
||||
- interrupts : Should contain CCM interrupt.
|
||||
- #clock-cells: Should be <1>.
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h
|
||||
for the full list of i.MX21 clock IDs.
|
||||
|
||||
Examples:
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx21-ccm";
|
||||
reg = <0x10027000 0x800>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart1: serial@1000a000 {
|
||||
compatible = "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks IMX21_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX21_CLK_PER1>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
@ -7,117 +7,22 @@ Required properties:
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX27
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
-----------------------
|
||||
dummy 0
|
||||
ckih 1
|
||||
ckil 2
|
||||
mpll 3
|
||||
spll 4
|
||||
mpll_main2 5
|
||||
ahb 6
|
||||
ipg 7
|
||||
nfc_div 8
|
||||
per1_div 9
|
||||
per2_div 10
|
||||
per3_div 11
|
||||
per4_div 12
|
||||
vpu_sel 13
|
||||
vpu_div 14
|
||||
usb_div 15
|
||||
cpu_sel 16
|
||||
clko_sel 17
|
||||
cpu_div 18
|
||||
clko_div 19
|
||||
ssi1_sel 20
|
||||
ssi2_sel 21
|
||||
ssi1_div 22
|
||||
ssi2_div 23
|
||||
clko_en 24
|
||||
ssi2_ipg_gate 25
|
||||
ssi1_ipg_gate 26
|
||||
slcdc_ipg_gate 27
|
||||
sdhc3_ipg_gate 28
|
||||
sdhc2_ipg_gate 29
|
||||
sdhc1_ipg_gate 30
|
||||
scc_ipg_gate 31
|
||||
sahara_ipg_gate 32
|
||||
rtc_ipg_gate 33
|
||||
pwm_ipg_gate 34
|
||||
owire_ipg_gate 35
|
||||
lcdc_ipg_gate 36
|
||||
kpp_ipg_gate 37
|
||||
iim_ipg_gate 38
|
||||
i2c2_ipg_gate 39
|
||||
i2c1_ipg_gate 40
|
||||
gpt6_ipg_gate 41
|
||||
gpt5_ipg_gate 42
|
||||
gpt4_ipg_gate 43
|
||||
gpt3_ipg_gate 44
|
||||
gpt2_ipg_gate 45
|
||||
gpt1_ipg_gate 46
|
||||
gpio_ipg_gate 47
|
||||
fec_ipg_gate 48
|
||||
emma_ipg_gate 49
|
||||
dma_ipg_gate 50
|
||||
cspi3_ipg_gate 51
|
||||
cspi2_ipg_gate 52
|
||||
cspi1_ipg_gate 53
|
||||
nfc_baud_gate 54
|
||||
ssi2_baud_gate 55
|
||||
ssi1_baud_gate 56
|
||||
vpu_baud_gate 57
|
||||
per4_gate 58
|
||||
per3_gate 59
|
||||
per2_gate 60
|
||||
per1_gate 61
|
||||
usb_ahb_gate 62
|
||||
slcdc_ahb_gate 63
|
||||
sahara_ahb_gate 64
|
||||
lcdc_ahb_gate 65
|
||||
vpu_ahb_gate 66
|
||||
fec_ahb_gate 67
|
||||
emma_ahb_gate 68
|
||||
emi_ahb_gate 69
|
||||
dma_ahb_gate 70
|
||||
csi_ahb_gate 71
|
||||
brom_ahb_gate 72
|
||||
ata_ahb_gate 73
|
||||
wdog_ipg_gate 74
|
||||
usb_ipg_gate 75
|
||||
uart6_ipg_gate 76
|
||||
uart5_ipg_gate 77
|
||||
uart4_ipg_gate 78
|
||||
uart3_ipg_gate 79
|
||||
uart2_ipg_gate 80
|
||||
uart1_ipg_gate 81
|
||||
ckih_div1p5 82
|
||||
fpm 83
|
||||
mpll_osc_sel 84
|
||||
mpll_sel 85
|
||||
spll_gate 86
|
||||
mshc_div 87
|
||||
rtic_ipg_gate 88
|
||||
mshc_ipg_gate 89
|
||||
rtic_ahb_gate 90
|
||||
mshc_baud_gate 91
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
|
||||
for the full list of i.MX27 clock IDs.
|
||||
|
||||
Examples:
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx27-ccm";
|
||||
reg = <0x10027000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx27-ccm";
|
||||
reg = <0x10027000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart1: serial@1000a000 {
|
||||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks 81>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
uart1: serial@1000a000 {
|
||||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -7,223 +7,13 @@ Required properties:
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX6Q
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
---------------------------
|
||||
dummy 0
|
||||
ckil 1
|
||||
ckih 2
|
||||
osc 3
|
||||
pll2_pfd0_352m 4
|
||||
pll2_pfd1_594m 5
|
||||
pll2_pfd2_396m 6
|
||||
pll3_pfd0_720m 7
|
||||
pll3_pfd1_540m 8
|
||||
pll3_pfd2_508m 9
|
||||
pll3_pfd3_454m 10
|
||||
pll2_198m 11
|
||||
pll3_120m 12
|
||||
pll3_80m 13
|
||||
pll3_60m 14
|
||||
twd 15
|
||||
step 16
|
||||
pll1_sw 17
|
||||
periph_pre 18
|
||||
periph2_pre 19
|
||||
periph_clk2_sel 20
|
||||
periph2_clk2_sel 21
|
||||
axi_sel 22
|
||||
esai_sel 23
|
||||
asrc_sel 24
|
||||
spdif_sel 25
|
||||
gpu2d_axi 26
|
||||
gpu3d_axi 27
|
||||
gpu2d_core_sel 28
|
||||
gpu3d_core_sel 29
|
||||
gpu3d_shader_sel 30
|
||||
ipu1_sel 31
|
||||
ipu2_sel 32
|
||||
ldb_di0_sel 33
|
||||
ldb_di1_sel 34
|
||||
ipu1_di0_pre_sel 35
|
||||
ipu1_di1_pre_sel 36
|
||||
ipu2_di0_pre_sel 37
|
||||
ipu2_di1_pre_sel 38
|
||||
ipu1_di0_sel 39
|
||||
ipu1_di1_sel 40
|
||||
ipu2_di0_sel 41
|
||||
ipu2_di1_sel 42
|
||||
hsi_tx_sel 43
|
||||
pcie_axi_sel 44
|
||||
ssi1_sel 45
|
||||
ssi2_sel 46
|
||||
ssi3_sel 47
|
||||
usdhc1_sel 48
|
||||
usdhc2_sel 49
|
||||
usdhc3_sel 50
|
||||
usdhc4_sel 51
|
||||
enfc_sel 52
|
||||
emi_sel 53
|
||||
emi_slow_sel 54
|
||||
vdo_axi_sel 55
|
||||
vpu_axi_sel 56
|
||||
cko1_sel 57
|
||||
periph 58
|
||||
periph2 59
|
||||
periph_clk2 60
|
||||
periph2_clk2 61
|
||||
ipg 62
|
||||
ipg_per 63
|
||||
esai_pred 64
|
||||
esai_podf 65
|
||||
asrc_pred 66
|
||||
asrc_podf 67
|
||||
spdif_pred 68
|
||||
spdif_podf 69
|
||||
can_root 70
|
||||
ecspi_root 71
|
||||
gpu2d_core_podf 72
|
||||
gpu3d_core_podf 73
|
||||
gpu3d_shader 74
|
||||
ipu1_podf 75
|
||||
ipu2_podf 76
|
||||
ldb_di0_podf 77
|
||||
ldb_di1_podf 78
|
||||
ipu1_di0_pre 79
|
||||
ipu1_di1_pre 80
|
||||
ipu2_di0_pre 81
|
||||
ipu2_di1_pre 82
|
||||
hsi_tx_podf 83
|
||||
ssi1_pred 84
|
||||
ssi1_podf 85
|
||||
ssi2_pred 86
|
||||
ssi2_podf 87
|
||||
ssi3_pred 88
|
||||
ssi3_podf 89
|
||||
uart_serial_podf 90
|
||||
usdhc1_podf 91
|
||||
usdhc2_podf 92
|
||||
usdhc3_podf 93
|
||||
usdhc4_podf 94
|
||||
enfc_pred 95
|
||||
enfc_podf 96
|
||||
emi_podf 97
|
||||
emi_slow_podf 98
|
||||
vpu_axi_podf 99
|
||||
cko1_podf 100
|
||||
axi 101
|
||||
mmdc_ch0_axi_podf 102
|
||||
mmdc_ch1_axi_podf 103
|
||||
arm 104
|
||||
ahb 105
|
||||
apbh_dma 106
|
||||
asrc 107
|
||||
can1_ipg 108
|
||||
can1_serial 109
|
||||
can2_ipg 110
|
||||
can2_serial 111
|
||||
ecspi1 112
|
||||
ecspi2 113
|
||||
ecspi3 114
|
||||
ecspi4 115
|
||||
ecspi5 116
|
||||
enet 117
|
||||
esai 118
|
||||
gpt_ipg 119
|
||||
gpt_ipg_per 120
|
||||
gpu2d_core 121
|
||||
gpu3d_core 122
|
||||
hdmi_iahb 123
|
||||
hdmi_isfr 124
|
||||
i2c1 125
|
||||
i2c2 126
|
||||
i2c3 127
|
||||
iim 128
|
||||
enfc 129
|
||||
ipu1 130
|
||||
ipu1_di0 131
|
||||
ipu1_di1 132
|
||||
ipu2 133
|
||||
ipu2_di0 134
|
||||
ldb_di0 135
|
||||
ldb_di1 136
|
||||
ipu2_di1 137
|
||||
hsi_tx 138
|
||||
mlb 139
|
||||
mmdc_ch0_axi 140
|
||||
mmdc_ch1_axi 141
|
||||
ocram 142
|
||||
openvg_axi 143
|
||||
pcie_axi 144
|
||||
pwm1 145
|
||||
pwm2 146
|
||||
pwm3 147
|
||||
pwm4 148
|
||||
per1_bch 149
|
||||
gpmi_bch_apb 150
|
||||
gpmi_bch 151
|
||||
gpmi_io 152
|
||||
gpmi_apb 153
|
||||
sata 154
|
||||
sdma 155
|
||||
spba 156
|
||||
ssi1 157
|
||||
ssi2 158
|
||||
ssi3 159
|
||||
uart_ipg 160
|
||||
uart_serial 161
|
||||
usboh3 162
|
||||
usdhc1 163
|
||||
usdhc2 164
|
||||
usdhc3 165
|
||||
usdhc4 166
|
||||
vdo_axi 167
|
||||
vpu_axi 168
|
||||
cko1 169
|
||||
pll1_sys 170
|
||||
pll2_bus 171
|
||||
pll3_usb_otg 172
|
||||
pll4_audio 173
|
||||
pll5_video 174
|
||||
pll8_mlb 175
|
||||
pll7_usb_host 176
|
||||
pll6_enet 177
|
||||
ssi1_ipg 178
|
||||
ssi2_ipg 179
|
||||
ssi3_ipg 180
|
||||
rom 181
|
||||
usbphy1 182
|
||||
usbphy2 183
|
||||
ldb_di0_div_3_5 184
|
||||
ldb_di1_div_3_5 185
|
||||
sata_ref 186
|
||||
sata_ref_100m 187
|
||||
pcie_ref 188
|
||||
pcie_ref_125m 189
|
||||
enet_ref 190
|
||||
usbphy1_gate 191
|
||||
usbphy2_gate 192
|
||||
pll4_post_div 193
|
||||
pll5_post_div 194
|
||||
pll5_video_div 195
|
||||
eim_slow 196
|
||||
spdif 197
|
||||
cko2_sel 198
|
||||
cko2_podf 199
|
||||
cko2 200
|
||||
cko 201
|
||||
vdoa 202
|
||||
pll4_audio_div 203
|
||||
lvds1_sel 204
|
||||
lvds2_sel 205
|
||||
lvds1_gate 206
|
||||
lvds2_gate 207
|
||||
esai_ahb 208
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
|
||||
for the full list of i.MX6 Quad and DualLite clock IDs.
|
||||
|
||||
Examples:
|
||||
|
||||
#include <dt-bindings/clock/imx6qdl-clock.h>
|
||||
|
||||
clks: ccm@020c4000 {
|
||||
compatible = "fsl,imx6q-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
@ -235,7 +25,7 @@ uart1: serial@02020000 {
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <0 26 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
@ -35,10 +36,8 @@ CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y
|
||||
CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y
|
||||
CONFIG_MACH_MX27_3DS=y
|
||||
CONFIG_MACH_IMX27_VISSTRIM_M10=y
|
||||
CONFIG_MACH_IMX27LITE=y
|
||||
CONFIG_MACH_PCA100=y
|
||||
CONFIG_MACH_MXT_TD60=y
|
||||
CONFIG_MACH_IMX27IPCAM=y
|
||||
CONFIG_MACH_IMX27_DT=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
@ -159,6 +158,8 @@ CONFIG_USB_CHIPIDEA=y
|
||||
CONFIG_USB_CHIPIDEA_UDC=y
|
||||
CONFIG_USB_CHIPIDEA_HOST=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_ETH=m
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
CONFIG_KERNEL_LZO=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_LOG_BUF_SHIFT=18
|
||||
@ -31,11 +32,12 @@ CONFIG_MACH_IMX35_DT=y
|
||||
CONFIG_MACH_PCM043=y
|
||||
CONFIG_MACH_MX35_3DS=y
|
||||
CONFIG_MACH_VPR200=y
|
||||
CONFIG_MACH_IMX51_DT=y
|
||||
CONFIG_SOC_IMX51=y
|
||||
CONFIG_SOC_IMX50=y
|
||||
CONFIG_SOC_IMX53=y
|
||||
CONFIG_SOC_IMX6Q=y
|
||||
CONFIG_SOC_IMX6SL=y
|
||||
CONFIG_SOC_IMX6SX=y
|
||||
CONFIG_SOC_VF610=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_IMX6=y
|
||||
@ -67,6 +69,8 @@ CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_CAN=y
|
||||
CONFIG_CAN_FLEXCAN=y
|
||||
CONFIG_CFG80211=y
|
||||
CONFIG_MAC80211=y
|
||||
CONFIG_RFKILL=y
|
||||
@ -160,6 +164,7 @@ CONFIG_SPI=y
|
||||
CONFIG_SPI_IMX=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_MC9S08DZ60=y
|
||||
CONFIG_GPIO_STMPE=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_IMX2_WDT=y
|
||||
@ -242,6 +247,7 @@ CONFIG_RTC_DRV_SNVS=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_IMX_SDMA=y
|
||||
CONFIG_MXS_DMA=y
|
||||
CONFIG_FSL_EDMA=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_DRM_IMX=y
|
||||
CONFIG_DRM_IMX_FB_HELPER=y
|
||||
@ -288,6 +294,7 @@ CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_ISO8859_15=m
|
||||
CONFIG_NLS_UTF8=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
|
||||
@ -27,7 +27,7 @@ CONFIG_ARCH_HIGHBANK=y
|
||||
CONFIG_ARCH_HI3xxx=y
|
||||
CONFIG_ARCH_KEYSTONE=y
|
||||
CONFIG_ARCH_MXC=y
|
||||
CONFIG_MACH_IMX51_DT=y
|
||||
CONFIG_SOC_IMX51=y
|
||||
CONFIG_SOC_IMX53=y
|
||||
CONFIG_SOC_IMX6Q=y
|
||||
CONFIG_SOC_IMX6SL=y
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_TASKSTATS=y
|
||||
|
||||
@ -65,18 +65,8 @@ config IMX_HAVE_IOMUX_V1
|
||||
config ARCH_MXC_IOMUX_V3
|
||||
bool
|
||||
|
||||
config ARCH_MX1
|
||||
bool
|
||||
|
||||
config ARCH_MX25
|
||||
bool
|
||||
|
||||
config MACH_MX27
|
||||
bool
|
||||
|
||||
config SOC_IMX1
|
||||
bool
|
||||
select ARCH_MX1
|
||||
select CPU_ARM920T
|
||||
select IMX_HAVE_IOMUX_V1
|
||||
select MXC_AVIC
|
||||
@ -89,7 +79,6 @@ config SOC_IMX21
|
||||
|
||||
config SOC_IMX25
|
||||
bool
|
||||
select ARCH_MX25
|
||||
select ARCH_MXC_IOMUX_V3
|
||||
select CPU_ARM926T
|
||||
select MXC_AVIC
|
||||
@ -100,7 +89,6 @@ config SOC_IMX27
|
||||
select ARCH_HAS_OPP
|
||||
select CPU_ARM926T
|
||||
select IMX_HAVE_IOMUX_V1
|
||||
select MACH_MX27
|
||||
select MXC_AVIC
|
||||
select PINCTRL_IMX27
|
||||
|
||||
@ -119,18 +107,6 @@ config SOC_IMX35
|
||||
select PINCTRL_IMX35
|
||||
select SMP_ON_UP if SMP
|
||||
|
||||
config SOC_IMX5
|
||||
bool
|
||||
select ARCH_HAS_OPP
|
||||
select ARCH_MXC_IOMUX_V3
|
||||
select MXC_TZIC
|
||||
|
||||
config SOC_IMX51
|
||||
bool
|
||||
select HAVE_IMX_SRC
|
||||
select PINCTRL_IMX51
|
||||
select SOC_IMX5
|
||||
|
||||
if ARCH_MULTI_V4T
|
||||
|
||||
comment "MX1 platforms:"
|
||||
@ -366,15 +342,6 @@ config MACH_IMX27_VISSTRIM_M10
|
||||
This includes specific configurations for the board and its
|
||||
peripherals.
|
||||
|
||||
config MACH_IMX27LITE
|
||||
bool "LogicPD MX27 LITEKIT platform"
|
||||
select IMX_HAVE_PLATFORM_IMX_SSI
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select SOC_IMX27
|
||||
help
|
||||
Include support for MX27 LITEKIT platform. This includes specific
|
||||
configurations for the board and its peripherals.
|
||||
|
||||
config MACH_PCA100
|
||||
bool "Phytec phyCARD-s (pca100)"
|
||||
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
|
||||
@ -406,15 +373,6 @@ config MACH_MXT_TD60
|
||||
Include support for i-MXT (aka td60) platform. This
|
||||
includes specific configurations for the module and its peripherals.
|
||||
|
||||
config MACH_IMX27IPCAM
|
||||
bool "IMX27 IPCAM platform"
|
||||
select IMX_HAVE_PLATFORM_IMX2_WDT
|
||||
select IMX_HAVE_PLATFORM_IMX_UART
|
||||
select SOC_IMX27
|
||||
help
|
||||
Include support for IMX27 IPCAM platform. This includes specific
|
||||
configurations for the board and its peripherals.
|
||||
|
||||
config MACH_IMX27_DT
|
||||
bool "Support i.MX27 platforms from device tree"
|
||||
select SOC_IMX27
|
||||
@ -700,24 +658,29 @@ if ARCH_MULTI_V7
|
||||
|
||||
comment "Device tree only"
|
||||
|
||||
config SOC_IMX5
|
||||
bool
|
||||
select ARCH_HAS_OPP
|
||||
select HAVE_IMX_SRC
|
||||
select MXC_TZIC
|
||||
|
||||
config SOC_IMX50
|
||||
bool "i.MX50 support"
|
||||
select HAVE_IMX_SRC
|
||||
select PINCTRL_IMX50
|
||||
select SOC_IMX5
|
||||
|
||||
help
|
||||
This enables support for Freescale i.MX50 processor.
|
||||
|
||||
config MACH_IMX51_DT
|
||||
config SOC_IMX51
|
||||
bool "i.MX51 support"
|
||||
select SOC_IMX51
|
||||
select PINCTRL_IMX51
|
||||
select SOC_IMX5
|
||||
help
|
||||
This enables support for Freescale i.MX51 processor
|
||||
|
||||
config SOC_IMX53
|
||||
bool "i.MX53 support"
|
||||
select HAVE_IMX_SRC
|
||||
select PINCTRL_IMX53
|
||||
select SOC_IMX5
|
||||
|
||||
@ -734,8 +697,6 @@ config SOC_IMX6
|
||||
select HAVE_IMX_MMDC
|
||||
select HAVE_IMX_SRC
|
||||
select MFD_SYSCON
|
||||
select PL310_ERRATA_588369 if CACHE_L2X0
|
||||
select PL310_ERRATA_727915 if CACHE_L2X0
|
||||
select PL310_ERRATA_769419 if CACHE_L2X0
|
||||
|
||||
config SOC_IMX6Q
|
||||
@ -771,8 +732,6 @@ config SOC_VF610
|
||||
select ARM_GIC
|
||||
select PINCTRL_VF610
|
||||
select VF_PIT_TIMER
|
||||
select PL310_ERRATA_588369 if CACHE_L2X0
|
||||
select PL310_ERRATA_727915 if CACHE_L2X0
|
||||
select PL310_ERRATA_769419 if CACHE_L2X0
|
||||
|
||||
help
|
||||
|
||||
@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
|
||||
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
|
||||
|
||||
imx5-pm-$(CONFIG_PM) += pm-imx5.o
|
||||
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y)
|
||||
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o clk-imx51-imx53.o $(imx5-pm-y)
|
||||
|
||||
obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
|
||||
clk-pfd.o clk-busy.o clk.o \
|
||||
@ -31,6 +31,8 @@ ifeq ($(CONFIG_CPU_IDLE),y)
|
||||
obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
|
||||
obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
|
||||
obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
|
||||
# i.MX6SX reuses i.MX6Q cpuidle driver
|
||||
obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6q.o
|
||||
endif
|
||||
|
||||
ifdef CONFIG_SND_IMX_SOC
|
||||
@ -38,9 +40,6 @@ obj-y += ssi-fiq.o
|
||||
obj-y += ssi-fiq-ksym.o
|
||||
endif
|
||||
|
||||
# Support for CMOS sensor interface
|
||||
obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
|
||||
|
||||
# i.MX1 based machines
|
||||
obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
|
||||
obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
|
||||
@ -60,13 +59,11 @@ obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
|
||||
obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
|
||||
obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
|
||||
obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
|
||||
obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
|
||||
obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
|
||||
obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
|
||||
obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
|
||||
obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
|
||||
obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
|
||||
obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
|
||||
obj-$(CONFIG_MACH_IMX27_DT) += imx27-dt.o
|
||||
|
||||
# i.MX31 based machines
|
||||
@ -109,8 +106,8 @@ obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
|
||||
endif
|
||||
obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
|
||||
|
||||
obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
|
||||
obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
|
||||
obj-$(CONFIG_SOC_IMX51) += mach-imx51.o
|
||||
obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
|
||||
|
||||
obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
|
||||
|
||||
@ -15,100 +15,103 @@
|
||||
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <dt-bindings/clock/imx1-clock.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "common.h"
|
||||
#include "hardware.h"
|
||||
|
||||
/* CCM register addresses */
|
||||
#define IO_ADDR_CCM(off) (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
|
||||
|
||||
#define CCM_CSCR IO_ADDR_CCM(0x0)
|
||||
#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
|
||||
#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
|
||||
#define CCM_PCDR IO_ADDR_CCM(0x20)
|
||||
|
||||
/* SCM register addresses */
|
||||
#define IO_ADDR_SCM(off) (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
|
||||
|
||||
#define SCM_GCCR IO_ADDR_SCM(0xc)
|
||||
|
||||
static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
|
||||
static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
|
||||
"prem", "fclk", };
|
||||
|
||||
enum imx1_clks {
|
||||
dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, mpll_gate,
|
||||
spll, spll_gate, mcu, fclk, hclk, clk48m, per1, per2, per3, clko,
|
||||
uart3_gate, ssi2_gate, brom_gate, dma_gate, csi_gate, mma_gate,
|
||||
usbd_gate, clk_max
|
||||
};
|
||||
static struct clk *clk[IMX1_CLK_MAX];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
static void __iomem *ccm __initdata;
|
||||
#define CCM_CSCR (ccm + 0x0000)
|
||||
#define CCM_MPCTL0 (ccm + 0x0004)
|
||||
#define CCM_SPCTL0 (ccm + 0x000c)
|
||||
#define CCM_PCDR (ccm + 0x0020)
|
||||
#define SCM_GCCR (ccm + 0x0810)
|
||||
|
||||
static void __init _mx1_clocks_init(unsigned long fref)
|
||||
{
|
||||
clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref);
|
||||
clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);
|
||||
clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
|
||||
clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
|
||||
clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks));
|
||||
clk[IMX1_CLK_MPLL] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
|
||||
clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
|
||||
clk[IMX1_CLK_SPLL] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
|
||||
clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
|
||||
clk[IMX1_CLK_MCU] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
|
||||
clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
|
||||
clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
|
||||
clk[IMX1_CLK_CLK48M] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
|
||||
clk[IMX1_CLK_PER1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
|
||||
clk[IMX1_CLK_PER2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
|
||||
clk[IMX1_CLK_PER3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
|
||||
clk[IMX1_CLK_CLKO] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
|
||||
clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
|
||||
clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
|
||||
clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
|
||||
clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
|
||||
clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
|
||||
clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
|
||||
clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
|
||||
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
}
|
||||
|
||||
int __init mx1_clocks_init(unsigned long fref)
|
||||
{
|
||||
int i;
|
||||
ccm = MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR);
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
clk[clk32] = imx_clk_fixed("clk32", fref);
|
||||
clk[clk16m_ext] = imx_clk_fixed("clk16m_ext", 16000000);
|
||||
clk[clk16m] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
|
||||
clk[clk32_premult] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
|
||||
clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks,
|
||||
ARRAY_SIZE(prem_sel_clks));
|
||||
clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
|
||||
clk[mpll_gate] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
|
||||
clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
|
||||
clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
|
||||
clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
|
||||
clk[fclk] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
|
||||
clk[hclk] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
|
||||
clk[clk48m] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
|
||||
clk[per1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
|
||||
clk[per2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
|
||||
clk[per3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
|
||||
clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks,
|
||||
ARRAY_SIZE(clko_sel_clks));
|
||||
clk[uart3_gate] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
|
||||
clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
|
||||
clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
|
||||
clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
|
||||
clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
|
||||
clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
|
||||
clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
|
||||
_mx1_clocks_init(fref);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("imx1 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
clk_register_clkdev(clk[dma_gate], "ahb", "imx1-dma");
|
||||
clk_register_clkdev(clk[hclk], "ipg", "imx1-dma");
|
||||
clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[per1], "per", "imx1-uart.0");
|
||||
clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.0");
|
||||
clk_register_clkdev(clk[per1], "per", "imx1-uart.1");
|
||||
clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1");
|
||||
clk_register_clkdev(clk[per1], "per", "imx1-uart.2");
|
||||
clk_register_clkdev(clk[uart3_gate], "ipg", "imx1-uart.2");
|
||||
clk_register_clkdev(clk[hclk], NULL, "imx1-i2c.0");
|
||||
clk_register_clkdev(clk[per2], "per", "imx1-cspi.0");
|
||||
clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0");
|
||||
clk_register_clkdev(clk[per2], "per", "imx1-cspi.1");
|
||||
clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1");
|
||||
clk_register_clkdev(clk[per2], "per", "imx1-fb.0");
|
||||
clk_register_clkdev(clk[dummy], "ipg", "imx1-fb.0");
|
||||
clk_register_clkdev(clk[dummy], "ahb", "imx1-fb.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_DMA_GATE], "ahb", "imx1-dma");
|
||||
clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma");
|
||||
clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.1");
|
||||
clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.1");
|
||||
clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.2");
|
||||
clk_register_clkdev(clk[IMX1_CLK_UART3_GATE], "ipg", "imx1-uart.2");
|
||||
clk_register_clkdev(clk[IMX1_CLK_HCLK], NULL, "imx1-i2c.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.1");
|
||||
clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.1");
|
||||
clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-fb.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0");
|
||||
clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0");
|
||||
|
||||
mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init mx1_clocks_init_dt(struct device_node *np)
|
||||
{
|
||||
ccm = of_iomap(np, 0);
|
||||
BUG_ON(!ccm);
|
||||
|
||||
_mx1_clocks_init(32768);
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
CLK_OF_DECLARE(imx1_ccm, "fsl,imx1-ccm", mx1_clocks_init_dt);
|
||||
|
||||
@ -7,178 +7,165 @@
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <dt-bindings/clock/imx21-clock.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "common.h"
|
||||
#include "hardware.h"
|
||||
|
||||
#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off)))
|
||||
static void __iomem *ccm __initdata;
|
||||
|
||||
/* Register offsets */
|
||||
#define CCM_CSCR IO_ADDR_CCM(0x0)
|
||||
#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
|
||||
#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
|
||||
#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
|
||||
#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
|
||||
#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
|
||||
#define CCM_PCDR0 IO_ADDR_CCM(0x18)
|
||||
#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
|
||||
#define CCM_PCCR0 IO_ADDR_CCM(0x20)
|
||||
#define CCM_PCCR1 IO_ADDR_CCM(0x24)
|
||||
#define CCM_CCSR IO_ADDR_CCM(0x28)
|
||||
#define CCM_PMCTL IO_ADDR_CCM(0x2c)
|
||||
#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
|
||||
#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
|
||||
#define CCM_CSCR (ccm + 0x00)
|
||||
#define CCM_MPCTL0 (ccm + 0x04)
|
||||
#define CCM_SPCTL0 (ccm + 0x0c)
|
||||
#define CCM_PCDR0 (ccm + 0x18)
|
||||
#define CCM_PCDR1 (ccm + 0x1c)
|
||||
#define CCM_PCCR0 (ccm + 0x20)
|
||||
#define CCM_PCCR1 (ccm + 0x24)
|
||||
|
||||
static const char *mpll_sel_clks[] = { "fpm", "ckih", };
|
||||
static const char *spll_sel_clks[] = { "fpm", "ckih", };
|
||||
static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
|
||||
static const char *mpll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
|
||||
static const char *spll_sel_clks[] = { "fpm_gate", "mpll_osc_sel", };
|
||||
static const char *ssi_sel_clks[] = { "spll_gate", "mpll_gate", };
|
||||
|
||||
enum imx21_clks {
|
||||
ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
|
||||
per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
|
||||
uart4_ipg_gate, gpt1_ipg_gate, gpt2_ipg_gate, gpt3_ipg_gate,
|
||||
pwm_ipg_gate, sdhc1_ipg_gate, sdhc2_ipg_gate, lcdc_ipg_gate,
|
||||
lcdc_hclk_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate,
|
||||
per4_gate, csi_hclk_gate, usb_div, usb_gate, usb_hclk_gate, ssi1_gate,
|
||||
ssi2_gate, nfc_div, nfc_gate, dma_gate, dma_hclk_gate, brom_gate,
|
||||
emma_gate, emma_hclk_gate, slcdc_gate, slcdc_hclk_gate, wdog_gate,
|
||||
gpio_gate, i2c_gate, kpp_gate, owire_gate, rtc_gate, clk_max
|
||||
};
|
||||
static struct clk *clk[IMX21_CLK_MAX];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
static void __init _mx21_clocks_init(unsigned long lref, unsigned long href)
|
||||
{
|
||||
BUG_ON(!ccm);
|
||||
|
||||
clk[IMX21_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
clk[IMX21_CLK_CKIL] = imx_obtain_fixed_clock("ckil", lref);
|
||||
clk[IMX21_CLK_CKIH] = imx_obtain_fixed_clock("ckih", href);
|
||||
clk[IMX21_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
|
||||
clk[IMX21_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);
|
||||
|
||||
clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
|
||||
clk[IMX21_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
|
||||
clk[IMX21_CLK_FPM_GATE] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2);
|
||||
clk[IMX21_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
|
||||
clk[IMX21_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
|
||||
clk[IMX21_CLK_IPG] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
|
||||
clk[IMX21_CLK_HCLK] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
|
||||
clk[IMX21_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
|
||||
clk[IMX21_CLK_SPLL_SEL] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks));
|
||||
clk[IMX21_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 19, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
|
||||
clk[IMX21_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 20, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
|
||||
clk[IMX21_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3);
|
||||
clk[IMX21_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3);
|
||||
|
||||
clk[IMX21_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
|
||||
|
||||
clk[IMX21_CLK_SPLL] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
|
||||
|
||||
clk[IMX21_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4);
|
||||
clk[IMX21_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
|
||||
clk[IMX21_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
|
||||
|
||||
clk[IMX21_CLK_PER1] = imx_clk_divider("per1", "mpll_gate", CCM_PCDR1, 0, 6);
|
||||
clk[IMX21_CLK_PER2] = imx_clk_divider("per2", "mpll_gate", CCM_PCDR1, 8, 6);
|
||||
clk[IMX21_CLK_PER3] = imx_clk_divider("per3", "mpll_gate", CCM_PCDR1, 16, 6);
|
||||
clk[IMX21_CLK_PER4] = imx_clk_divider("per4", "mpll_gate", CCM_PCDR1, 24, 6);
|
||||
|
||||
clk[IMX21_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
|
||||
clk[IMX21_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
|
||||
clk[IMX21_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
|
||||
clk[IMX21_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
|
||||
clk[IMX21_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
|
||||
clk[IMX21_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
|
||||
clk[IMX21_CLK_SSI1_GATE] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
|
||||
clk[IMX21_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
|
||||
clk[IMX21_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
|
||||
clk[IMX21_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
|
||||
clk[IMX21_CLK_GPIO_GATE] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
|
||||
clk[IMX21_CLK_I2C_GATE] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
|
||||
clk[IMX21_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
|
||||
clk[IMX21_CLK_USB_GATE] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
|
||||
clk[IMX21_CLK_EMMA_GATE] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
|
||||
clk[IMX21_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16);
|
||||
clk[IMX21_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17);
|
||||
clk[IMX21_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
|
||||
clk[IMX21_CLK_NFC_GATE] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
|
||||
clk[IMX21_CLK_SLCDC_HCLK_GATE] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
|
||||
clk[IMX21_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
|
||||
clk[IMX21_CLK_BMI_GATE] = imx_clk_gate("bmi_gate", "hclk", CCM_PCCR0, 23);
|
||||
clk[IMX21_CLK_USB_HCLK_GATE] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
|
||||
clk[IMX21_CLK_SLCDC_GATE] = imx_clk_gate("slcdc_gate", "hclk", CCM_PCCR0, 25);
|
||||
clk[IMX21_CLK_LCDC_HCLK_GATE] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
|
||||
clk[IMX21_CLK_EMMA_HCLK_GATE] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
|
||||
clk[IMX21_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
|
||||
clk[IMX21_CLK_DMA_HCLK_GATE] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
|
||||
clk[IMX21_CLK_CSI_HCLK_GATE] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
|
||||
|
||||
clk[IMX21_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
|
||||
clk[IMX21_CLK_WDOG_GATE] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
|
||||
clk[IMX21_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
|
||||
clk[IMX21_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
|
||||
clk[IMX21_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
|
||||
clk[IMX21_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
|
||||
clk[IMX21_CLK_RTC_GATE] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
|
||||
clk[IMX21_CLK_KPP_GATE] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
|
||||
clk[IMX21_CLK_OWIRE_GATE] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
|
||||
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
}
|
||||
|
||||
/*
|
||||
* must be called very early to get information about the
|
||||
* available clock rate when the timer framework starts
|
||||
*/
|
||||
int __init mx21_clocks_init(unsigned long lref, unsigned long href)
|
||||
{
|
||||
int i;
|
||||
ccm = ioremap(MX21_CCM_BASE_ADDR, SZ_2K);
|
||||
|
||||
clk[ckil] = imx_clk_fixed("ckil", lref);
|
||||
clk[ckih] = imx_clk_fixed("ckih", href);
|
||||
clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
|
||||
clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
|
||||
ARRAY_SIZE(mpll_sel_clks));
|
||||
clk[spll_sel] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks,
|
||||
ARRAY_SIZE(spll_sel_clks));
|
||||
clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
|
||||
clk[spll] = imx_clk_pllv1("spll", "spll_sel", CCM_SPCTL0);
|
||||
clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 29, 3);
|
||||
clk[hclk] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4);
|
||||
clk[ipg] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1);
|
||||
clk[per1] = imx_clk_divider("per1", "mpll", CCM_PCDR1, 0, 6);
|
||||
clk[per2] = imx_clk_divider("per2", "mpll", CCM_PCDR1, 8, 6);
|
||||
clk[per3] = imx_clk_divider("per3", "mpll", CCM_PCDR1, 16, 6);
|
||||
clk[per4] = imx_clk_divider("per4", "mpll", CCM_PCDR1, 24, 6);
|
||||
clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0);
|
||||
clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1);
|
||||
clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2);
|
||||
clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3);
|
||||
clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25);
|
||||
clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26);
|
||||
clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27);
|
||||
clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28);
|
||||
clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9);
|
||||
clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10);
|
||||
clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18);
|
||||
clk[lcdc_hclk_gate] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26);
|
||||
clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23);
|
||||
clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5);
|
||||
clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4);
|
||||
clk[per4_gate] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22);
|
||||
clk[csi_hclk_gate] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31);
|
||||
clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 26, 3);
|
||||
clk[usb_gate] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14);
|
||||
clk[usb_hclk_gate] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24);
|
||||
clk[ssi1_gate] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6);
|
||||
clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7);
|
||||
clk[nfc_div] = imx_clk_divider("nfc_div", "ipg", CCM_PCDR0, 12, 4);
|
||||
clk[nfc_gate] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19);
|
||||
clk[dma_gate] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13);
|
||||
clk[dma_hclk_gate] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30);
|
||||
clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28);
|
||||
clk[emma_gate] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15);
|
||||
clk[emma_hclk_gate] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27);
|
||||
clk[slcdc_gate] = imx_clk_gate("slcdc_gate", "ipg", CCM_PCCR0, 25);
|
||||
clk[slcdc_hclk_gate] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21);
|
||||
clk[wdog_gate] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24);
|
||||
clk[gpio_gate] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11);
|
||||
clk[i2c_gate] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12);
|
||||
clk[kpp_gate] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30);
|
||||
clk[owire_gate] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31);
|
||||
clk[rtc_gate] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29);
|
||||
_mx21_clocks_init(lref, href);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX21 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
clk_register_clkdev(clk[per1], "per1", NULL);
|
||||
clk_register_clkdev(clk[per2], "per2", NULL);
|
||||
clk_register_clkdev(clk[per3], "per3", NULL);
|
||||
clk_register_clkdev(clk[per4], "per4", NULL);
|
||||
clk_register_clkdev(clk[per1], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[per1], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[per1], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[per1], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
|
||||
clk_register_clkdev(clk[per1], "per", "imx-gpt.1");
|
||||
clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
|
||||
clk_register_clkdev(clk[per1], "per", "imx-gpt.2");
|
||||
clk_register_clkdev(clk[per2], "per", "imx21-cspi.0");
|
||||
clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx21-cspi.0");
|
||||
clk_register_clkdev(clk[per2], "per", "imx21-cspi.1");
|
||||
clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx21-cspi.1");
|
||||
clk_register_clkdev(clk[per2], "per", "imx21-cspi.2");
|
||||
clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx21-cspi.2");
|
||||
clk_register_clkdev(clk[per3], "per", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");
|
||||
clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");
|
||||
clk_register_clkdev(clk[nfc_gate], NULL, "imx21-nand.0");
|
||||
clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx21-dma");
|
||||
clk_register_clkdev(clk[dma_gate], "ipg", "imx21-dma");
|
||||
clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[i2c_gate], NULL, "imx21-i2c.0");
|
||||
clk_register_clkdev(clk[kpp_gate], NULL, "mxc-keypad");
|
||||
clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
|
||||
clk_register_clkdev(clk[brom_gate], "brom", NULL);
|
||||
clk_register_clkdev(clk[emma_gate], "emma", NULL);
|
||||
clk_register_clkdev(clk[slcdc_gate], "slcdc", NULL);
|
||||
clk_register_clkdev(clk[gpio_gate], "gpio", NULL);
|
||||
clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
|
||||
clk_register_clkdev(clk[csi_hclk_gate], "csi", NULL);
|
||||
clk_register_clkdev(clk[ssi1_gate], "ssi1", NULL);
|
||||
clk_register_clkdev(clk[ssi2_gate], "ssi2", NULL);
|
||||
clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
|
||||
clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[IMX21_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[IMX21_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[IMX21_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[IMX21_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_CSPI1_IPG_GATE], "ipg", "imx21-cspi.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.1");
|
||||
clk_register_clkdev(clk[IMX21_CLK_CSPI2_IPG_GATE], "ipg", "imx21-cspi.1");
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.2");
|
||||
clk_register_clkdev(clk[IMX21_CLK_CSPI3_IPG_GATE], "ipg", "imx21-cspi.2");
|
||||
clk_register_clkdev(clk[IMX21_CLK_PER3], "per", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_LCDC_HCLK_GATE], "ahb", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_USB_GATE], "per", "imx21-hcd.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_USB_HCLK_GATE], "ahb", "imx21-hcd.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_NFC_GATE], NULL, "imx21-nand.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_DMA_HCLK_GATE], "ahb", "imx21-dma");
|
||||
clk_register_clkdev(clk[IMX21_CLK_DMA_GATE], "ipg", "imx21-dma");
|
||||
clk_register_clkdev(clk[IMX21_CLK_WDOG_GATE], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0");
|
||||
clk_register_clkdev(clk[IMX21_CLK_OWIRE_GATE], NULL, "mxc_w1.0");
|
||||
|
||||
mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init mx21_clocks_init_dt(struct device_node *np)
|
||||
{
|
||||
ccm = of_iomap(np, 0);
|
||||
|
||||
_mx21_clocks_init(32768, 26000000);
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
CLK_OF_DECLARE(imx27_ccm, "fsl,imx21-ccm", mx21_clocks_init_dt);
|
||||
|
||||
@ -32,8 +32,6 @@
|
||||
#include "hardware.h"
|
||||
#include "mx25.h"
|
||||
|
||||
#define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
|
||||
|
||||
#define CCM_MPCTL 0x00
|
||||
#define CCM_UPCTL 0x04
|
||||
#define CCM_CCTL 0x08
|
||||
@ -56,7 +54,7 @@
|
||||
#define CCM_LTR3 0x4c
|
||||
#define CCM_MCR 0x64
|
||||
|
||||
#define ccm(x) (CRM_BASE + (x))
|
||||
#define ccm(x) (ccm_base + (x))
|
||||
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
@ -91,9 +89,10 @@ enum mx25_clks {
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
|
||||
static int __init __mx25_clocks_init(unsigned long osc_rate)
|
||||
static int __init __mx25_clocks_init(unsigned long osc_rate,
|
||||
void __iomem *ccm_base)
|
||||
{
|
||||
int i;
|
||||
BUG_ON(!ccm_base);
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
clk[osc] = imx_clk_fixed("osc", osc_rate);
|
||||
@ -224,19 +223,13 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
|
||||
/* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */
|
||||
clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX25 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
clk_prepare_enable(clk[emi_ahb]);
|
||||
|
||||
/* Clock source for gpt must be derived from AHB */
|
||||
clk_set_parent(clk[per5_sel], clk[ahb]);
|
||||
|
||||
clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
|
||||
|
||||
/*
|
||||
* Let's initially set up CLKO parent as ipg, since this configuration
|
||||
* is used on some imx25 board designs to clock the audio codec.
|
||||
@ -248,8 +241,14 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
|
||||
|
||||
int __init mx25_clocks_init(void)
|
||||
{
|
||||
__mx25_clocks_init(24000000);
|
||||
void __iomem *ccm;
|
||||
|
||||
ccm = ioremap(MX25_CRM_BASE_ADDR, SZ_16K);
|
||||
|
||||
__mx25_clocks_init(24000000, ccm);
|
||||
|
||||
clk_register_clkdev(clk[gpt1_ipg], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
|
||||
/* i.mx25 has the i.mx21 type uart */
|
||||
clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
|
||||
@ -314,29 +313,27 @@ int __init mx25_clocks_init(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init mx25_clocks_init_dt(void)
|
||||
static void __init mx25_clocks_init_dt(struct device_node *np)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct device_node *refnp;
|
||||
unsigned long osc_rate = 24000000;
|
||||
void __iomem *ccm;
|
||||
|
||||
/* retrieve the freqency of fixed clocks from device tree */
|
||||
for_each_compatible_node(np, NULL, "fixed-clock") {
|
||||
for_each_compatible_node(refnp, NULL, "fixed-clock") {
|
||||
u32 rate;
|
||||
if (of_property_read_u32(np, "clock-frequency", &rate))
|
||||
if (of_property_read_u32(refnp, "clock-frequency", &rate))
|
||||
continue;
|
||||
|
||||
if (of_device_is_compatible(np, "fsl,imx-osc"))
|
||||
if (of_device_is_compatible(refnp, "fsl,imx-osc"))
|
||||
osc_rate = rate;
|
||||
}
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
|
||||
ccm = of_iomap(np, 0);
|
||||
__mx25_clocks_init(osc_rate, ccm);
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
__mx25_clocks_init(osc_rate);
|
||||
|
||||
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt"));
|
||||
|
||||
return 0;
|
||||
}
|
||||
CLK_OF_DECLARE(imx25_ccm, "fsl,imx25-ccm", mx25_clocks_init_dt);
|
||||
|
||||
@ -1,61 +1,36 @@
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <dt-bindings/clock/imx27-clock.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "common.h"
|
||||
#include "hardware.h"
|
||||
|
||||
#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
|
||||
static void __iomem *ccm __initdata;
|
||||
|
||||
/* Register offsets */
|
||||
#define CCM_CSCR IO_ADDR_CCM(0x0)
|
||||
#define CCM_MPCTL0 IO_ADDR_CCM(0x4)
|
||||
#define CCM_MPCTL1 IO_ADDR_CCM(0x8)
|
||||
#define CCM_SPCTL0 IO_ADDR_CCM(0xc)
|
||||
#define CCM_SPCTL1 IO_ADDR_CCM(0x10)
|
||||
#define CCM_OSC26MCTL IO_ADDR_CCM(0x14)
|
||||
#define CCM_PCDR0 IO_ADDR_CCM(0x18)
|
||||
#define CCM_PCDR1 IO_ADDR_CCM(0x1c)
|
||||
#define CCM_PCCR0 IO_ADDR_CCM(0x20)
|
||||
#define CCM_PCCR1 IO_ADDR_CCM(0x24)
|
||||
#define CCM_CCSR IO_ADDR_CCM(0x28)
|
||||
#define CCM_PMCTL IO_ADDR_CCM(0x2c)
|
||||
#define CCM_PMCOUNT IO_ADDR_CCM(0x30)
|
||||
#define CCM_WKGDCTL IO_ADDR_CCM(0x34)
|
||||
|
||||
#define CCM_CSCR_UPDATE_DIS (1 << 31)
|
||||
#define CCM_CSCR_SSI2 (1 << 23)
|
||||
#define CCM_CSCR_SSI1 (1 << 22)
|
||||
#define CCM_CSCR_VPU (1 << 21)
|
||||
#define CCM_CSCR_MSHC (1 << 20)
|
||||
#define CCM_CSCR_SPLLRES (1 << 19)
|
||||
#define CCM_CSCR_MPLLRES (1 << 18)
|
||||
#define CCM_CSCR_SP (1 << 17)
|
||||
#define CCM_CSCR_MCU (1 << 16)
|
||||
#define CCM_CSCR_OSC26MDIV (1 << 4)
|
||||
#define CCM_CSCR_OSC26M (1 << 3)
|
||||
#define CCM_CSCR_FPM (1 << 2)
|
||||
#define CCM_CSCR_SPEN (1 << 1)
|
||||
#define CCM_CSCR_MPEN (1 << 0)
|
||||
|
||||
/* i.MX27 TO 2+ */
|
||||
#define CCM_CSCR_ARM_SRC (1 << 15)
|
||||
|
||||
#define CCM_SPCTL1_LF (1 << 15)
|
||||
#define CCM_SPCTL1_BRMO (1 << 6)
|
||||
#define CCM_CSCR (ccm + 0x00)
|
||||
#define CCM_MPCTL0 (ccm + 0x04)
|
||||
#define CCM_MPCTL1 (ccm + 0x08)
|
||||
#define CCM_SPCTL0 (ccm + 0x0c)
|
||||
#define CCM_SPCTL1 (ccm + 0x10)
|
||||
#define CCM_PCDR0 (ccm + 0x18)
|
||||
#define CCM_PCDR1 (ccm + 0x1c)
|
||||
#define CCM_PCCR0 (ccm + 0x20)
|
||||
#define CCM_PCCR1 (ccm + 0x24)
|
||||
#define CCM_CCSR (ccm + 0x28)
|
||||
|
||||
static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
|
||||
static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
|
||||
static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", };
|
||||
static const char *mpll_osc_sel_clks[] = { "ckih", "ckih_div1p5", };
|
||||
static const char *mpll_osc_sel_clks[] = { "ckih_gate", "ckih_div1p5", };
|
||||
static const char *clko_sel_clks[] = {
|
||||
"ckil", "fpm", "ckih", "ckih",
|
||||
"ckih", "mpll", "spll", "cpu_div",
|
||||
"ckil", "fpm", "ckih_gate", "ckih_gate",
|
||||
"ckih_gate", "mpll", "spll", "cpu_div",
|
||||
"ahb", "ipg", "per1_div", "per2_div",
|
||||
"per3_div", "per4_div", "ssi1_div", "ssi2_div",
|
||||
"nfc_div", "mshc_div", "vpu_div", "60m",
|
||||
@ -64,239 +39,220 @@ static const char *clko_sel_clks[] = {
|
||||
|
||||
static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
|
||||
|
||||
enum mx27_clks {
|
||||
dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
|
||||
per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel,
|
||||
clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div,
|
||||
clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate,
|
||||
sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate,
|
||||
rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate,
|
||||
kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate,
|
||||
gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate,
|
||||
gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate,
|
||||
emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate,
|
||||
cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate,
|
||||
vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate,
|
||||
usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate,
|
||||
vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
|
||||
csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
|
||||
uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
|
||||
uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
|
||||
mpll_sel, spll_gate, mshc_div, rtic_ipg_gate, mshc_ipg_gate,
|
||||
rtic_ahb_gate, mshc_baud_gate, clk_max
|
||||
};
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
static struct clk *clk[IMX27_CLK_MAX];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static void __init _mx27_clocks_init(unsigned long fref)
|
||||
{
|
||||
BUG_ON(!ccm);
|
||||
|
||||
clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref);
|
||||
clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768);
|
||||
clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
|
||||
clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3);
|
||||
clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3);
|
||||
clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks));
|
||||
clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks));
|
||||
clk[IMX27_CLK_MPLL] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
|
||||
clk[IMX27_CLK_SPLL] = imx_clk_pllv1("spll", "ckih_gate", CCM_SPCTL0);
|
||||
clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
|
||||
clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
|
||||
|
||||
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
|
||||
clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
|
||||
clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
|
||||
} else {
|
||||
clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
|
||||
clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
|
||||
}
|
||||
|
||||
clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
|
||||
clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
|
||||
clk[IMX27_CLK_PER1_DIV] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
|
||||
clk[IMX27_CLK_PER2_DIV] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
|
||||
clk[IMX27_CLK_PER3_DIV] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
|
||||
clk[IMX27_CLK_PER4_DIV] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
|
||||
clk[IMX27_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
|
||||
clk[IMX27_CLK_VPU_DIV] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
|
||||
clk[IMX27_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
|
||||
clk[IMX27_CLK_CPU_SEL] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
|
||||
clk[IMX27_CLK_CLKO_SEL] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
|
||||
|
||||
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
|
||||
clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
|
||||
else
|
||||
clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
|
||||
|
||||
clk[IMX27_CLK_CLKO_DIV] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
|
||||
clk[IMX27_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
|
||||
clk[IMX27_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
|
||||
clk[IMX27_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
|
||||
clk[IMX27_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
|
||||
clk[IMX27_CLK_CLKO_EN] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
|
||||
clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
|
||||
clk[IMX27_CLK_SSI1_IPG_GATE] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
|
||||
clk[IMX27_CLK_SLCDC_IPG_GATE] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
|
||||
clk[IMX27_CLK_SDHC3_IPG_GATE] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
|
||||
clk[IMX27_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
|
||||
clk[IMX27_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
|
||||
clk[IMX27_CLK_SCC_IPG_GATE] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
|
||||
clk[IMX27_CLK_SAHARA_IPG_GATE] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
|
||||
clk[IMX27_CLK_RTIC_IPG_GATE] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
|
||||
clk[IMX27_CLK_RTC_IPG_GATE] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
|
||||
clk[IMX27_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
|
||||
clk[IMX27_CLK_OWIRE_IPG_GATE] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
|
||||
clk[IMX27_CLK_MSHC_IPG_GATE] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
|
||||
clk[IMX27_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
|
||||
clk[IMX27_CLK_KPP_IPG_GATE] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
|
||||
clk[IMX27_CLK_IIM_IPG_GATE] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
|
||||
clk[IMX27_CLK_I2C2_IPG_GATE] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
|
||||
clk[IMX27_CLK_I2C1_IPG_GATE] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
|
||||
clk[IMX27_CLK_GPT6_IPG_GATE] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
|
||||
clk[IMX27_CLK_GPT5_IPG_GATE] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
|
||||
clk[IMX27_CLK_GPT4_IPG_GATE] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
|
||||
clk[IMX27_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
|
||||
clk[IMX27_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
|
||||
clk[IMX27_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
|
||||
clk[IMX27_CLK_GPIO_IPG_GATE] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
|
||||
clk[IMX27_CLK_FEC_IPG_GATE] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
|
||||
clk[IMX27_CLK_EMMA_IPG_GATE] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
|
||||
clk[IMX27_CLK_DMA_IPG_GATE] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
|
||||
clk[IMX27_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
|
||||
clk[IMX27_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
|
||||
clk[IMX27_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
|
||||
clk[IMX27_CLK_MSHC_BAUD_GATE] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
|
||||
clk[IMX27_CLK_NFC_BAUD_GATE] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3);
|
||||
clk[IMX27_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4);
|
||||
clk[IMX27_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5);
|
||||
clk[IMX27_CLK_VPU_BAUD_GATE] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6);
|
||||
clk[IMX27_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7);
|
||||
clk[IMX27_CLK_PER3_GATE] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8);
|
||||
clk[IMX27_CLK_PER2_GATE] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9);
|
||||
clk[IMX27_CLK_PER1_GATE] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
|
||||
clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
|
||||
clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
|
||||
clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
|
||||
clk[IMX27_CLK_RTIC_AHB_GATE] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
|
||||
clk[IMX27_CLK_LCDC_AHB_GATE] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
|
||||
clk[IMX27_CLK_VPU_AHB_GATE] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
|
||||
clk[IMX27_CLK_FEC_AHB_GATE] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
|
||||
clk[IMX27_CLK_EMMA_AHB_GATE] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
|
||||
clk[IMX27_CLK_EMI_AHB_GATE] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
|
||||
clk[IMX27_CLK_DMA_AHB_GATE] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
|
||||
clk[IMX27_CLK_CSI_AHB_GATE] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
|
||||
clk[IMX27_CLK_BROM_AHB_GATE] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
|
||||
clk[IMX27_CLK_ATA_AHB_GATE] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
|
||||
clk[IMX27_CLK_WDOG_IPG_GATE] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
|
||||
clk[IMX27_CLK_USB_IPG_GATE] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
|
||||
clk[IMX27_CLK_UART6_IPG_GATE] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
|
||||
clk[IMX27_CLK_UART5_IPG_GATE] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
|
||||
clk[IMX27_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
|
||||
clk[IMX27_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
|
||||
clk[IMX27_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
|
||||
clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
|
||||
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0");
|
||||
|
||||
clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
|
||||
|
||||
imx_print_silicon_rev("i.MX27", mx27_revision());
|
||||
}
|
||||
|
||||
int __init mx27_clocks_init(unsigned long fref)
|
||||
{
|
||||
int i;
|
||||
struct device_node *np;
|
||||
ccm = ioremap(MX27_CCM_BASE_ADDR, SZ_4K);
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
clk[ckih] = imx_clk_fixed("ckih", fref);
|
||||
clk[ckil] = imx_clk_fixed("ckil", 32768);
|
||||
clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
|
||||
clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
|
||||
_mx27_clocks_init(fref);
|
||||
|
||||
clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1,
|
||||
mpll_osc_sel_clks,
|
||||
ARRAY_SIZE(mpll_osc_sel_clks));
|
||||
clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
|
||||
ARRAY_SIZE(mpll_sel_clks));
|
||||
clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
|
||||
clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
|
||||
clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
|
||||
clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
|
||||
|
||||
if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
|
||||
clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
|
||||
clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
|
||||
} else {
|
||||
clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
|
||||
clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
|
||||
}
|
||||
|
||||
clk[mshc_div] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
|
||||
clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
|
||||
clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
|
||||
clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
|
||||
clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
|
||||
clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
|
||||
clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
|
||||
clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
|
||||
clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
|
||||
clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
|
||||
clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
|
||||
if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
|
||||
clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
|
||||
else
|
||||
clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
|
||||
clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
|
||||
clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
|
||||
clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
|
||||
clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
|
||||
clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
|
||||
clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
|
||||
clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
|
||||
clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
|
||||
clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
|
||||
clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
|
||||
clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
|
||||
clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
|
||||
clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
|
||||
clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
|
||||
clk[rtic_ipg_gate] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
|
||||
clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
|
||||
clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
|
||||
clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
|
||||
clk[mshc_ipg_gate] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
|
||||
clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
|
||||
clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
|
||||
clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
|
||||
clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
|
||||
clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
|
||||
clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
|
||||
clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
|
||||
clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
|
||||
clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
|
||||
clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
|
||||
clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
|
||||
clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
|
||||
clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
|
||||
clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
|
||||
clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
|
||||
clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
|
||||
clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
|
||||
clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
|
||||
clk[mshc_baud_gate] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
|
||||
clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3);
|
||||
clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4);
|
||||
clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5);
|
||||
clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6);
|
||||
clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7);
|
||||
clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8);
|
||||
clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9);
|
||||
clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
|
||||
clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
|
||||
clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
|
||||
clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
|
||||
clk[rtic_ahb_gate] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
|
||||
clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
|
||||
clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
|
||||
clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
|
||||
clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
|
||||
clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
|
||||
clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
|
||||
clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
|
||||
clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
|
||||
clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
|
||||
clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
|
||||
clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
|
||||
clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
|
||||
clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
|
||||
clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
|
||||
clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
|
||||
clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
|
||||
clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX27 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx27-ccm");
|
||||
if (np) {
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
|
||||
clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5");
|
||||
clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
|
||||
clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
|
||||
clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2");
|
||||
clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0");
|
||||
clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1");
|
||||
clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1");
|
||||
clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2");
|
||||
clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2");
|
||||
clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
|
||||
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
|
||||
clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0");
|
||||
clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
|
||||
clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
|
||||
clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma");
|
||||
clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma");
|
||||
clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
|
||||
clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0");
|
||||
clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx21-i2c.0");
|
||||
clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx21-i2c.1");
|
||||
clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0");
|
||||
clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad");
|
||||
clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
|
||||
clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
|
||||
clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5");
|
||||
clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_CSI_AHB_GATE], "ahb", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_PER4_GATE], "per", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "imx-udc-mx27");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX27_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_NFC_BAUD_GATE], NULL, "imx27-nand.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_VPU_BAUD_GATE], "per", "coda-imx27.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_VPU_AHB_GATE], "ahb", "coda-imx27.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_DMA_AHB_GATE], "ahb", "imx27-dma");
|
||||
clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma");
|
||||
clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_FEC_AHB_GATE], "ahb", "imx27-fec.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_WDOG_IPG_GATE], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1");
|
||||
clk_register_clkdev(clk[IMX27_CLK_OWIRE_IPG_GATE], NULL, "mxc_w1.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_KPP_IPG_GATE], NULL, "imx-keypad");
|
||||
clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "emma-ahb", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0");
|
||||
clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0");
|
||||
|
||||
mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
|
||||
|
||||
clk_prepare_enable(clk[emi_ahb_gate]);
|
||||
|
||||
imx_print_silicon_rev("i.MX27", mx27_revision());
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __init mx27_clocks_init_dt(void)
|
||||
static void __init mx27_clocks_init_dt(struct device_node *np)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct device_node *refnp;
|
||||
u32 fref = 26000000; /* default */
|
||||
|
||||
for_each_compatible_node(np, NULL, "fixed-clock") {
|
||||
if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
|
||||
for_each_compatible_node(refnp, NULL, "fixed-clock") {
|
||||
if (!of_device_is_compatible(refnp, "fsl,imx-osc26m"))
|
||||
continue;
|
||||
|
||||
if (!of_property_read_u32(np, "clock-frequency", &fref))
|
||||
if (!of_property_read_u32(refnp, "clock-frequency", &fref))
|
||||
break;
|
||||
}
|
||||
|
||||
return mx27_clocks_init(fref);
|
||||
ccm = of_iomap(np, 0);
|
||||
|
||||
_mx27_clocks_init(fref);
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
}
|
||||
CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm", mx27_clocks_init_dt);
|
||||
|
||||
@ -51,7 +51,6 @@ static struct clk_onecell_data clk_data;
|
||||
int __init mx31_clocks_init(unsigned long fref)
|
||||
{
|
||||
void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
|
||||
int i;
|
||||
struct device_node *np;
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
@ -114,10 +113,7 @@ int __init mx31_clocks_init(unsigned long fref)
|
||||
clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
|
||||
clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("imx31 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
|
||||
|
||||
|
||||
@ -75,7 +75,6 @@ int __init mx35_clocks_init(void)
|
||||
u32 pdr0, consumer_sel, hsp_sel;
|
||||
struct arm_ahb_div *aad;
|
||||
unsigned char *hsp_div;
|
||||
u32 i;
|
||||
|
||||
pdr0 = __raw_readl(base + MXC_CCM_PDR0);
|
||||
consumer_sel = (pdr0 >> 16) & 0xf;
|
||||
@ -200,10 +199,7 @@ int __init mx35_clocks_init(void)
|
||||
clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2);
|
||||
clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX35 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
|
||||
clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
|
||||
|
||||
@ -18,11 +18,54 @@
|
||||
#include <linux/of_irq.h>
|
||||
#include <dt-bindings/clock/imx5-clock.h>
|
||||
|
||||
#include "crm-regs-imx5.h"
|
||||
#include "clk.h"
|
||||
#include "common.h"
|
||||
#include "hardware.h"
|
||||
|
||||
#define MX51_DPLL1_BASE 0x83f80000
|
||||
#define MX51_DPLL2_BASE 0x83f84000
|
||||
#define MX51_DPLL3_BASE 0x83f88000
|
||||
|
||||
#define MX53_DPLL1_BASE 0x63f80000
|
||||
#define MX53_DPLL2_BASE 0x63f84000
|
||||
#define MX53_DPLL3_BASE 0x63f88000
|
||||
#define MX53_DPLL4_BASE 0x63f8c000
|
||||
|
||||
#define MXC_CCM_CCR (ccm_base + 0x00)
|
||||
#define MXC_CCM_CCDR (ccm_base + 0x04)
|
||||
#define MXC_CCM_CSR (ccm_base + 0x08)
|
||||
#define MXC_CCM_CCSR (ccm_base + 0x0c)
|
||||
#define MXC_CCM_CACRR (ccm_base + 0x10)
|
||||
#define MXC_CCM_CBCDR (ccm_base + 0x14)
|
||||
#define MXC_CCM_CBCMR (ccm_base + 0x18)
|
||||
#define MXC_CCM_CSCMR1 (ccm_base + 0x1c)
|
||||
#define MXC_CCM_CSCMR2 (ccm_base + 0x20)
|
||||
#define MXC_CCM_CSCDR1 (ccm_base + 0x24)
|
||||
#define MXC_CCM_CS1CDR (ccm_base + 0x28)
|
||||
#define MXC_CCM_CS2CDR (ccm_base + 0x2c)
|
||||
#define MXC_CCM_CDCDR (ccm_base + 0x30)
|
||||
#define MXC_CCM_CHSCDR (ccm_base + 0x34)
|
||||
#define MXC_CCM_CSCDR2 (ccm_base + 0x38)
|
||||
#define MXC_CCM_CSCDR3 (ccm_base + 0x3c)
|
||||
#define MXC_CCM_CSCDR4 (ccm_base + 0x40)
|
||||
#define MXC_CCM_CWDR (ccm_base + 0x44)
|
||||
#define MXC_CCM_CDHIPR (ccm_base + 0x48)
|
||||
#define MXC_CCM_CDCR (ccm_base + 0x4c)
|
||||
#define MXC_CCM_CTOR (ccm_base + 0x50)
|
||||
#define MXC_CCM_CLPCR (ccm_base + 0x54)
|
||||
#define MXC_CCM_CISR (ccm_base + 0x58)
|
||||
#define MXC_CCM_CIMR (ccm_base + 0x5c)
|
||||
#define MXC_CCM_CCOSR (ccm_base + 0x60)
|
||||
#define MXC_CCM_CGPR (ccm_base + 0x64)
|
||||
#define MXC_CCM_CCGR0 (ccm_base + 0x68)
|
||||
#define MXC_CCM_CCGR1 (ccm_base + 0x6c)
|
||||
#define MXC_CCM_CCGR2 (ccm_base + 0x70)
|
||||
#define MXC_CCM_CCGR3 (ccm_base + 0x74)
|
||||
#define MXC_CCM_CCGR4 (ccm_base + 0x78)
|
||||
#define MXC_CCM_CCGR5 (ccm_base + 0x7c)
|
||||
#define MXC_CCM_CCGR6 (ccm_base + 0x80)
|
||||
#define MXC_CCM_CCGR7 (ccm_base + 0x84)
|
||||
|
||||
/* Low-power Audio Playback Mode clock */
|
||||
static const char *lp_apm_sel[] = { "osc", };
|
||||
|
||||
@ -86,17 +129,15 @@ static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
|
||||
static struct clk *clk[IMX5_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static void __init mx5_clocks_common_init(unsigned long rate_ckil,
|
||||
unsigned long rate_osc, unsigned long rate_ckih1,
|
||||
unsigned long rate_ckih2)
|
||||
static void __init mx5_clocks_common_init(void __iomem *ccm_base)
|
||||
{
|
||||
int i;
|
||||
imx5_pm_set_ccm_base(ccm_base);
|
||||
|
||||
clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", rate_ckil);
|
||||
clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", rate_osc);
|
||||
clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
|
||||
clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
|
||||
clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
|
||||
clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
|
||||
clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0);
|
||||
clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0);
|
||||
|
||||
clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
|
||||
periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
|
||||
@ -244,58 +285,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
|
||||
clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
|
||||
clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX5 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
clk_register_clkdev(clk[IMX5_CLK_GPT_HF_GATE], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_GPT_IPG_GATE], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART1_PER_GATE], "per", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART2_PER_GATE], "per", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART3_PER_GATE], "per", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART4_PER_GATE], "per", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART5_PER_GATE], "per", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[IMX5_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ECSPI1_PER_GATE], "per", "imx51-ecspi.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ECSPI1_IPG_GATE], "ipg", "imx51-ecspi.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ECSPI2_PER_GATE], "per", "imx51-ecspi.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ECSPI2_IPG_GATE], "ipg", "imx51-ecspi.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_CSPI_IPG_GATE], NULL, "imx35-cspi.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_I2C1_GATE], NULL, "imx21-i2c.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_I2C2_GATE], NULL, "imx21-i2c.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "mxc-ehci.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_PER_GATE], "per", "imx-udc-mx51");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ipg", "imx-udc-mx51");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USBOH3_GATE], "ahb", "imx-udc-mx51");
|
||||
clk_register_clkdev(clk[IMX5_CLK_NFC_GATE], NULL, "imx51-nand");
|
||||
clk_register_clkdev(clk[IMX5_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_SSI3_IPG_GATE], NULL, "imx-ssi.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_SDMA_GATE], NULL, "imx35-sdma");
|
||||
clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_IIM_GATE], "iim", NULL);
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx2-wdt.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], NULL, "imx-keypad");
|
||||
clk_register_clkdev(clk[IMX5_CLK_IPU_DI1_GATE], "di1", "imx-tve.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
|
||||
clk_register_clkdev(clk[IMX5_CLK_EPIT1_IPG_GATE], "ipg", "imx-epit.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_EPIT1_HF_GATE], "per", "imx-epit.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_EPIT2_IPG_GATE], "ipg", "imx-epit.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_EPIT2_HF_GATE], "per", "imx-epit.1");
|
||||
|
||||
/* Set SDHC parents to be PLL2 */
|
||||
clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
|
||||
@ -322,12 +313,26 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
|
||||
|
||||
static void __init mx50_clocks_init(struct device_node *np)
|
||||
{
|
||||
void __iomem *ccm_base;
|
||||
void __iomem *pll_base;
|
||||
unsigned long r;
|
||||
int i;
|
||||
|
||||
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
|
||||
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
|
||||
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
|
||||
pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
|
||||
|
||||
pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
|
||||
|
||||
pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
|
||||
|
||||
ccm_base = of_iomap(np, 0);
|
||||
WARN_ON(!ccm_base);
|
||||
|
||||
mx5_clocks_common_init(ccm_base);
|
||||
|
||||
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
|
||||
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
|
||||
@ -349,17 +354,12 @@ static void __init mx50_clocks_init(struct device_node *np)
|
||||
clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
|
||||
clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX50 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
mx5_clocks_common_init(0, 0, 0, 0);
|
||||
|
||||
/* set SDHC root clock to 200MHZ*/
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
|
||||
@ -370,21 +370,32 @@ static void __init mx50_clocks_init(struct device_node *np)
|
||||
|
||||
r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
|
||||
clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
|
||||
|
||||
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt"));
|
||||
}
|
||||
CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
|
||||
|
||||
int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
||||
unsigned long rate_ckih1, unsigned long rate_ckih2)
|
||||
static void __init mx51_clocks_init(struct device_node *np)
|
||||
{
|
||||
int i;
|
||||
void __iomem *ccm_base;
|
||||
void __iomem *pll_base;
|
||||
u32 val;
|
||||
struct device_node *np;
|
||||
|
||||
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
|
||||
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
|
||||
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX51_DPLL3_BASE);
|
||||
pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
|
||||
|
||||
pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
|
||||
|
||||
pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
|
||||
|
||||
ccm_base = of_iomap(np, 0);
|
||||
WARN_ON(!ccm_base);
|
||||
|
||||
mx5_clocks_common_init(ccm_base);
|
||||
|
||||
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
|
||||
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
|
||||
clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
|
||||
@ -417,35 +428,12 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
||||
mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
|
||||
clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX51 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
|
||||
|
||||
clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
|
||||
clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx51.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx51.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx51.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx51.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx51.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx51.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx51.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx51.3");
|
||||
|
||||
/* set the usboh3 parent to pll2_sw */
|
||||
clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
|
||||
|
||||
@ -453,9 +441,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
|
||||
|
||||
/* System timer */
|
||||
mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
|
||||
|
||||
clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
|
||||
imx_print_silicon_rev("i.MX51", mx51_revision());
|
||||
clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
|
||||
@ -474,25 +459,35 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
||||
val = readl(MXC_CCM_CLPCR);
|
||||
val |= 1 << 23;
|
||||
writel(val, MXC_CCM_CLPCR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init mx51_clocks_init_dt(struct device_node *np)
|
||||
{
|
||||
mx51_clocks_init(0, 0, 0, 0);
|
||||
}
|
||||
CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt);
|
||||
CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
|
||||
|
||||
static void __init mx53_clocks_init(struct device_node *np)
|
||||
{
|
||||
int i;
|
||||
void __iomem *ccm_base;
|
||||
void __iomem *pll_base;
|
||||
unsigned long r;
|
||||
|
||||
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
|
||||
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
|
||||
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);
|
||||
clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", MX53_DPLL4_BASE);
|
||||
pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
|
||||
|
||||
pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
|
||||
|
||||
pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
|
||||
|
||||
pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);
|
||||
WARN_ON(!pll_base);
|
||||
clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", pll_base);
|
||||
|
||||
ccm_base = of_iomap(np, 0);
|
||||
WARN_ON(!ccm_base);
|
||||
|
||||
mx5_clocks_common_init(ccm_base);
|
||||
|
||||
clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
|
||||
lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
|
||||
@ -543,33 +538,12 @@ static void __init mx53_clocks_init(struct device_node *np)
|
||||
clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
|
||||
mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX53 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
mx5_clocks_common_init(0, 0, 0, 0);
|
||||
|
||||
clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx53.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC1_PER_GATE], "per", "sdhci-esdhc-imx53.0");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_IPG_GATE], "ipg", "sdhci-esdhc-imx53.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC2_PER_GATE], "per", "sdhci-esdhc-imx53.1");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_IPG_GATE], "ipg", "sdhci-esdhc-imx53.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC3_PER_GATE], "per", "sdhci-esdhc-imx53.2");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_IPG_GATE], "ipg", "sdhci-esdhc-imx53.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_DUMMY], "ahb", "sdhci-esdhc-imx53.3");
|
||||
clk_register_clkdev(clk[IMX5_CLK_ESDHC4_PER_GATE], "per", "sdhci-esdhc-imx53.3");
|
||||
|
||||
/* set SDHC root clock to 200MHZ*/
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
|
||||
clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
|
||||
@ -583,7 +557,5 @@ static void __init mx53_clocks_init(struct device_node *np)
|
||||
|
||||
r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
|
||||
clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
|
||||
|
||||
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"));
|
||||
}
|
||||
CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
|
||||
|
||||
@ -19,6 +19,7 @@
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <dt-bindings/clock/imx6qdl-clock.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "common.h"
|
||||
@ -70,51 +71,16 @@ static const char *cko_sels[] = { "cko1", "cko2", };
|
||||
static const char *lvds_sels[] = {
|
||||
"dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
|
||||
"pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
|
||||
"pcie_ref", "sata_ref",
|
||||
"pcie_ref_125m", "sata_ref_100m",
|
||||
};
|
||||
|
||||
enum mx6q_clks {
|
||||
dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
|
||||
pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
|
||||
pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
|
||||
periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
|
||||
esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
|
||||
gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
|
||||
ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
|
||||
ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
|
||||
ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
|
||||
usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
|
||||
emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
|
||||
periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
|
||||
asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
|
||||
gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
|
||||
ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
|
||||
ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
|
||||
ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
|
||||
usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
|
||||
emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
|
||||
mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
|
||||
can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
|
||||
esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
|
||||
hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
|
||||
ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
|
||||
mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
|
||||
gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
|
||||
ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
|
||||
usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
|
||||
pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
|
||||
ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
|
||||
sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
|
||||
usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
|
||||
spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div,
|
||||
lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, esai_ahb, clk_max
|
||||
};
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
static struct clk *clk[IMX6QDL_CLK_END];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static enum mx6q_clks const clks_init_on[] __initconst = {
|
||||
mmdc_ch0_axi, rom, arm,
|
||||
static unsigned int const clks_init_on[] __initconst = {
|
||||
IMX6QDL_CLK_MMDC_CH0_AXI,
|
||||
IMX6QDL_CLK_ROM,
|
||||
IMX6QDL_CLK_ARM,
|
||||
};
|
||||
|
||||
static struct clk_div_table clk_enet_ref_table[] = {
|
||||
@ -149,10 +115,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
||||
int i;
|
||||
int ret;
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
|
||||
clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
|
||||
clk[osc] = imx_obtain_fixed_clock("osc", 0);
|
||||
clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
|
||||
clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
|
||||
clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
|
||||
clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
@ -166,14 +132,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
||||
video_div_table[2].div = 1;
|
||||
};
|
||||
|
||||
/* type name parent_name base div_mask */
|
||||
clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
|
||||
clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
|
||||
clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
|
||||
clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
|
||||
clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
|
||||
clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
|
||||
clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
|
||||
/* type name parent_name base div_mask */
|
||||
clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
|
||||
clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
|
||||
clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
|
||||
clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
|
||||
clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
|
||||
clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
|
||||
clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
|
||||
|
||||
/*
|
||||
* Bit 20 is the reserved and read-only bit, we do this only for:
|
||||
@ -181,28 +147,28 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
||||
* - Keep refcount when do usbphy clk_enable/disable, in that case,
|
||||
* the clk framework may need to enable/disable usbphy's parent
|
||||
*/
|
||||
clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
|
||||
clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
|
||||
clk[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
|
||||
clk[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
|
||||
|
||||
/*
|
||||
* usbphy*_gate needs to be on after system boots up, and software
|
||||
* never needs to control it anymore.
|
||||
*/
|
||||
clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
|
||||
clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
|
||||
clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
|
||||
clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
|
||||
|
||||
clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
|
||||
clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
|
||||
clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
|
||||
clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
|
||||
|
||||
clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
|
||||
clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
|
||||
clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
|
||||
clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
|
||||
|
||||
clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
|
||||
clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
|
||||
base + 0xe0, 0, 2, 0, clk_enet_ref_table,
|
||||
&imx_ccm_lock);
|
||||
|
||||
clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
|
||||
clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
|
||||
clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
|
||||
clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
|
||||
|
||||
/*
|
||||
* lvds1_gate and lvds2_gate are pseudo-gates. Both can be
|
||||
@ -210,29 +176,29 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
||||
* the "output_enable" bit as a gate, even though it's really just
|
||||
* enabling clock output.
|
||||
*/
|
||||
clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
|
||||
clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
|
||||
clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
|
||||
clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
|
||||
|
||||
/* name parent_name reg idx */
|
||||
clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
|
||||
clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
|
||||
clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
|
||||
clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
|
||||
clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
|
||||
clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
|
||||
clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
|
||||
/* name parent_name reg idx */
|
||||
clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
|
||||
clk[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
|
||||
clk[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
|
||||
clk[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
|
||||
clk[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
|
||||
clk[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
|
||||
clk[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
|
||||
|
||||
/* name parent_name mult div */
|
||||
clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
|
||||
clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
|
||||
clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
|
||||
clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
|
||||
clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2);
|
||||
/* name parent_name mult div */
|
||||
clk[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
|
||||
clk[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
|
||||
clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
|
||||
clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
|
||||
clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
|
||||
|
||||
clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
|
||||
clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
|
||||
clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
|
||||
clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
|
||||
clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
|
||||
|
||||
np = ccm_node;
|
||||
base = of_iomap(np, 0);
|
||||
@ -240,262 +206,254 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
||||
|
||||
imx6q_pm_set_ccm_base(base);
|
||||
|
||||
/* name reg shift width parent_names num_parents */
|
||||
clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
|
||||
clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
|
||||
clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
|
||||
clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
|
||||
clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
|
||||
clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
|
||||
clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
|
||||
clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
|
||||
clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
|
||||
clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
|
||||
clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
|
||||
clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
|
||||
clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu1_di0_sel] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu1_di1_sel] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu2_di0_sel] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu2_di1_sel] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
|
||||
clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
|
||||
clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
|
||||
clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[ssi2_sel] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[ssi3_sel] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[usdhc1_sel] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[usdhc2_sel] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[usdhc3_sel] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[usdhc4_sel] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
|
||||
clk[emi_sel] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
|
||||
clk[emi_slow_sel] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
|
||||
clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
|
||||
clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
|
||||
clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
|
||||
clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
|
||||
clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
|
||||
/* name reg shift width parent_names num_parents */
|
||||
clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
|
||||
clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
|
||||
clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
|
||||
clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
|
||||
clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
|
||||
clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
|
||||
clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
|
||||
clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
|
||||
clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
|
||||
clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
|
||||
clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
|
||||
clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
|
||||
clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
|
||||
clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
|
||||
clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
|
||||
clk[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
|
||||
clk[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
|
||||
clk[IMX6QDL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
|
||||
clk[IMX6QDL_CLK_EMI_SEL] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_EMI_SLOW_SEL] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
|
||||
clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
|
||||
clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
|
||||
clk[IMX6QDL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
|
||||
clk[IMX6QDL_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
|
||||
|
||||
/* name reg shift width busy: reg, shift parent_names num_parents */
|
||||
clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
|
||||
clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
|
||||
/* name reg shift width busy: reg, shift parent_names num_parents */
|
||||
clk[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
|
||||
clk[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
|
||||
|
||||
/* name parent_name reg shift width */
|
||||
clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
|
||||
clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
|
||||
clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
|
||||
clk[ipg_per] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
|
||||
clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
|
||||
clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
|
||||
clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
|
||||
clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
|
||||
clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
|
||||
clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
|
||||
clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
|
||||
clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
|
||||
clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
|
||||
clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
|
||||
clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
|
||||
clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
|
||||
clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
|
||||
clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
|
||||
clk[ldb_di0_podf] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
|
||||
clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
|
||||
clk[ldb_di1_podf] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
|
||||
clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
|
||||
clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
|
||||
clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
|
||||
clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
|
||||
clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
|
||||
clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
|
||||
clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
|
||||
clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
|
||||
clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
|
||||
clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
|
||||
clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
|
||||
clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
|
||||
clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
|
||||
clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
|
||||
clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
|
||||
clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
|
||||
clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
|
||||
clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
|
||||
clk[emi_podf] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
|
||||
clk[emi_slow_podf] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
|
||||
clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
|
||||
clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
|
||||
clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
|
||||
/* name parent_name reg shift width */
|
||||
clk[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
|
||||
clk[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
|
||||
clk[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
|
||||
clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
|
||||
clk[IMX6QDL_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
|
||||
clk[IMX6QDL_CLK_ASRC_PRED] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
|
||||
clk[IMX6QDL_CLK_ASRC_PODF] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
|
||||
clk[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
|
||||
clk[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
|
||||
clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
|
||||
clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
|
||||
clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
|
||||
clk[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
|
||||
clk[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
|
||||
clk[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
|
||||
clk[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
|
||||
clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
|
||||
clk[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
|
||||
clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
|
||||
clk[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
|
||||
clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
|
||||
clk[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
|
||||
clk[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
|
||||
clk[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
|
||||
clk[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
|
||||
clk[IMX6QDL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
|
||||
clk[IMX6QDL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
|
||||
clk[IMX6QDL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
|
||||
clk[IMX6QDL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
|
||||
clk[IMX6QDL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
|
||||
clk[IMX6QDL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
|
||||
clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
|
||||
clk[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
|
||||
clk[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
|
||||
clk[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
|
||||
clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
|
||||
clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
|
||||
clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
|
||||
clk[IMX6QDL_CLK_EMI_PODF] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_EMI_SLOW_PODF] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
|
||||
clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
|
||||
clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
|
||||
clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
|
||||
|
||||
/* name parent_name reg shift width busy: reg, shift */
|
||||
clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
|
||||
clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
|
||||
clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
|
||||
clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
|
||||
clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
|
||||
/* name parent_name reg shift width busy: reg, shift */
|
||||
clk[IMX6QDL_CLK_AXI] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
|
||||
clk[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
|
||||
clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
|
||||
clk[IMX6QDL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
|
||||
clk[IMX6QDL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
|
||||
|
||||
/* name parent_name reg shift */
|
||||
clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
|
||||
clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
|
||||
clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
|
||||
clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
|
||||
clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
|
||||
clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
|
||||
clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
|
||||
clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
|
||||
clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
|
||||
clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
|
||||
/* name parent_name reg shift */
|
||||
clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
|
||||
clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
|
||||
clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
|
||||
clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
|
||||
clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
|
||||
clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
|
||||
clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
|
||||
clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
|
||||
clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
|
||||
clk[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
|
||||
if (cpu_is_imx6dl())
|
||||
/* ecspi5 is replaced with i2c4 on imx6dl & imx6s */
|
||||
clk[ecspi5] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
|
||||
clk[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
|
||||
else
|
||||
clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
|
||||
clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
|
||||
clk[esai] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai);
|
||||
clk[esai_ahb] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai);
|
||||
clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
|
||||
clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
|
||||
clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
|
||||
clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
|
||||
clk[IMX6QDL_CLK_ESAI] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai);
|
||||
clk[IMX6QDL_CLK_ESAI_AHB] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai);
|
||||
clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
|
||||
clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
|
||||
if (cpu_is_imx6dl())
|
||||
/*
|
||||
* The multiplexer and divider of imx6q clock gpu3d_shader get
|
||||
* redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
|
||||
*/
|
||||
clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
|
||||
clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
|
||||
else
|
||||
clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
|
||||
clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
|
||||
clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
|
||||
clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
|
||||
clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
|
||||
clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
|
||||
clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
|
||||
clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
|
||||
clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
|
||||
clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
|
||||
clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
|
||||
clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
|
||||
clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
|
||||
clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
|
||||
clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
|
||||
clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
|
||||
clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
|
||||
clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
|
||||
clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
|
||||
clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
|
||||
clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
|
||||
clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
|
||||
clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
|
||||
clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
|
||||
clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
|
||||
clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
|
||||
clk[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
|
||||
clk[IMX6QDL_CLK_ENFC] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
|
||||
clk[IMX6QDL_CLK_VDOA] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
|
||||
clk[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
|
||||
clk[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
|
||||
clk[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
|
||||
clk[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
|
||||
clk[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
|
||||
clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
|
||||
clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
|
||||
clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
|
||||
clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
|
||||
if (cpu_is_imx6dl())
|
||||
/*
|
||||
* The multiplexer and divider of the imx6q clock gpu2d get
|
||||
* redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
|
||||
*/
|
||||
clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18);
|
||||
clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18);
|
||||
else
|
||||
clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
|
||||
clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
|
||||
clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
|
||||
clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
|
||||
clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
|
||||
clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
|
||||
clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
|
||||
clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
|
||||
clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
|
||||
clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
|
||||
clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
|
||||
clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
|
||||
clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
|
||||
clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
|
||||
clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
|
||||
clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
|
||||
clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
|
||||
clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
|
||||
clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
||||
clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
|
||||
clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
|
||||
clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
|
||||
clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
|
||||
clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
|
||||
clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
|
||||
clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
|
||||
clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
|
||||
clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
|
||||
clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
|
||||
clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
|
||||
clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
|
||||
clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
|
||||
clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
|
||||
clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
|
||||
clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
|
||||
clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
|
||||
clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
|
||||
clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
|
||||
clk[IMX6QDL_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
|
||||
clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
|
||||
clk[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
|
||||
clk[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
|
||||
clk[IMX6QDL_CLK_PWM1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
|
||||
clk[IMX6QDL_CLK_PWM2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
|
||||
clk[IMX6QDL_CLK_PWM3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
|
||||
clk[IMX6QDL_CLK_PWM4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
|
||||
clk[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
|
||||
clk[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
|
||||
clk[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
|
||||
clk[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
|
||||
clk[IMX6QDL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
|
||||
clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
|
||||
clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
|
||||
clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
||||
clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
|
||||
clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
|
||||
clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
|
||||
clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
|
||||
clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
|
||||
clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
|
||||
clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
|
||||
clk[IMX6QDL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
|
||||
clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
|
||||
clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
|
||||
clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
|
||||
clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
|
||||
clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
|
||||
clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
|
||||
clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
|
||||
clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clk); i++)
|
||||
if (IS_ERR(clk[i]))
|
||||
pr_err("i.MX6q clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
|
||||
clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);
|
||||
clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
|
||||
|
||||
if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
|
||||
cpu_is_imx6dl()) {
|
||||
clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
}
|
||||
|
||||
clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
|
||||
clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
|
||||
clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
|
||||
clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);
|
||||
|
||||
/*
|
||||
* The gpmi needs 100MHz frequency in the EDO/Sync mode,
|
||||
* We can not get the 100MHz from the pll2_pfd0_352m.
|
||||
* So choose pll2_pfd2_396m as enfc_sel's parent.
|
||||
*/
|
||||
clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
|
||||
clk_prepare_enable(clk[clks_init_on[i]]);
|
||||
|
||||
if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
|
||||
clk_prepare_enable(clk[usbphy1_gate]);
|
||||
clk_prepare_enable(clk[usbphy2_gate]);
|
||||
clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
|
||||
clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
|
||||
}
|
||||
|
||||
/*
|
||||
* Let's initially set up CLKO with OSC24M, since this configuration
|
||||
* is widely used by imx6q board designs to clock audio codec.
|
||||
*/
|
||||
ret = clk_set_parent(clk[cko2_sel], clk[osc]);
|
||||
ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
|
||||
if (!ret)
|
||||
ret = clk_set_parent(clk[cko], clk[cko2]);
|
||||
ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
|
||||
if (ret)
|
||||
pr_warn("failed to set up CLKO: %d\n", ret);
|
||||
|
||||
/* Audio-related clocks configuration */
|
||||
clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
|
||||
|
||||
/* All existing boards with PCIe use LVDS1 */
|
||||
if (IS_ENABLED(CONFIG_PCI_IMX6))
|
||||
clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
|
||||
clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
|
||||
|
||||
/* Set initial power mode */
|
||||
imx6q_set_lpm(WAIT_CLOCKED);
|
||||
|
||||
mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"));
|
||||
}
|
||||
CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
|
||||
|
||||
@ -348,18 +348,12 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
||||
clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
|
||||
clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks); i++)
|
||||
if (IS_ERR(clks[i]))
|
||||
pr_err("i.MX6SL clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clks[i]));
|
||||
imx_check_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
clk_data.clks = clks;
|
||||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
|
||||
|
||||
/* Ensure the AHB clk is at 132MHz. */
|
||||
ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
|
||||
if (ret)
|
||||
@ -383,8 +377,5 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
||||
|
||||
/* Set initial power mode */
|
||||
imx6q_set_lpm(WAIT_CLOCKED);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
|
||||
mxc_timer_init_dt(np);
|
||||
}
|
||||
CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
|
||||
|
||||
@ -124,6 +124,9 @@ static struct clk_div_table video_div_table[] = {
|
||||
static u32 share_count_asrc;
|
||||
static u32 share_count_audio;
|
||||
static u32 share_count_esai;
|
||||
static u32 share_count_ssi1;
|
||||
static u32 share_count_ssi2;
|
||||
static u32 share_count_ssi3;
|
||||
|
||||
static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
||||
{
|
||||
@ -409,12 +412,12 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
||||
clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
||||
clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6SX_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
|
||||
clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
|
||||
clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
|
||||
clks[IMX6SX_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18);
|
||||
clks[IMX6SX_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20);
|
||||
clks[IMX6SX_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22);
|
||||
clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
|
||||
clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
|
||||
clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
|
||||
clks[IMX6SX_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
|
||||
clks[IMX6SX_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
|
||||
clks[IMX6SX_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
|
||||
clks[IMX6SX_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
|
||||
clks[IMX6SX_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_podf", base + 0x7c, 26);
|
||||
clks[IMX6SX_CLK_SAI1_IPG] = imx_clk_gate2("sai1_ipg", "ipg", base + 0x7c, 28);
|
||||
@ -443,17 +446,12 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
||||
/* mask handshake of mmdc */
|
||||
writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks); i++)
|
||||
if (IS_ERR(clks[i]))
|
||||
pr_err("i.MX6sx clk %d: register failed with %ld\n", i, PTR_ERR(clks[i]));
|
||||
imx_check_clocks(clks, ARRAY_SIZE(clks));
|
||||
|
||||
clk_data.clks = clks;
|
||||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
clk_register_clkdev(clks[IMX6SX_CLK_GPT_BUS], "ipg", "imx-gpt.0");
|
||||
clk_register_clkdev(clks[IMX6SX_CLK_GPT_SERIAL], "per", "imx-gpt.0");
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
|
||||
clk_prepare_enable(clks[clks_init_on[i]]);
|
||||
|
||||
@ -517,8 +515,5 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
||||
|
||||
/* Set initial power mode */
|
||||
imx6q_set_lpm(WAIT_CLOCKED);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-gpt");
|
||||
mxc_timer_init_dt(np);
|
||||
}
|
||||
CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
|
||||
|
||||
@ -295,14 +295,18 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
|
||||
|
||||
clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1));
|
||||
|
||||
clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
|
||||
clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
|
||||
clk[VF610_CLK_FLEXCAN0_EN] = imx_clk_gate("flexcan0_en", "ipg_bus", CCM_CSCDR2, 11);
|
||||
clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "flexcan0_en", CCM_CCGR0, CCM_CCGRx_CGn(0));
|
||||
clk[VF610_CLK_FLEXCAN1_EN] = imx_clk_gate("flexcan1_en", "ipg_bus", CCM_CSCDR2, 12);
|
||||
clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "flexcan1_en", CCM_CCGR9, CCM_CCGRx_CGn(4));
|
||||
|
||||
clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4));
|
||||
clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5));
|
||||
clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1));
|
||||
clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2));
|
||||
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
|
||||
clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
|
||||
clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
|
||||
|
||||
@ -7,6 +7,16 @@
|
||||
|
||||
DEFINE_SPINLOCK(imx_ccm_lock);
|
||||
|
||||
void __init imx_check_clocks(struct clk *clks[], unsigned int count)
|
||||
{
|
||||
unsigned i;
|
||||
|
||||
for (i = 0; i < count; i++)
|
||||
if (IS_ERR(clks[i]))
|
||||
pr_err("i.MX clk %u: register failed with %ld\n",
|
||||
i, PTR_ERR(clks[i]));
|
||||
}
|
||||
|
||||
static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
|
||||
{
|
||||
struct of_phandle_args phandle;
|
||||
|
||||
@ -6,6 +6,8 @@
|
||||
|
||||
extern spinlock_t imx_ccm_lock;
|
||||
|
||||
void imx_check_clocks(struct clk *clks[], unsigned int count);
|
||||
|
||||
extern void imx_cscmr1_fixup(u32 *val);
|
||||
|
||||
struct clk *imx_clk_pllv1(const char *name, const char *parent,
|
||||
@ -95,6 +97,13 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent,
|
||||
shift, 0, &imx_ccm_lock);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
|
||||
void __iomem *reg, u8 shift)
|
||||
{
|
||||
return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
|
||||
shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
|
||||
}
|
||||
|
||||
static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
|
||||
u8 shift, u8 width, const char **parents, int num_parents)
|
||||
{
|
||||
|
||||
@ -19,6 +19,7 @@ struct pt_regs;
|
||||
struct clk;
|
||||
struct device_node;
|
||||
enum mxc_cpu_pwr_mode;
|
||||
struct of_device_id;
|
||||
|
||||
void mx1_map_io(void);
|
||||
void mx21_map_io(void);
|
||||
@ -26,48 +27,34 @@ void mx25_map_io(void);
|
||||
void mx27_map_io(void);
|
||||
void mx31_map_io(void);
|
||||
void mx35_map_io(void);
|
||||
void mx51_map_io(void);
|
||||
void mx53_map_io(void);
|
||||
void imx1_init_early(void);
|
||||
void imx21_init_early(void);
|
||||
void imx25_init_early(void);
|
||||
void imx27_init_early(void);
|
||||
void imx31_init_early(void);
|
||||
void imx35_init_early(void);
|
||||
void imx51_init_early(void);
|
||||
void imx53_init_early(void);
|
||||
void mxc_init_irq(void __iomem *);
|
||||
void tzic_init_irq(void __iomem *);
|
||||
void tzic_init_irq(void);
|
||||
void mx1_init_irq(void);
|
||||
void mx21_init_irq(void);
|
||||
void mx25_init_irq(void);
|
||||
void mx27_init_irq(void);
|
||||
void mx31_init_irq(void);
|
||||
void mx35_init_irq(void);
|
||||
void mx51_init_irq(void);
|
||||
void mx53_init_irq(void);
|
||||
void imx1_soc_init(void);
|
||||
void imx21_soc_init(void);
|
||||
void imx25_soc_init(void);
|
||||
void imx27_soc_init(void);
|
||||
void imx31_soc_init(void);
|
||||
void imx35_soc_init(void);
|
||||
void imx51_soc_init(void);
|
||||
void imx51_init_late(void);
|
||||
void imx53_init_late(void);
|
||||
void epit_timer_init(void __iomem *base, int irq);
|
||||
void mxc_timer_init(void __iomem *, int);
|
||||
void mxc_timer_init_dt(struct device_node *);
|
||||
int mx1_clocks_init(unsigned long fref);
|
||||
int mx21_clocks_init(unsigned long lref, unsigned long fref);
|
||||
int mx25_clocks_init(void);
|
||||
int mx27_clocks_init(unsigned long fref);
|
||||
int mx31_clocks_init(unsigned long fref);
|
||||
int mx35_clocks_init(void);
|
||||
int mx51_clocks_init(unsigned long ckil, unsigned long osc,
|
||||
unsigned long ckih1, unsigned long ckih2);
|
||||
int mx25_clocks_init_dt(void);
|
||||
int mx27_clocks_init_dt(void);
|
||||
int mx31_clocks_init_dt(void);
|
||||
struct platform_device *mxc_register_gpio(char *name, int id,
|
||||
resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
|
||||
@ -75,8 +62,10 @@ void mxc_set_cpu_type(unsigned int type);
|
||||
void mxc_restart(enum reboot_mode, const char *);
|
||||
void mxc_arch_reset_init(void __iomem *);
|
||||
void mxc_arch_reset_init_dt(void);
|
||||
int mx51_revision(void);
|
||||
int mx53_revision(void);
|
||||
void imx_set_aips(void __iomem *);
|
||||
void imx_aips_allow_unprivileged_access(const char *compat);
|
||||
int mxc_device_init(void);
|
||||
void imx_set_soc_revision(unsigned int rev);
|
||||
unsigned int imx_get_soc_revision(void);
|
||||
@ -117,7 +106,7 @@ static inline void imx_scu_standby_enable(void) {}
|
||||
#endif
|
||||
void imx_src_init(void);
|
||||
void imx_gpc_init(void);
|
||||
void imx_gpc_pre_suspend(void);
|
||||
void imx_gpc_pre_suspend(bool arm_power_off);
|
||||
void imx_gpc_post_resume(void);
|
||||
void imx_gpc_mask_all(void);
|
||||
void imx_gpc_restore_all(void);
|
||||
@ -127,7 +116,7 @@ void imx_anatop_init(void);
|
||||
void imx_anatop_pre_suspend(void);
|
||||
void imx_anatop_post_resume(void);
|
||||
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
|
||||
void imx6q_set_int_mem_clk_lpm(void);
|
||||
void imx6q_set_int_mem_clk_lpm(bool enable);
|
||||
void imx6sl_set_wait_clk(bool enter);
|
||||
|
||||
void imx_cpu_die(unsigned int cpu);
|
||||
@ -144,12 +133,17 @@ static inline void imx6_suspend(void __iomem *ocram_vbase) {}
|
||||
void imx6q_pm_init(void);
|
||||
void imx6dl_pm_init(void);
|
||||
void imx6sl_pm_init(void);
|
||||
void imx6sx_pm_init(void);
|
||||
void imx6q_pm_set_ccm_base(void __iomem *base);
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
void imx5_pm_init(void);
|
||||
void imx51_pm_init(void);
|
||||
void imx53_pm_init(void);
|
||||
void imx5_pm_set_ccm_base(void __iomem *base);
|
||||
#else
|
||||
static inline void imx5_pm_init(void) {}
|
||||
static inline void imx51_pm_init(void) {}
|
||||
static inline void imx53_pm_init(void) {}
|
||||
static inline void imx5_pm_set_ccm_base(void __iomem *base) {}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NEON
|
||||
|
||||
@ -16,6 +16,8 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include "hardware.h"
|
||||
#include "common.h"
|
||||
@ -24,10 +26,26 @@ static int mx5_cpu_rev = -1;
|
||||
|
||||
#define IIM_SREV 0x24
|
||||
|
||||
static u32 imx5_read_srev_reg(const char *compat)
|
||||
{
|
||||
void __iomem *iim_base;
|
||||
struct device_node *np;
|
||||
u32 srev;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, compat);
|
||||
iim_base = of_iomap(np, 0);
|
||||
WARN_ON(!iim_base);
|
||||
|
||||
srev = readl(iim_base + IIM_SREV) & 0xff;
|
||||
|
||||
iounmap(iim_base);
|
||||
|
||||
return srev;
|
||||
}
|
||||
|
||||
static int get_mx51_srev(void)
|
||||
{
|
||||
void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
|
||||
u32 rev = readl(iim_base + IIM_SREV) & 0xff;
|
||||
u32 rev = imx5_read_srev_reg("fsl,imx51-iim");
|
||||
|
||||
switch (rev) {
|
||||
case 0x0:
|
||||
@ -77,8 +95,7 @@ int __init mx51_neon_fixup(void)
|
||||
|
||||
static int get_mx53_srev(void)
|
||||
{
|
||||
void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
|
||||
u32 rev = readl(iim_base + IIM_SREV) & 0xff;
|
||||
u32 rev = imx5_read_srev_reg("fsl,imx53-iim");
|
||||
|
||||
switch (rev) {
|
||||
case 0x0:
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/sys_soc.h>
|
||||
|
||||
@ -60,6 +61,18 @@ void __init imx_set_aips(void __iomem *base)
|
||||
__raw_writel(reg, base + 0x50);
|
||||
}
|
||||
|
||||
void __init imx_aips_allow_unprivileged_access(
|
||||
const char *compat)
|
||||
{
|
||||
void __iomem *aips_base_addr;
|
||||
struct device_node *np;
|
||||
|
||||
for_each_compatible_node(np, NULL, compat) {
|
||||
aips_base_addr = of_iomap(np, 0);
|
||||
imx_set_aips(aips_base_addr);
|
||||
}
|
||||
}
|
||||
|
||||
struct device * __init imx_soc_device_init(void)
|
||||
{
|
||||
struct soc_device_attribute *soc_dev_attr;
|
||||
|
||||
@ -13,6 +13,7 @@
|
||||
|
||||
#include "common.h"
|
||||
#include "cpuidle.h"
|
||||
#include "hardware.h"
|
||||
|
||||
static atomic_t master = ATOMIC_INIT(0);
|
||||
static DEFINE_SPINLOCK(master_lock);
|
||||
@ -66,10 +67,11 @@ static struct cpuidle_driver imx6q_cpuidle_driver = {
|
||||
int __init imx6q_cpuidle_init(void)
|
||||
{
|
||||
/* Need to enable SCU standby for entering WAIT modes */
|
||||
imx_scu_standby_enable();
|
||||
if (!cpu_is_imx6sx())
|
||||
imx_scu_standby_enable();
|
||||
|
||||
/* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
|
||||
imx6q_set_int_mem_clk_lpm();
|
||||
imx6q_set_int_mem_clk_lpm(true);
|
||||
|
||||
return cpuidle_register(&imx6q_cpuidle_driver, NULL);
|
||||
}
|
||||
|
||||
@ -1,600 +0,0 @@
|
||||
/*
|
||||
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
|
||||
#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
|
||||
|
||||
#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR)
|
||||
#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR)
|
||||
#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR)
|
||||
#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR)
|
||||
#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
|
||||
#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
|
||||
|
||||
/*MX53*/
|
||||
#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
|
||||
#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
|
||||
#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
|
||||
#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
|
||||
#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR)
|
||||
|
||||
/* PLL Register Offsets */
|
||||
#define MXC_PLL_DP_CTL 0x00
|
||||
#define MXC_PLL_DP_CONFIG 0x04
|
||||
#define MXC_PLL_DP_OP 0x08
|
||||
#define MXC_PLL_DP_MFD 0x0C
|
||||
#define MXC_PLL_DP_MFN 0x10
|
||||
#define MXC_PLL_DP_MFNMINUS 0x14
|
||||
#define MXC_PLL_DP_MFNPLUS 0x18
|
||||
#define MXC_PLL_DP_HFS_OP 0x1C
|
||||
#define MXC_PLL_DP_HFS_MFD 0x20
|
||||
#define MXC_PLL_DP_HFS_MFN 0x24
|
||||
#define MXC_PLL_DP_MFN_TOGC 0x28
|
||||
#define MXC_PLL_DP_DESTAT 0x2c
|
||||
|
||||
/* PLL Register Bit definitions */
|
||||
#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
|
||||
#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
|
||||
#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
|
||||
#define MXC_PLL_DP_CTL_ADE 0x800
|
||||
#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
|
||||
#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
|
||||
#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
|
||||
#define MXC_PLL_DP_CTL_HFSM 0x80
|
||||
#define MXC_PLL_DP_CTL_PRE 0x40
|
||||
#define MXC_PLL_DP_CTL_UPEN 0x20
|
||||
#define MXC_PLL_DP_CTL_RST 0x10
|
||||
#define MXC_PLL_DP_CTL_RCP 0x8
|
||||
#define MXC_PLL_DP_CTL_PLM 0x4
|
||||
#define MXC_PLL_DP_CTL_BRM0 0x2
|
||||
#define MXC_PLL_DP_CTL_LRF 0x1
|
||||
|
||||
#define MXC_PLL_DP_CONFIG_BIST 0x8
|
||||
#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
|
||||
#define MXC_PLL_DP_CONFIG_AREN 0x2
|
||||
#define MXC_PLL_DP_CONFIG_LDREQ 0x1
|
||||
|
||||
#define MXC_PLL_DP_OP_MFI_OFFSET 4
|
||||
#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
|
||||
#define MXC_PLL_DP_OP_PDF_OFFSET 0
|
||||
#define MXC_PLL_DP_OP_PDF_MASK 0xF
|
||||
|
||||
#define MXC_PLL_DP_MFD_OFFSET 0
|
||||
#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
|
||||
|
||||
#define MXC_PLL_DP_MFN_OFFSET 0x0
|
||||
#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
|
||||
|
||||
#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
|
||||
#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
|
||||
#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
|
||||
#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
|
||||
|
||||
#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
|
||||
#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
|
||||
|
||||
/* Register addresses of CCM*/
|
||||
#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00)
|
||||
#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04)
|
||||
#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08)
|
||||
#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C)
|
||||
#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10)
|
||||
#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14)
|
||||
#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18)
|
||||
#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C)
|
||||
#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20)
|
||||
#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24)
|
||||
#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28)
|
||||
#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C)
|
||||
#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30)
|
||||
#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34)
|
||||
#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38)
|
||||
#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C)
|
||||
#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40)
|
||||
#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44)
|
||||
#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48)
|
||||
#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C)
|
||||
#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50)
|
||||
#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54)
|
||||
#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58)
|
||||
#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C)
|
||||
#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60)
|
||||
#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64)
|
||||
#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68)
|
||||
#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C)
|
||||
#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70)
|
||||
#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74)
|
||||
#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78)
|
||||
#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C)
|
||||
#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80)
|
||||
#define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84)
|
||||
|
||||
#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84)
|
||||
|
||||
/* Define the bits in register CCR */
|
||||
#define MXC_CCM_CCR_COSC_EN (1 << 12)
|
||||
#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
|
||||
#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
|
||||
#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
|
||||
#define MXC_CCM_CCR_FPM_EN (1 << 8)
|
||||
#define MXC_CCM_CCR_OSCNT_OFFSET (0)
|
||||
#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
|
||||
|
||||
/* Define the bits in register CCDR */
|
||||
#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
|
||||
#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
|
||||
#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
|
||||
|
||||
/* Define the bits in register CSR */
|
||||
#define MXC_CCM_CSR_COSR_READY (1 << 5)
|
||||
#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
|
||||
#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
|
||||
#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
|
||||
#define MXC_CCM_CSR_FPM_READY (1 << 1)
|
||||
#define MXC_CCM_CSR_REF_EN_B (1 << 0)
|
||||
|
||||
/* Define the bits in register CCSR */
|
||||
#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
|
||||
#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
|
||||
#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
|
||||
#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0
|
||||
#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */
|
||||
#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2
|
||||
#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3
|
||||
#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
|
||||
#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
|
||||
#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
|
||||
#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
|
||||
#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk,
|
||||
1: step_clk */
|
||||
#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
|
||||
#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
|
||||
|
||||
/* Define the bits in register CACRR */
|
||||
#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
|
||||
|
||||
/* Define the bits in register CBCDR */
|
||||
#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
|
||||
#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
|
||||
#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
|
||||
#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
|
||||
#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27)
|
||||
#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
|
||||
#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
|
||||
#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
|
||||
#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
|
||||
#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
|
||||
#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
|
||||
#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
|
||||
#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
|
||||
#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
|
||||
#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
|
||||
#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
|
||||
#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
|
||||
#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
|
||||
|
||||
/* Define the bits in register CBCMR */
|
||||
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
|
||||
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
|
||||
#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
|
||||
#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
|
||||
#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
|
||||
#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
|
||||
#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
|
||||
#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14)
|
||||
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
|
||||
#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
|
||||
|
||||
/* Define the bits in register CSCMR1 */
|
||||
#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
|
||||
#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
|
||||
#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
|
||||
#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
|
||||
#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
|
||||
#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
|
||||
#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
|
||||
#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
|
||||
#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
|
||||
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_MX53_CLK_SEL (0x1 << 19)
|
||||
#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
|
||||
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
|
||||
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_OFFSET (16)
|
||||
#define MXC_CCM_CSCMR1_ESDHC3_MX53_CLK_SEL_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
|
||||
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
|
||||
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
|
||||
#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
|
||||
#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
|
||||
#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
|
||||
#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
|
||||
#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
|
||||
#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
|
||||
#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
|
||||
#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
|
||||
#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
|
||||
|
||||
/* Define the bits in register CSCMR2 */
|
||||
#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
|
||||
#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
|
||||
#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
|
||||
#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
|
||||
#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
|
||||
#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
|
||||
#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
|
||||
#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
|
||||
#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
|
||||
#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
|
||||
#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
|
||||
#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
|
||||
#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
|
||||
#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
|
||||
#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
|
||||
#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
|
||||
#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
|
||||
#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
|
||||
#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
|
||||
|
||||
/* Define the bits in register CSCDR1 */
|
||||
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
|
||||
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
|
||||
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
|
||||
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_OFFSET (22)
|
||||
#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PRED_MASK (0x7 << 22)
|
||||
#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_OFFSET (19)
|
||||
#define MXC_CCM_CSCDR1_ESDHC3_MX53_CLK_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
|
||||
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
|
||||
#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
|
||||
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
|
||||
|
||||
/* Define the bits in register CS1CDR and CS2CDR */
|
||||
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
|
||||
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
|
||||
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
|
||||
#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
|
||||
|
||||
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
|
||||
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
|
||||
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
|
||||
#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
|
||||
|
||||
/* Define the bits in register CDCDR */
|
||||
#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
|
||||
#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
|
||||
#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
|
||||
#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
|
||||
#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
|
||||
|
||||
/* Define the bits in register CHSCCDR */
|
||||
#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
|
||||
#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
|
||||
#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
|
||||
#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
|
||||
#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
|
||||
|
||||
/* Define the bits in register CSCDR2 */
|
||||
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
|
||||
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
|
||||
#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
|
||||
#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
|
||||
#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
|
||||
#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
|
||||
#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
|
||||
#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
|
||||
#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
|
||||
|
||||
/* Define the bits in register CSCDR3 */
|
||||
#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
|
||||
#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
|
||||
#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
|
||||
#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
|
||||
#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
|
||||
|
||||
/* Define the bits in register CSCDR4 */
|
||||
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
|
||||
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
|
||||
#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
|
||||
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
|
||||
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
|
||||
|
||||
/* Define the bits in register CDHIPR */
|
||||
#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
|
||||
#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
|
||||
#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
|
||||
#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
|
||||
#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
|
||||
#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
|
||||
#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
|
||||
#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
|
||||
#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
|
||||
#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
|
||||
|
||||
/* Define the bits in register CDCR */
|
||||
#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
|
||||
#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
|
||||
#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
|
||||
|
||||
/* Define the bits in register CLPCR */
|
||||
#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
|
||||
#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
|
||||
#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
|
||||
#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
|
||||
#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
|
||||
#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
|
||||
#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
|
||||
#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
|
||||
#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
|
||||
#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
|
||||
#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
|
||||
#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
|
||||
#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
|
||||
#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
|
||||
#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
|
||||
#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
|
||||
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
|
||||
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
|
||||
#define MXC_CCM_CLPCR_LPM_OFFSET (0)
|
||||
#define MXC_CCM_CLPCR_LPM_MASK (0x3)
|
||||
|
||||
/* Define the bits in register CISR */
|
||||
#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
|
||||
#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
|
||||
#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
|
||||
#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
|
||||
#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
|
||||
#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
|
||||
#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
|
||||
#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
|
||||
#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
|
||||
#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
|
||||
#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
|
||||
#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
|
||||
#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
|
||||
#define MXC_CCM_CISR_LRF_PLL1 (0x1)
|
||||
|
||||
/* Define the bits in register CIMR */
|
||||
#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
|
||||
#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
|
||||
#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
|
||||
#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
|
||||
#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
|
||||
#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
|
||||
#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
|
||||
#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
|
||||
#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
|
||||
#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
|
||||
#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
|
||||
#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
|
||||
#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
|
||||
|
||||
/* Define the bits in register CCOSR */
|
||||
#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
|
||||
#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
|
||||
#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
|
||||
#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
|
||||
#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
|
||||
#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
|
||||
#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
|
||||
#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
|
||||
#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
|
||||
#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
|
||||
|
||||
/* Define the bits in registers CGPR */
|
||||
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
|
||||
#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
|
||||
#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
|
||||
#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
|
||||
|
||||
/* Define the bits in registers CCGRx */
|
||||
#define MXC_CCM_CCGRx_CG_MASK 0x3
|
||||
#define MXC_CCM_CCGRx_MOD_OFF 0x0
|
||||
#define MXC_CCM_CCGRx_MOD_ON 0x3
|
||||
#define MXC_CCM_CCGRx_MOD_IDLE 0x1
|
||||
|
||||
#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30)
|
||||
#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10)
|
||||
#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2)
|
||||
#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0)
|
||||
|
||||
#define MXC_CCM_CCGRx_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGRx_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGRx_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGRx_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGRx_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGRx_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGRx_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGRx_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGRx_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGRx_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGRx_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGRx_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGRx_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGRx_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGRx_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGRx_CG0_OFFSET 0
|
||||
|
||||
#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80)
|
||||
#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100)
|
||||
#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180)
|
||||
#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0)
|
||||
#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
|
||||
#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
|
||||
#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
|
||||
#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280)
|
||||
#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0)
|
||||
#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0)
|
||||
#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0)
|
||||
#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0)
|
||||
#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300)
|
||||
|
||||
/* CORTEXA8 platform */
|
||||
#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0)
|
||||
#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4)
|
||||
#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8)
|
||||
#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC)
|
||||
#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10)
|
||||
#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14)
|
||||
#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18)
|
||||
#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20)
|
||||
#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24)
|
||||
|
||||
/* DVFS CORE */
|
||||
#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
|
||||
#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
|
||||
#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
|
||||
#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
|
||||
#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
|
||||
#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
|
||||
#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
|
||||
#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
|
||||
#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
|
||||
#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
|
||||
#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
|
||||
#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
|
||||
#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
|
||||
#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
|
||||
#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
|
||||
#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
|
||||
#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
|
||||
|
||||
/* GPC */
|
||||
#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0)
|
||||
#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4)
|
||||
#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8)
|
||||
#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
|
||||
#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10)
|
||||
#define MXC_GPC_PGR_ARMPG_OFFSET 8
|
||||
#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
|
||||
|
||||
/* PGC */
|
||||
#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
|
||||
#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
|
||||
#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
|
||||
#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
|
||||
#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
|
||||
#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
|
||||
|
||||
#define MXC_PGCR_PCR 1
|
||||
#define MXC_SRPGCR_PCR 1
|
||||
#define MXC_EMPGCR_PCR 1
|
||||
#define MXC_PGSR_PSR 1
|
||||
|
||||
|
||||
#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
|
||||
#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
|
||||
|
||||
/* SRPG */
|
||||
#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
|
||||
#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
|
||||
#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
|
||||
|
||||
#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
|
||||
#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
|
||||
#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
|
||||
|
||||
#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
|
||||
#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
|
||||
#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
|
||||
|
||||
#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
|
||||
#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
|
||||
#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
|
||||
|
||||
#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
|
||||
#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
|
||||
#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
|
||||
|
||||
#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
|
||||
#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
|
||||
#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
|
||||
|
||||
#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
|
||||
@ -1,66 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Pengutronix
|
||||
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it under
|
||||
* the terms of the GNU General Public License version 2 as published by the
|
||||
* Free Software Foundation.
|
||||
*/
|
||||
#include "devices/devices-common.h"
|
||||
|
||||
extern const struct imx_fec_data imx51_fec_data;
|
||||
#define imx51_add_fec(pdata) \
|
||||
imx_add_fec(&imx51_fec_data, pdata)
|
||||
|
||||
extern const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data;
|
||||
#define imx51_add_fsl_usb2_udc(pdata) \
|
||||
imx_add_fsl_usb2_udc(&imx51_fsl_usb2_udc_data, pdata)
|
||||
|
||||
extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
|
||||
#define imx51_add_imx_i2c(id, pdata) \
|
||||
imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
|
||||
#define imx51_add_hsi2c(pdata) \
|
||||
imx51_add_imx_i2c(2, pdata)
|
||||
|
||||
extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
|
||||
#define imx51_add_imx_ssi(id, pdata) \
|
||||
imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
|
||||
|
||||
extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
|
||||
#define imx51_add_imx_uart(id, pdata) \
|
||||
imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
|
||||
|
||||
extern const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data;
|
||||
#define imx51_add_mxc_ehci_otg(pdata) \
|
||||
imx_add_mxc_ehci(&imx51_mxc_ehci_otg_data, pdata)
|
||||
extern const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[];
|
||||
#define imx51_add_mxc_ehci_hs(id, pdata) \
|
||||
imx_add_mxc_ehci(&imx51_mxc_ehci_hs_data[id - 1], pdata)
|
||||
|
||||
extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
|
||||
#define imx51_add_mxc_nand(pdata) \
|
||||
imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
|
||||
|
||||
extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[];
|
||||
#define imx51_add_sdhci_esdhc_imx(id, pdata) \
|
||||
imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
|
||||
|
||||
extern const struct imx_spi_imx_data imx51_cspi_data;
|
||||
#define imx51_add_cspi(pdata) \
|
||||
imx_add_spi_imx(&imx51_cspi_data, pdata)
|
||||
|
||||
extern const struct imx_spi_imx_data imx51_ecspi_data[];
|
||||
#define imx51_add_ecspi(id, pdata) \
|
||||
imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
|
||||
|
||||
extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
|
||||
#define imx51_add_imx2_wdt(id) \
|
||||
imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
|
||||
|
||||
extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
|
||||
#define imx51_add_imx_keypad(pdata) \
|
||||
imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
|
||||
|
||||
extern const struct imx_pata_imx_data imx51_pata_imx_data;
|
||||
#define imx51_add_pata_imx() \
|
||||
imx_add_pata_imx(&imx51_pata_imx_data)
|
||||
@ -1,6 +1,6 @@
|
||||
config IMX_HAVE_PLATFORM_FEC
|
||||
bool
|
||||
default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53
|
||||
default y if SOC_IMX25 || SOC_IMX27 || SOC_IMX35
|
||||
|
||||
config IMX_HAVE_PLATFORM_FLEXCAN
|
||||
bool
|
||||
@ -10,7 +10,6 @@ config IMX_HAVE_PLATFORM_FSL_USB2_UDC
|
||||
|
||||
config IMX_HAVE_PLATFORM_GPIO_KEYS
|
||||
bool
|
||||
default y if SOC_IMX51
|
||||
|
||||
config IMX_HAVE_PLATFORM_IMX21_HCD
|
||||
bool
|
||||
@ -43,15 +42,9 @@ config IMX_HAVE_PLATFORM_IMX_SSI
|
||||
config IMX_HAVE_PLATFORM_IMX_UART
|
||||
bool
|
||||
|
||||
config IMX_HAVE_PLATFORM_IMX_UDC
|
||||
bool
|
||||
|
||||
config IMX_HAVE_PLATFORM_IPU_CORE
|
||||
bool
|
||||
|
||||
config IMX_HAVE_PLATFORM_MX1_CAMERA
|
||||
bool
|
||||
|
||||
config IMX_HAVE_PLATFORM_MX2_CAMERA
|
||||
bool
|
||||
|
||||
|
||||
@ -16,9 +16,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_PATA_IMX) += platform-pata_imx.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
|
||||
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
|
||||
|
||||
@ -176,22 +176,6 @@ struct platform_device *__init imx_add_imx_uart_1irq(
|
||||
const struct imx_imx_uart_1irq_data *data,
|
||||
const struct imxuart_platform_data *pdata);
|
||||
|
||||
#include <linux/platform_data/usb-imx_udc.h>
|
||||
struct imx_imx_udc_data {
|
||||
resource_size_t iobase;
|
||||
resource_size_t iosize;
|
||||
resource_size_t irq0;
|
||||
resource_size_t irq1;
|
||||
resource_size_t irq2;
|
||||
resource_size_t irq3;
|
||||
resource_size_t irq4;
|
||||
resource_size_t irq5;
|
||||
resource_size_t irq6;
|
||||
};
|
||||
struct platform_device *__init imx_add_imx_udc(
|
||||
const struct imx_imx_udc_data *data,
|
||||
const struct imxusb_platform_data *pdata);
|
||||
|
||||
#include <linux/platform_data/video-mx3fb.h>
|
||||
#include <linux/platform_data/camera-mx3.h>
|
||||
struct imx_ipu_core_data {
|
||||
@ -208,16 +192,6 @@ struct platform_device *__init imx_add_mx3_sdc_fb(
|
||||
const struct imx_ipu_core_data *data,
|
||||
struct mx3fb_platform_data *pdata);
|
||||
|
||||
#include <linux/platform_data/camera-mx1.h>
|
||||
struct imx_mx1_camera_data {
|
||||
resource_size_t iobase;
|
||||
resource_size_t iosize;
|
||||
resource_size_t irq;
|
||||
};
|
||||
struct platform_device *__init imx_add_mx1_camera(
|
||||
const struct imx_mx1_camera_data *data,
|
||||
const struct mx1_camera_pdata *pdata);
|
||||
|
||||
#include <linux/platform_data/camera-mx2.h>
|
||||
struct imx_mx2_camera_data {
|
||||
const char *devid;
|
||||
|
||||
@ -35,18 +35,6 @@ const struct imx_fec_data imx35_fec_data __initconst =
|
||||
imx_fec_data_entry_single(MX35, "imx27-fec");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
/* i.mx51 has the i.mx27 type fec */
|
||||
const struct imx_fec_data imx51_fec_data __initconst =
|
||||
imx_fec_data_entry_single(MX51, "imx27-fec");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX53
|
||||
/* i.mx53 has the i.mx25 type fec */
|
||||
const struct imx_fec_data imx53_fec_data __initconst =
|
||||
imx_fec_data_entry_single(MX53, "imx25-fec");
|
||||
#endif
|
||||
|
||||
struct platform_device *__init imx_add_fec(
|
||||
const struct imx_fec_data *data,
|
||||
const struct fec_platform_data *pdata)
|
||||
|
||||
@ -38,11 +38,6 @@ const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst =
|
||||
imx_fsl_usb2_udc_data_entry_single(MX35, "imx-udc-mx27");
|
||||
#endif /* ifdef CONFIG_SOC_IMX35 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
const struct imx_fsl_usb2_udc_data imx51_fsl_usb2_udc_data __initconst =
|
||||
imx_fsl_usb2_udc_data_entry_single(MX51, "imx-udc-mx51");
|
||||
#endif
|
||||
|
||||
struct platform_device *__init imx_add_fsl_usb2_udc(
|
||||
const struct imx_fsl_usb2_udc_data *data,
|
||||
const struct fsl_usb2_platform_data *pdata)
|
||||
|
||||
@ -70,32 +70,6 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX35 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
|
||||
#define imx51_imx_i2c_data_entry(_id, _hwid) \
|
||||
imx_imx_i2c_data_entry(MX51, "imx21-i2c", _id, _hwid, SZ_4K)
|
||||
imx51_imx_i2c_data_entry(0, 1),
|
||||
imx51_imx_i2c_data_entry(1, 2),
|
||||
{
|
||||
.devid = "imx21-i2c",
|
||||
.id = 2,
|
||||
.iobase = MX51_HSI2C_DMA_BASE_ADDR,
|
||||
.iosize = SZ_16K,
|
||||
.irq = MX51_INT_HS_I2C,
|
||||
},
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX51 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX53
|
||||
const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst = {
|
||||
#define imx53_imx_i2c_data_entry(_id, _hwid) \
|
||||
imx_imx_i2c_data_entry(MX53, "imx21-i2c", _id, _hwid, SZ_4K)
|
||||
imx53_imx_i2c_data_entry(0, 1),
|
||||
imx53_imx_i2c_data_entry(1, 2),
|
||||
imx53_imx_i2c_data_entry(2, 3),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX53 */
|
||||
|
||||
struct platform_device *__init imx_add_imx_i2c(
|
||||
const struct imx_imx_i2c_data *data,
|
||||
const struct imxi2c_platform_data *pdata)
|
||||
|
||||
@ -41,16 +41,6 @@ const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst =
|
||||
imx_imx_keypad_data_entry_single(MX35, SZ_16);
|
||||
#endif /* ifdef CONFIG_SOC_IMX35 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst =
|
||||
imx_imx_keypad_data_entry_single(MX51, SZ_16);
|
||||
#endif /* ifdef CONFIG_SOC_IMX51 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX53
|
||||
const struct imx_imx_keypad_data imx53_imx_keypad_data __initconst =
|
||||
imx_imx_keypad_data_entry_single(MX53, SZ_16);
|
||||
#endif /* ifdef CONFIG_SOC_IMX53 */
|
||||
|
||||
struct platform_device *__init imx_add_imx_keypad(
|
||||
const struct imx_imx_keypad_data *data,
|
||||
const struct matrix_keymap_data *pdata)
|
||||
|
||||
@ -66,26 +66,6 @@ const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = {
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX35 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = {
|
||||
#define imx51_imx_ssi_data_entry(_id, _hwid) \
|
||||
imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_16K)
|
||||
imx51_imx_ssi_data_entry(0, 1),
|
||||
imx51_imx_ssi_data_entry(1, 2),
|
||||
imx51_imx_ssi_data_entry(2, 3),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX51 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX53
|
||||
const struct imx_imx_ssi_data imx53_imx_ssi_data[] __initconst = {
|
||||
#define imx53_imx_ssi_data_entry(_id, _hwid) \
|
||||
imx_imx_ssi_data_entry(MX53, _id, _hwid, SZ_16K)
|
||||
imx53_imx_ssi_data_entry(0, 1),
|
||||
imx53_imx_ssi_data_entry(1, 2),
|
||||
imx53_imx_ssi_data_entry(2, 3),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX53 */
|
||||
|
||||
struct platform_device *__init imx_add_imx_ssi(
|
||||
const struct imx_imx_ssi_data *data,
|
||||
const struct imx_ssi_platform_data *pdata)
|
||||
|
||||
@ -94,28 +94,6 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX35 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
|
||||
#define imx51_imx_uart_data_entry(_id, _hwid) \
|
||||
imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K)
|
||||
imx51_imx_uart_data_entry(0, 1),
|
||||
imx51_imx_uart_data_entry(1, 2),
|
||||
imx51_imx_uart_data_entry(2, 3),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX51 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX53
|
||||
const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = {
|
||||
#define imx53_imx_uart_data_entry(_id, _hwid) \
|
||||
imx_imx_uart_1irq_data_entry(MX53, _id, _hwid, SZ_4K)
|
||||
imx53_imx_uart_data_entry(0, 1),
|
||||
imx53_imx_uart_data_entry(1, 2),
|
||||
imx53_imx_uart_data_entry(2, 3),
|
||||
imx53_imx_uart_data_entry(3, 4),
|
||||
imx53_imx_uart_data_entry(4, 5),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX53 */
|
||||
|
||||
struct platform_device *__init imx_add_imx_uart_3irq(
|
||||
const struct imx_imx_uart_3irq_data *data,
|
||||
const struct imxuart_platform_data *pdata)
|
||||
|
||||
@ -45,24 +45,6 @@ const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst =
|
||||
imx_imx2_wdt_data_entry_single(MX35, 0, , SZ_16K);
|
||||
#endif /* ifdef CONFIG_SOC_IMX35 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = {
|
||||
#define imx51_imx2_wdt_data_entry(_id, _hwid) \
|
||||
imx_imx2_wdt_data_entry(MX51, _id, _hwid, SZ_16K)
|
||||
imx51_imx2_wdt_data_entry(0, 1),
|
||||
imx51_imx2_wdt_data_entry(1, 2),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX51 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX53
|
||||
const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst = {
|
||||
#define imx53_imx2_wdt_data_entry(_id, _hwid) \
|
||||
imx_imx2_wdt_data_entry(MX53, _id, _hwid, SZ_16K)
|
||||
imx53_imx2_wdt_data_entry(0, 1),
|
||||
imx53_imx2_wdt_data_entry(1, 2),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX53 */
|
||||
|
||||
struct platform_device *__init imx_add_imx2_wdt(
|
||||
const struct imx_imx2_wdt_data *data)
|
||||
{
|
||||
|
||||
@ -1,75 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Pengutronix
|
||||
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it under
|
||||
* the terms of the GNU General Public License version 2 as published by the
|
||||
* Free Software Foundation.
|
||||
*/
|
||||
#include "../hardware.h"
|
||||
#include "devices-common.h"
|
||||
|
||||
#define imx_imx_udc_data_entry_single(soc, _size) \
|
||||
{ \
|
||||
.iobase = soc ## _USBD_BASE_ADDR, \
|
||||
.iosize = _size, \
|
||||
.irq0 = soc ## _INT_USBD0, \
|
||||
.irq1 = soc ## _INT_USBD1, \
|
||||
.irq2 = soc ## _INT_USBD2, \
|
||||
.irq3 = soc ## _INT_USBD3, \
|
||||
.irq4 = soc ## _INT_USBD4, \
|
||||
.irq5 = soc ## _INT_USBD5, \
|
||||
.irq6 = soc ## _INT_USBD6, \
|
||||
}
|
||||
|
||||
#define imx_imx_udc_data_entry(soc, _size) \
|
||||
[_id] = imx_imx_udc_data_entry_single(soc, _size)
|
||||
|
||||
#ifdef CONFIG_SOC_IMX1
|
||||
const struct imx_imx_udc_data imx1_imx_udc_data __initconst =
|
||||
imx_imx_udc_data_entry_single(MX1, SZ_4K);
|
||||
#endif /* ifdef CONFIG_SOC_IMX1 */
|
||||
|
||||
struct platform_device *__init imx_add_imx_udc(
|
||||
const struct imx_imx_udc_data *data,
|
||||
const struct imxusb_platform_data *pdata)
|
||||
{
|
||||
struct resource res[] = {
|
||||
{
|
||||
.start = data->iobase,
|
||||
.end = data->iobase + data->iosize - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = data->irq0,
|
||||
.end = data->irq0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}, {
|
||||
.start = data->irq1,
|
||||
.end = data->irq1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}, {
|
||||
.start = data->irq2,
|
||||
.end = data->irq2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}, {
|
||||
.start = data->irq3,
|
||||
.end = data->irq3,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}, {
|
||||
.start = data->irq4,
|
||||
.end = data->irq4,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}, {
|
||||
.start = data->irq5,
|
||||
.end = data->irq5,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}, {
|
||||
.start = data->irq6,
|
||||
.end = data->irq6,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
return imx_add_platform_device("imx_udc", 0,
|
||||
res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
|
||||
}
|
||||
@ -1,42 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Pengutronix
|
||||
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it under
|
||||
* the terms of the GNU General Public License version 2 as published by the
|
||||
* Free Software Foundation.
|
||||
*/
|
||||
#include "../hardware.h"
|
||||
#include "devices-common.h"
|
||||
|
||||
#define imx_mx1_camera_data_entry_single(soc, _size) \
|
||||
{ \
|
||||
.iobase = soc ## _CSI ## _BASE_ADDR, \
|
||||
.iosize = _size, \
|
||||
.irq = soc ## _INT_CSI, \
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOC_IMX1
|
||||
const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst =
|
||||
imx_mx1_camera_data_entry_single(MX1, 10);
|
||||
#endif /* ifdef CONFIG_SOC_IMX1 */
|
||||
|
||||
struct platform_device *__init imx_add_mx1_camera(
|
||||
const struct imx_mx1_camera_data *data,
|
||||
const struct mx1_camera_pdata *pdata)
|
||||
{
|
||||
struct resource res[] = {
|
||||
{
|
||||
.start = data->iobase,
|
||||
.end = data->iobase + data->iosize - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = data->irq,
|
||||
.end = data->irq,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
return imx_add_platform_device_dmamask("mx1-camera", 0,
|
||||
res, ARRAY_SIZE(res),
|
||||
pdata, sizeof(*pdata), DMA_BIT_MASK(32));
|
||||
}
|
||||
@ -50,15 +50,6 @@ const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst =
|
||||
imx_mxc_ehci_data_entry_single(MX35, 1, HS);
|
||||
#endif /* ifdef CONFIG_SOC_IMX35 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
const struct imx_mxc_ehci_data imx51_mxc_ehci_otg_data __initconst =
|
||||
imx_mxc_ehci_data_entry_single(MX51, 0, OTG);
|
||||
const struct imx_mxc_ehci_data imx51_mxc_ehci_hs_data[] __initconst = {
|
||||
imx_mxc_ehci_data_entry_single(MX51, 1, HS1),
|
||||
imx_mxc_ehci_data_entry_single(MX51, 2, HS2),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX51 */
|
||||
|
||||
struct platform_device *__init imx_add_mxc_ehci(
|
||||
const struct imx_mxc_ehci_data *data,
|
||||
const struct mxc_usbh_platform_data *pdata)
|
||||
|
||||
@ -54,11 +54,6 @@ const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst =
|
||||
imx_mxc_nand_data_entry_single(MX35, "imx25-nand", SZ_8K);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst =
|
||||
imx_mxc_nandv3_data_entry_single(MX51, "imx51-nand", SZ_16K);
|
||||
#endif
|
||||
|
||||
struct platform_device *__init imx_add_mxc_nand(
|
||||
const struct imx_mxc_nand_data *data,
|
||||
const struct mxc_nand_platform_data *pdata)
|
||||
|
||||
@ -48,9 +48,6 @@ static int __init imxXX_add_mxc_rnga(void)
|
||||
#endif /* if defined(CONFIG_SOC_IMX31) */
|
||||
ret = ERR_PTR(-ENODEV);
|
||||
|
||||
if (IS_ERR(ret))
|
||||
return PTR_ERR(ret);
|
||||
|
||||
return 0;
|
||||
return PTR_ERR_OR_ZERO(ret);
|
||||
}
|
||||
arch_initcall(imxXX_add_mxc_rnga);
|
||||
|
||||
@ -28,16 +28,6 @@ const struct imx_pata_imx_data imx35_pata_imx_data __initconst =
|
||||
imx_pata_imx_data_entry_single(MX35, SZ_16K);
|
||||
#endif /* ifdef CONFIG_SOC_IMX35 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
const struct imx_pata_imx_data imx51_pata_imx_data __initconst =
|
||||
imx_pata_imx_data_entry_single(MX51, SZ_16K);
|
||||
#endif /* ifdef CONFIG_SOC_IMX51 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX53
|
||||
const struct imx_pata_imx_data imx53_pata_imx_data __initconst =
|
||||
imx_pata_imx_data_entry_single(MX53, SZ_16K);
|
||||
#endif /* ifdef CONFIG_SOC_IMX53 */
|
||||
|
||||
struct platform_device *__init imx_add_pata_imx(
|
||||
const struct imx_pata_imx_data *data)
|
||||
{
|
||||
|
||||
@ -43,30 +43,6 @@ imx35_sdhci_esdhc_imx_data[] __initconst = {
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX35 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
const struct imx_sdhci_esdhc_imx_data
|
||||
imx51_sdhci_esdhc_imx_data[] __initconst = {
|
||||
#define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid) \
|
||||
imx_sdhci_esdhc_imx_data_entry(MX51, "sdhci-esdhc-imx51", _id, _hwid)
|
||||
imx51_sdhci_esdhc_imx_data_entry(0, 1),
|
||||
imx51_sdhci_esdhc_imx_data_entry(1, 2),
|
||||
imx51_sdhci_esdhc_imx_data_entry(2, 3),
|
||||
imx51_sdhci_esdhc_imx_data_entry(3, 4),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX51 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX53
|
||||
const struct imx_sdhci_esdhc_imx_data
|
||||
imx53_sdhci_esdhc_imx_data[] __initconst = {
|
||||
#define imx53_sdhci_esdhc_imx_data_entry(_id, _hwid) \
|
||||
imx_sdhci_esdhc_imx_data_entry(MX53, "sdhci-esdhc-imx53", _id, _hwid)
|
||||
imx53_sdhci_esdhc_imx_data_entry(0, 1),
|
||||
imx53_sdhci_esdhc_imx_data_entry(1, 2),
|
||||
imx53_sdhci_esdhc_imx_data_entry(2, 3),
|
||||
imx53_sdhci_esdhc_imx_data_entry(3, 4),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX53 */
|
||||
|
||||
static const struct esdhc_platform_data default_esdhc_pdata __initconst = {
|
||||
.wp_type = ESDHC_WP_NONE,
|
||||
.cd_type = ESDHC_CD_NONE,
|
||||
|
||||
@ -79,33 +79,6 @@ const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX35 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX51
|
||||
/* i.mx51 has the i.mx35 type cspi */
|
||||
const struct imx_spi_imx_data imx51_cspi_data __initconst =
|
||||
imx_spi_imx_data_entry_single(MX51, CSPI, "imx35-cspi", 2, , SZ_4K);
|
||||
|
||||
const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
|
||||
#define imx51_ecspi_data_entry(_id, _hwid) \
|
||||
imx_spi_imx_data_entry(MX51, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K)
|
||||
imx51_ecspi_data_entry(0, 1),
|
||||
imx51_ecspi_data_entry(1, 2),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX51 */
|
||||
|
||||
#ifdef CONFIG_SOC_IMX53
|
||||
/* i.mx53 has the i.mx35 type cspi */
|
||||
const struct imx_spi_imx_data imx53_cspi_data __initconst =
|
||||
imx_spi_imx_data_entry_single(MX53, CSPI, "imx35-cspi", 2, , SZ_4K);
|
||||
|
||||
/* i.mx53 has the i.mx51 type ecspi */
|
||||
const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = {
|
||||
#define imx53_ecspi_data_entry(_id, _hwid) \
|
||||
imx_spi_imx_data_entry(MX53, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K)
|
||||
imx53_ecspi_data_entry(0, 1),
|
||||
imx53_ecspi_data_entry(1, 2),
|
||||
};
|
||||
#endif /* ifdef CONFIG_SOC_IMX53 */
|
||||
|
||||
struct platform_device *__init imx_add_spi_imx(
|
||||
const struct imx_spi_imx_data *data,
|
||||
const struct spi_imx_master *pdata)
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_data/usb-ehci-mxc.h>
|
||||
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
|
||||
#define USBCTRL_OTGBASE_OFFSET 0x600
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_data/usb-ehci-mxc.h>
|
||||
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
|
||||
#define USBCTRL_OTGBASE_OFFSET 0x600
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_data/usb-ehci-mxc.h>
|
||||
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
|
||||
#define USBCTRL_OTGBASE_OFFSET 0x600
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_data/usb-ehci-mxc.h>
|
||||
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
|
||||
#define USBCTRL_OTGBASE_OFFSET 0x600
|
||||
|
||||
@ -1,171 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_data/usb-ehci-mxc.h>
|
||||
|
||||
#include "hardware.h"
|
||||
|
||||
#define MXC_OTG_OFFSET 0
|
||||
#define MXC_H1_OFFSET 0x200
|
||||
#define MXC_H2_OFFSET 0x400
|
||||
|
||||
/* USB_CTRL */
|
||||
#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
|
||||
#define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */
|
||||
#define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */
|
||||
#define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */
|
||||
#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */
|
||||
|
||||
/* USB_PHY_CTRL_FUNC */
|
||||
#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */
|
||||
#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
|
||||
#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */
|
||||
#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
|
||||
#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */
|
||||
|
||||
/* USBH2CTRL */
|
||||
#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
|
||||
#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
|
||||
#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
|
||||
|
||||
#define MXC_USBCMD_OFFSET 0x140
|
||||
|
||||
/* USBCMD */
|
||||
#define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */
|
||||
|
||||
int mx51_initialize_usb_hw(int port, unsigned int flags)
|
||||
{
|
||||
unsigned int v;
|
||||
void __iomem *usb_base;
|
||||
void __iomem *usbotg_base;
|
||||
void __iomem *usbother_base;
|
||||
int ret = 0;
|
||||
|
||||
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
|
||||
if (!usb_base) {
|
||||
printk(KERN_ERR "%s(): ioremap failed\n", __func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
switch (port) {
|
||||
case 0: /* OTG port */
|
||||
usbotg_base = usb_base + MXC_OTG_OFFSET;
|
||||
break;
|
||||
case 1: /* Host 1 port */
|
||||
usbotg_base = usb_base + MXC_H1_OFFSET;
|
||||
break;
|
||||
case 2: /* Host 2 port */
|
||||
usbotg_base = usb_base + MXC_H2_OFFSET;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR"%s no such port %d\n", __func__, port);
|
||||
ret = -ENOENT;
|
||||
goto error;
|
||||
}
|
||||
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
|
||||
|
||||
switch (port) {
|
||||
case 0: /*OTG port */
|
||||
if (flags & MXC_EHCI_INTERNAL_PHY) {
|
||||
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
|
||||
|
||||
if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
|
||||
v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
|
||||
else
|
||||
v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
|
||||
if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
|
||||
/* OC/USBPWR is used */
|
||||
v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
|
||||
} else {
|
||||
/* OC/USBPWR is not used */
|
||||
v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
|
||||
}
|
||||
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
|
||||
v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
|
||||
else
|
||||
v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
|
||||
__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
|
||||
|
||||
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
|
||||
if (flags & MXC_EHCI_WAKEUP_ENABLED)
|
||||
v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
|
||||
else
|
||||
v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
|
||||
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
|
||||
v &= ~MXC_OTG_UCTRL_OPM_BIT;
|
||||
else
|
||||
v |= MXC_OTG_UCTRL_OPM_BIT;
|
||||
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
|
||||
}
|
||||
break;
|
||||
case 1: /* Host 1 */
|
||||
/*Host ULPI */
|
||||
v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
|
||||
if (flags & MXC_EHCI_WAKEUP_ENABLED) {
|
||||
/* HOST1 wakeup/ULPI intr enable */
|
||||
v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
|
||||
} else {
|
||||
/* HOST1 wakeup/ULPI intr disable */
|
||||
v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
|
||||
}
|
||||
|
||||
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
|
||||
v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/
|
||||
else
|
||||
v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
|
||||
__raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
|
||||
|
||||
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
|
||||
if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
|
||||
v |= MXC_H1_OC_POL_BIT;
|
||||
else
|
||||
v &= ~MXC_H1_OC_POL_BIT;
|
||||
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
|
||||
v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
|
||||
else
|
||||
v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
|
||||
__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
|
||||
|
||||
v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET);
|
||||
if (flags & MXC_EHCI_ITC_NO_THRESHOLD)
|
||||
/* Interrupt Threshold Control:Immediate (no threshold) */
|
||||
v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
|
||||
__raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
|
||||
break;
|
||||
case 2: /* Host 2 ULPI */
|
||||
v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
|
||||
if (flags & MXC_EHCI_WAKEUP_ENABLED) {
|
||||
/* HOST1 wakeup/ULPI intr enable */
|
||||
v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
|
||||
} else {
|
||||
/* HOST1 wakeup/ULPI intr disable */
|
||||
v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
|
||||
}
|
||||
|
||||
if (flags & MXC_EHCI_POWER_PINS_ENABLED)
|
||||
v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/
|
||||
else
|
||||
v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
|
||||
__raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
|
||||
break;
|
||||
}
|
||||
|
||||
error:
|
||||
iounmap(usb_base);
|
||||
return ret;
|
||||
}
|
||||
|
||||
43
arch/arm/mach-imx/ehci.h
Normal file
43
arch/arm/mach-imx/ehci.h
Normal file
@ -0,0 +1,43 @@
|
||||
#ifndef __MACH_IMX_EHCI_H
|
||||
#define __MACH_IMX_EHCI_H
|
||||
|
||||
/* values for portsc field */
|
||||
#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
|
||||
#define MXC_EHCI_FORCE_FS (1 << 24)
|
||||
#define MXC_EHCI_UTMI_8BIT (0 << 28)
|
||||
#define MXC_EHCI_UTMI_16BIT (1 << 28)
|
||||
#define MXC_EHCI_SERIAL (1 << 29)
|
||||
#define MXC_EHCI_MODE_UTMI (0 << 30)
|
||||
#define MXC_EHCI_MODE_PHILIPS (1 << 30)
|
||||
#define MXC_EHCI_MODE_ULPI (2 << 30)
|
||||
#define MXC_EHCI_MODE_SERIAL (3 << 30)
|
||||
|
||||
/* values for flags field */
|
||||
#define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0)
|
||||
#define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0)
|
||||
#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
|
||||
#define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0)
|
||||
#define MXC_EHCI_INTERFACE_MASK (0xf)
|
||||
|
||||
#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
|
||||
#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6)
|
||||
#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7)
|
||||
#define MXC_EHCI_TTL_ENABLED (1 << 8)
|
||||
|
||||
#define MXC_EHCI_INTERNAL_PHY (1 << 9)
|
||||
#define MXC_EHCI_IPPUE_DOWN (1 << 10)
|
||||
#define MXC_EHCI_IPPUE_UP (1 << 11)
|
||||
#define MXC_EHCI_WAKEUP_ENABLED (1 << 12)
|
||||
#define MXC_EHCI_ITC_NO_THRESHOLD (1 << 13)
|
||||
|
||||
#define MXC_USBCTRL_OFFSET 0
|
||||
#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
|
||||
#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
|
||||
#define MXC_USBH2CTRL_OFFSET 0x14
|
||||
|
||||
int mx25_initialize_usb_hw(int port, unsigned int flags);
|
||||
int mx31_initialize_usb_hw(int port, unsigned int flags);
|
||||
int mx35_initialize_usb_hw(int port, unsigned int flags);
|
||||
int mx27_initialize_usb_hw(int port, unsigned int flags);
|
||||
|
||||
#endif /* __MACH_IMX_EHCI_H */
|
||||
@ -27,13 +27,14 @@ static void __iomem *gpc_base;
|
||||
static u32 gpc_wake_irqs[IMR_NUM];
|
||||
static u32 gpc_saved_imrs[IMR_NUM];
|
||||
|
||||
void imx_gpc_pre_suspend(void)
|
||||
void imx_gpc_pre_suspend(bool arm_power_off)
|
||||
{
|
||||
void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
|
||||
int i;
|
||||
|
||||
/* Tell GPC to power off ARM core when suspend */
|
||||
writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
|
||||
if (arm_power_off)
|
||||
writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
|
||||
|
||||
for (i = 0; i < IMR_NUM; i++) {
|
||||
gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
|
||||
|
||||
@ -105,8 +105,6 @@
|
||||
|
||||
#include "mxc.h"
|
||||
|
||||
#include "mx51.h"
|
||||
#include "mx53.h"
|
||||
#include "mx3x.h"
|
||||
#include "mx31.h"
|
||||
#include "mx35.h"
|
||||
|
||||
@ -29,16 +29,10 @@ static const char * const imx25_dt_board_compat[] __initconst = {
|
||||
NULL
|
||||
};
|
||||
|
||||
static void __init imx25_timer_init(void)
|
||||
{
|
||||
mx25_clocks_init_dt();
|
||||
}
|
||||
|
||||
DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
|
||||
.map_io = mx25_map_io,
|
||||
.init_early = imx25_init_early,
|
||||
.init_irq = mx25_init_irq,
|
||||
.init_time = imx25_timer_init,
|
||||
.init_machine = imx25_dt_init,
|
||||
.dt_compat = imx25_dt_board_compat,
|
||||
.restart = mxc_restart,
|
||||
|
||||
@ -34,16 +34,10 @@ static const char * const imx27_dt_board_compat[] __initconst = {
|
||||
NULL
|
||||
};
|
||||
|
||||
static void __init imx27_timer_init(void)
|
||||
{
|
||||
mx27_clocks_init_dt();
|
||||
}
|
||||
|
||||
DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
|
||||
.map_io = mx27_map_io,
|
||||
.init_early = imx27_init_early,
|
||||
.init_irq = mx27_init_irq,
|
||||
.init_time = imx27_timer_init,
|
||||
.init_machine = imx27_dt_init,
|
||||
.dt_compat = imx27_dt_board_compat,
|
||||
.restart = mxc_restart,
|
||||
|
||||
@ -25,7 +25,7 @@ static void __init imx31_dt_init(void)
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static const char *imx31_dt_board_compat[] __initconst = {
|
||||
static const char * const imx31_dt_board_compat[] __initconst = {
|
||||
"fsl,imx31",
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -34,7 +34,7 @@ static void __init imx35_irq_init(void)
|
||||
mx35_init_irq();
|
||||
}
|
||||
|
||||
static const char *imx35_dt_board_compat[] __initconst = {
|
||||
static const char * const imx35_dt_board_compat[] __initconst = {
|
||||
"fsl,imx35",
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -1,827 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
|
||||
* Copyright (C) 2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#ifndef __MACH_IOMUX_MX51_H__
|
||||
#define __MACH_IOMUX_MX51_H__
|
||||
|
||||
#include "iomux-v3.h"
|
||||
#define __NA_ 0x000
|
||||
|
||||
|
||||
/* Pad control groupings */
|
||||
#define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
|
||||
PAD_CTL_HYS | PAD_CTL_SRE_FAST)
|
||||
#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_HYS)
|
||||
#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_HYS)
|
||||
#define MX51_USBH1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
|
||||
PAD_CTL_HYS | PAD_CTL_PUE)
|
||||
#define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
|
||||
#define MX51_SDHCI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
|
||||
PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
|
||||
PAD_CTL_SRE_FAST | PAD_CTL_DVS)
|
||||
#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
|
||||
|
||||
#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS)
|
||||
#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
|
||||
#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
|
||||
#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
|
||||
|
||||
/*
|
||||
* The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
|
||||
* If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
|
||||
* See also iomux-v3.h
|
||||
*/
|
||||
|
||||
/* Raw pin modes without pad control */
|
||||
/* PAD MUX ALT INPSE PATH PADCTRL */
|
||||
|
||||
/* The same pins as above but with the default pad control values applied */
|
||||
#define MX51_PAD_EIM_D16__AUD4_RXFS IOMUX_PAD(0x3f0, 0x05c, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D16__AUD5_TXD IOMUX_PAD(0x3f0, 0x05c, 7, 0x8d8, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D16__GPIO2_0 IOMUX_PAD(0x3f0, 0x05c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, 0x14, 0x9b4, 0, MX51_I2C_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D16__UART2_CTS IOMUX_PAD(0x3f0, 0x05c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D16__USBH2_DATA0 IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D17__AUD5_RXD IOMUX_PAD(0x3f4, 0x060, 7, 0x8d4, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D17__GPIO2_1 IOMUX_PAD(0x3f4, 0x060, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D17__UART2_RXD IOMUX_PAD(0x3f4, 0x060, 3, 0x9ec, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D17__UART3_CTS IOMUX_PAD(0x3f4, 0x060, 4, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D17__USBH2_DATA1 IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D18__AUD5_TXC IOMUX_PAD(0x3f8, 0x064, 7, 0x8e4, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D18__GPIO2_2 IOMUX_PAD(0x3f8, 0x064, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D18__UART2_TXD IOMUX_PAD(0x3f8, 0x064, 3, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D18__UART3_RTS IOMUX_PAD(0x3f8, 0x064, 4, 0x9f0, 1, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D18__USBH2_DATA2 IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D19__AUD4_RXC IOMUX_PAD(0x3fc, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D19__AUD5_TXFS IOMUX_PAD(0x3fc, 0x068, 7, 0x8e8, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D19__GPIO2_3 IOMUX_PAD(0x3fc, 0x068, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, 0x14, 0x9b0, 0, MX51_I2C_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D19__UART2_RTS IOMUX_PAD(0x3fc, 0x068, 3, 0x9e8, 1, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D19__USBH2_DATA3 IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D20__AUD4_TXD IOMUX_PAD(0x400, 0x06c, 5, 0x8c8, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x06c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x06c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB IOMUX_PAD(0x400, 0x06c, 4, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D20__USBH2_DATA4 IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D21__AUD4_RXD IOMUX_PAD(0x404, 0x070, 5, 0x8c4, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x070, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB IOMUX_PAD(0x404, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D21__USBH2_DATA5 IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D22__AUD4_TXC IOMUX_PAD(0x408, 0x074, 5, 0x8cc, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D22__GPIO2_6 IOMUX_PAD(0x408, 0x074, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D22__USBH2_DATA6 IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D23__AUD4_TXFS IOMUX_PAD(0x40c, 0x078, 5, 0x8d0, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40c, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D23__GPIO2_7 IOMUX_PAD(0x40c, 0x078, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D23__SPDIF_OUT1 IOMUX_PAD(0x40c, 0x078, 4, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D23__USBH2_DATA7 IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D24__AUD6_RXFS IOMUX_PAD(0x410, 0x07c, 5, 0x8f8, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x07c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D24__GPIO2_8 IOMUX_PAD(0x410, 0x07c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D24__I2C2_SDA IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D24__USBOTG_DATA0 IOMUX_PAD(0x410, 0x07c, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D25__KEY_COL6 IOMUX_PAD(0x414, 0x080, 1, 0x9c8, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D25__GPT_CMPOUT1 IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D26__GPT_CMPOUT2 IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D27__I2C2_SCL IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D27__USBOTG_DATA3 IOMUX_PAD(0x41c, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D28__AUD6_TXD IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D28__KEY_ROW4 IOMUX_PAD(0x420, 0x08c, 1, 0x9d0, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D28__USBOTG_DATA4 IOMUX_PAD(0x420, 0x08c, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D29__AUD6_RXD IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D29__KEY_ROW5 IOMUX_PAD(0x424, 0x090, 1, 0x9d4, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D29__USBOTG_DATA5 IOMUX_PAD(0x424, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D30__AUD6_TXC IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D30__KEY_ROW6 IOMUX_PAD(0x428, 0x094, 1, 0x9d8, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D30__USBOTG_DATA6 IOMUX_PAD(0x428, 0x094, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D31__AUD6_TXFS IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D31__KEY_ROW7 IOMUX_PAD(0x42c, 0x098, 1, 0x9dc, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_D31__USBOTG_DATA7 IOMUX_PAD(0x42c, 0x098, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x09c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A16__GPIO2_10 IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 IOMUX_PAD(0x430, 0x09c, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A17__GPIO2_11 IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 IOMUX_PAD(0x434, 0x0a0, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A18__BOOT_LPB0 IOMUX_PAD(0x438, 0x0a4, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A18__GPIO2_12 IOMUX_PAD(0x438, 0x0a4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A19__BOOT_LPB1 IOMUX_PAD(0x43c, 0x0a8, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A19__GPIO2_13 IOMUX_PAD(0x43c, 0x0a8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 IOMUX_PAD(0x440, 0x0ac, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A21__GPIO2_15 IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A23__BOOT_HPN_EN IOMUX_PAD(0x44c, 0x0b8, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A23__GPIO2_17 IOMUX_PAD(0x44c, 0x0b8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A24__GPIO2_18 IOMUX_PAD(0x450, 0x0bc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A24__USBH2_CLK IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A25__DISP1_PIN4 IOMUX_PAD(0x454, 0x0c0, 6, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A25__GPIO2_19 IOMUX_PAD(0x454, 0x0c0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A25__USBH2_DIR IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A26__CSI1_DATA_EN IOMUX_PAD(0x458, 0x0c4, 5, 0x9a0, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A26__DISP2_EXT_CLK IOMUX_PAD(0x458, 0x0c4, 6, 0x908, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A26__GPIO2_20 IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A26__USBH2_STP IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A27__CSI2_DATA_EN IOMUX_PAD(0x45c, 0x0c8, 5, 0x99c, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A27__DISP1_PIN1 IOMUX_PAD(0x45c, 0x0c8, 6, 0x9a4, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A27__GPIO2_21 IOMUX_PAD(0x45c, 0x0c8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_A27__USBH2_NXT IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_EB2__AUD5_RXFS IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_EB2__CSI1_D2 IOMUX_PAD(0x468, 0x0d4, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_EB2__FEC_MDIO (IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, 0) | \
|
||||
MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
|
||||
PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS))
|
||||
#define MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0x0d4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 IOMUX_PAD(0x468, 0x0d4, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_EB3__AUD5_RXC IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_EB3__CSI1_D3 IOMUX_PAD(0x46c, 0x0d8, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 IOMUX_PAD(0x46c, 0x0d8, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0x0dc, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0x0dc, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS0__GPIO2_25 IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS1__GPIO2_26 IOMUX_PAD(0x478, 0x0e4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS2__AUD5_TXD IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS2__CSI1_D4 IOMUX_PAD(0x47c, 0x0e8, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS2__USBOTG_STP IOMUX_PAD(0x47c, 0x0e8, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS3__AUD5_RXD IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS3__CSI1_D5 IOMUX_PAD(0x480, 0x0ec, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS3__USBOTG_NXT IOMUX_PAD(0x480, 0x0ec, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS4__AUD5_TXC IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS4__CSI1_D6 IOMUX_PAD(0x484, 0x0f0, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2)
|
||||
#define MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS4__USBOTG_CLK IOMUX_PAD(0x484, 0x0f0, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS5__AUD5_TXFS IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS5__CSI1_D7 IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2)
|
||||
#define MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CS5__USBOTG_DIR IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0x0f8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0x0fc, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0x0fc, 1, 0x978, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DRAM_CS1__CCM_CLKO IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_WE_B__SD3_DATA0 IOMUX_PAD(0x4e4, 0x108, 2, 0x93c, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RE_B__GPIO3_4 IOMUX_PAD(0x4e8, 0x10c, 3, 0x984, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RE_B__PATA_DIOR IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RE_B__SD3_DATA1 IOMUX_PAD(0x4e8, 0x10c, 2, 0x940, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_ALE__GPIO3_5 IOMUX_PAD(0x4ec, 0x110, 3, 0x988, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CLE__GPIO3_6 IOMUX_PAD(0x4f0, 0x114, 3, 0x98c, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CLE__PATA_RESET_B IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_WP_B__GPIO3_7 IOMUX_PAD(0x4f4, 0x118, 3, 0x990, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_WP_B__PATA_DMACK IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_WP_B__SD3_DATA2 IOMUX_PAD(0x4f4, 0x118, 2, 0x944, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 IOMUX_PAD(0x4f8, 0x11c, 5, 0x930, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB0__GPIO3_8 IOMUX_PAD(0x4f8, 0x11c, 3, 0x994, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB0__PATA_DMARQ IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB0__SD3_DATA3 IOMUX_PAD(0x4f8, 0x11c, 2, 0x948, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB1__CSPI_MOSI IOMUX_PAD(0x4fc, 0x120, 6, 0x91c, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB1__ECSPI2_RDY IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB1__GPT_CMPOUT2 IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2)
|
||||
#define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB2__GPT_CMPOUT3 IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2)
|
||||
#define MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 0x17, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS1__GPIO3_17 IOMUX_PAD(0x51c, 0x134, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51c, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS2__CSPI_SCLK IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5)
|
||||
#define MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
|
||||
#define MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 0x17, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5)
|
||||
#define MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 0x17, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5)
|
||||
#define MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS4__PATA_DA_0 IOMUX_PAD(0x528, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS4__SD4_DAT1 IOMUX_PAD(0x528, 0x140, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS4__USBH3_STP IOMUX_PAD(0x528, 0x140, 7, 0xa24, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52c, 0x144, 2, __NA_, 0, MX51_PAD_CTRL_5)
|
||||
#define MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52c, 0x144, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52c, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS5__PATA_DA_1 IOMUX_PAD(0x52c, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS5__SD4_DAT2 IOMUX_PAD(0x52c, 0x144, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS5__USBH3_DIR IOMUX_PAD(0x52c, 0x144, 7, 0xa1c, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS6__CSPI_SS3 IOMUX_PAD(0x530, 0x148, 7, 0x928, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, __NA_, 0, MX51_PAD_CTRL_5)
|
||||
#define MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS6__PATA_DA_2 IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS6__SD4_DAT3 IOMUX_PAD(0x530, 0x148, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5)
|
||||
#define MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_CS7__SD3_CLK IOMUX_PAD(0x534, 0x14c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
|
||||
#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 IOMUX_PAD(0x538, 0x150, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4)
|
||||
#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D15__PATA_DATA15 IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D15__SD3_DAT7 IOMUX_PAD(0x53c, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D14__ECSPI2_SS3 IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D14__GPIO3_26 IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D14__PATA_DATA14 IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D14__SD3_DAT6 IOMUX_PAD(0x540, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D13__ECSPI2_SS2 IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D13__GPIO3_27 IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D13__PATA_DATA13 IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D13__SD3_DAT5 IOMUX_PAD(0x544, 0x15c, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D12__ECSPI2_SS1 IOMUX_PAD(0x548, 0x160, 2, 0x930, 1, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D12__GPIO3_28 IOMUX_PAD(0x548, 0x160, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D12__PATA_DATA12 IOMUX_PAD(0x548, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D12__SD3_DAT4 IOMUX_PAD(0x548, 0x160, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54c, 0x164, 2, 0x96c, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54c, 0x164, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54c, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D11__PATA_DATA11 IOMUX_PAD(0x54c, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D11__SD3_DATA3 IOMUX_PAD(0x54c, 0x164, 5, 0x948, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D10__PATA_DATA10 IOMUX_PAD(0x550, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D10__SD3_DATA2 IOMUX_PAD(0x550, 0x168, 5, 0x944, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16c, 0x12, 0x958, 0, MX51_PAD_CTRL_4)
|
||||
#define MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D9__PATA_DATA9 IOMUX_PAD(0x554, 0x16c, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D9__SD3_DATA1 IOMUX_PAD(0x554, 0x16c, 5, 0x940, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, __NA_, 0, MX51_PAD_CTRL_5)
|
||||
#define MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D8__PATA_DATA8 IOMUX_PAD(0x558, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D8__SD3_DATA0 IOMUX_PAD(0x558, 0x170, 5, 0x93c, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D7__GPIO4_1 IOMUX_PAD(0x55c, 0x174, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55c, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D7__PATA_DATA7 IOMUX_PAD(0x55c, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D7__USBH3_DATA0 IOMUX_PAD(0x55c, 0x174, 5, 0x9fc, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D6__GPIO4_2 IOMUX_PAD(0x560, 0x178, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D6__PATA_DATA6 IOMUX_PAD(0x560, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D6__SD4_LCTL IOMUX_PAD(0x560, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D6__USBH3_DATA1 IOMUX_PAD(0x560, 0x178, 5, 0xa00, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D5__GPIO4_3 IOMUX_PAD(0x564, 0x17c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D5__PATA_DATA5 IOMUX_PAD(0x564, 0x17c, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D5__SD4_WP IOMUX_PAD(0x564, 0x17c, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D5__USBH3_DATA2 IOMUX_PAD(0x564, 0x17c, 5, 0xa04, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D4__GPIO4_4 IOMUX_PAD(0x568, 0x180, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D4__PATA_DATA4 IOMUX_PAD(0x568, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D4__SD4_CD IOMUX_PAD(0x568, 0x180, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D4__USBH3_DATA3 IOMUX_PAD(0x568, 0x180, 5, 0xa08, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D3__GPIO4_5 IOMUX_PAD(0x56c, 0x184, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56c, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D3__PATA_DATA3 IOMUX_PAD(0x56c, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D3__SD4_DAT4 IOMUX_PAD(0x56c, 0x184, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D3__USBH3_DATA4 IOMUX_PAD(0x56c, 0x184, 5, 0xa0c, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D2__GPIO4_6 IOMUX_PAD(0x570, 0x188, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D2__PATA_DATA2 IOMUX_PAD(0x570, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D2__SD4_DAT5 IOMUX_PAD(0x570, 0x188, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D2__USBH3_DATA5 IOMUX_PAD(0x570, 0x188, 5, 0xa10, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D1__GPIO4_7 IOMUX_PAD(0x574, 0x18c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D1__PATA_DATA1 IOMUX_PAD(0x574, 0x18c, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D1__SD4_DAT6 IOMUX_PAD(0x574, 0x18c, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D1__USBH3_DATA6 IOMUX_PAD(0x574, 0x18c, 5, 0xa14, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D0__GPIO4_8 IOMUX_PAD(0x578, 0x190, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D0__PATA_DATA0 IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D0__SD4_DAT7 IOMUX_PAD(0x578, 0x190, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_NANDF_D0__USBH3_DATA7 IOMUX_PAD(0x578, 0x190, 5, 0xa18, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57c, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_D8__GPIO3_12 IOMUX_PAD(0x57c, 0x194, 3, 0x998, 1, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1a0, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58c, 0x1a4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1a8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1ac, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1b0, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59c, 0x1b4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5a0, 0x1b8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5a4, 0x1bc, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5a8, 0x1c0, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5ac, 0x1c4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_VSYNC__GPIO3_14 IOMUX_PAD(0x5ac, 0x1c4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5b0, 0x1c8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_HSYNC__GPIO3_15 IOMUX_PAD(0x5b0, 0x1c8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5b4, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5b8, __NA_, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5bc, 0x1cc, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_D12__GPIO4_9 IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5c0, 0x1d0, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5c4, 0x1d4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5c8, 0x1d8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5cc, 0x1dc, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5d0, 0x1e0, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5d4, 0x1e4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_D18__GPIO4_11 IOMUX_PAD(0x5d4, 0x1e4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5d8, 0x1e8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_D19__GPIO4_12 IOMUX_PAD(0x5d8, 0x1e8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_VSYNC__GPIO4_13 IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_HSYNC__GPIO4_14 IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5e4, 0x1f4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 IOMUX_PAD(0x5e4, 0x1f4, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_I2C1_CLK__GPIO4_16 IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
|
||||
#define MX51_PAD_I2C1_DAT__GPIO4_17 IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL)
|
||||
#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD IOMUX_PAD(0x5f0, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5f0, 0x200, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD IOMUX_PAD(0x5f4, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_AUD3_BB_RXD__UART3_RXD IOMUX_PAD(0x5f4, 0x204, 1, 0x9f4, 2, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_AUD3_BB_CK__AUD3_TXC IOMUX_PAD(0x5f8, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5f8, 0x208, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS IOMUX_PAD(0x5fc, 0x20c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_AUD3_BB_FS__GPIO4_21 IOMUX_PAD(0x5fc, 0x20c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_AUD3_BB_FS__UART3_TXD IOMUX_PAD(0x5fc, 0x20c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_MOSI__GPIO4_22 IOMUX_PAD(0x600, 0x210, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_MOSI__I2C1_SDA IOMUX_PAD(0x600, 0x210, 0x11, 0x9b4, 1, MX51_I2C_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_MISO__AUD4_RXD IOMUX_PAD(0x604, 0x214, 1, 0x8c4, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_MISO__GPIO4_23 IOMUX_PAD(0x604, 0x214, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_SS0__AUD4_TXC IOMUX_PAD(0x608, 0x218, 1, 0x8cc, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_SS1__AUD4_TXD IOMUX_PAD(0x60c, 0x21c, 1, 0x8c8, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60c, 0x21c, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60c, 0x21c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_RDY__AUD4_TXFS IOMUX_PAD(0x610, 0x220, 1, 0x8d0, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_RDY__GPIO4_26 IOMUX_PAD(0x610, 0x220, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_SCLK__GPIO4_27 IOMUX_PAD(0x614, 0x224, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_CSPI1_SCLK__I2C1_SCL IOMUX_PAD(0x614, 0x224, 0x11, 0x9b0, 1, MX51_I2C_PAD_CTRL)
|
||||
#define MX51_PAD_UART1_RXD__GPIO4_28 IOMUX_PAD(0x618, 0x228, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_UART1_TXD__GPIO4_29 IOMUX_PAD(0x61c, 0x22c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x61c, 0x22c, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_UART1_RTS__GPIO4_30 IOMUX_PAD(0x620, 0x230, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_UART1_CTS__GPIO4_31 IOMUX_PAD(0x624, 0x234, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_UART2_RXD__FIRI_TXD IOMUX_PAD(0x628, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_UART2_RXD__GPIO1_20 IOMUX_PAD(0x628, 0x238, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_UART3_TXD__CSI1_D1 IOMUX_PAD(0x634, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_UART3_TXD__GPIO1_23 IOMUX_PAD(0x634, 0x244, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_UART3_TXD__UART1_DSR IOMUX_PAD(0x634, 0x244, 0, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_OWIRE_LINE__GPIO1_24 IOMUX_PAD(0x638, 0x248, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_OWIRE_LINE__SPDIF_OUT IOMUX_PAD(0x638, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63c, 0x24c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64c, 0x25c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_COL0__PLL1_BYP IOMUX_PAD(0x64c, 0x25c, 7, 0x90c, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_COL1__PLL2_BYP IOMUX_PAD(0x650, 0x260, 7, 0x910, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_COL2__PLL3_BYP IOMUX_PAD(0x654, 0x264, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65c, 0x26c, 0x13, 0x9b8, 1, MX51_I2C_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65c, 0x26c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_COL4__SPDIF_OUT1 IOMUX_PAD(0x65c, 0x26c, 6, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_COL4__UART1_RI IOMUX_PAD(0x65c, 0x26c, 1, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65c, 0x26c, 2, 0x9f0, 4, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, 0x13, 0x9bc, 1, MX51_I2C_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_COL5__UART1_DCD IOMUX_PAD(0x660, 0x270, 1, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_CLK__CSPI_SCLK IOMUX_PAD(0x678, 0x278, 1, 0x914, 1, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_CLK__GPIO1_25 IOMUX_PAD(0x678, 0x278, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_CLK__I2C2_SCL IOMUX_PAD(0x678, 0x278, 0x15, 0x9b8, 2, MX51_I2C_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DIR__CSPI_MOSI IOMUX_PAD(0x67c, 0x27c, 1, 0x91c, 1, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DIR__GPIO1_26 IOMUX_PAD(0x67c, 0x27c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DIR__I2C2_SDA IOMUX_PAD(0x67c, 0x27c, 0x15, 0x9bc, 2, MX51_I2C_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_STP__CSPI_RDY IOMUX_PAD(0x680, 0x280, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_STP__GPIO1_27 IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_STP__UART3_RXD IOMUX_PAD(0x680, 0x280, 5, 0x9f4, 6, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_NXT__CSPI_MISO IOMUX_PAD(0x684, 0x284, 1, 0x918, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_NXT__GPIO1_28 IOMUX_PAD(0x684, 0x284, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_NXT__UART3_TXD IOMUX_PAD(0x684, 0x284, 5, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA0__GPIO1_11 IOMUX_PAD(0x688, 0x288, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA0__UART2_CTS IOMUX_PAD(0x688, 0x288, 1, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA1__GPIO1_12 IOMUX_PAD(0x68c, 0x28c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x9ec, 4, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x9e8, 5, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA4__CSPI_SS0 IOMUX_PAD(0x698, 0x298, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA4__GPIO1_15 IOMUX_PAD(0x698, 0x298, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA5__CSPI_SS1 IOMUX_PAD(0x69c, 0x29c, 1, 0x920, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA5__GPIO1_16 IOMUX_PAD(0x69c, 0x29c, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA6__CSPI_SS3 IOMUX_PAD(0x6a0, 0x2a0, 1, 0x928, 1, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA6__GPIO1_17 IOMUX_PAD(0x6a0, 0x2a0, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 IOMUX_PAD(0x6a4, 0x2a4, 1, __NA_, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 IOMUX_PAD(0x6a4, 0x2a4, 5, 0x934, 1, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA7__GPIO1_18 IOMUX_PAD(0x6a4, 0x2a4, 2, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6a8, 0x2a8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 IOMUX_PAD(0x6a8, 0x2a8, 7, __NA_, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_PIN11__GPIO3_0 IOMUX_PAD(0x6a8, 0x2a8, 4, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6ac, 0x2ac, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_PIN12__GPIO3_1 IOMUX_PAD(0x6ac, 0x2ac, 4, 0x978, 1, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6b0, 0x2b0, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_PIN13__GPIO3_2 IOMUX_PAD(0x6b0, 0x2b0, 4, 0x97c, 1, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6b4, 0x2b4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6b4, 0x2b4, 4, 0x980, 1, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6b8, 0x2b8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 IOMUX_PAD(0x6b8, 0x2b8, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 IOMUX_PAD(0x6b8, 0x2b8, 3, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 IOMUX_PAD(0x6bc, 0x2bc, 2, 0x9a4, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x9c4, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 IOMUX_PAD(0x6c0, 0x2c0, 3, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x9c4, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 IOMUX_PAD(0x6c4, 0x2c4, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 IOMUX_PAD(0x6c4, 0x2c4, 3, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 IOMUX_PAD(0x6c4, 0x2c4, 4, 0x990, 1, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI1_PIN15__DI1_PIN15 IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI_GP3__DISP1_SER_DIO IOMUX_PAD(0x744, 0x33c, 0, 0x9c0, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI_GP3__FEC_TX_ER IOMUX_PAD(0x744, 0x33c, 2, __NA_, 0, MX51_PAD_CTRL_5)
|
||||
#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN IOMUX_PAD(0x748, 0x340, 3, 0x99c, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI2_PIN4__FEC_CRS IOMUX_PAD(0x748, 0x340, 2, 0x950, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, __NA_, 0, MX51_PAD_CTRL_5)
|
||||
#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x954, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x95c, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x9c0, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x960, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x964, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x9c8, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x9f4, 8, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x9f8, 1, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x970, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x9cc, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, __NA_, 0, MX51_UART_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0xa1c, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76c, 0x364, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5)
|
||||
#define MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5)
|
||||
#define MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5)
|
||||
#define MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5)
|
||||
#define MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x94c, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x9dc, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0xa04, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x96c, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0xa0c, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x8fc, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK IOMUX_PAD(0x790, 0x388, 2, 0x974, 1, MX51_PAD_CTRL_4)
|
||||
#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 IOMUX_PAD(0x790, 0x388, 3, 0xa10, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT14__AUD6_TXFS IOMUX_PAD(0x794, 0x38c, 4, 0x900, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38c, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 IOMUX_PAD(0x794, 0x38c, 2, 0x958, 1, MX51_PAD_CTRL_4)
|
||||
#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 IOMUX_PAD(0x794, 0x38c, 3, 0xa14, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT15__AUD6_RXFS IOMUX_PAD(0x798, 0x390, 4, 0x8f8, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS IOMUX_PAD(0x798, 0x390, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 IOMUX_PAD(0x798, 0x390, 2, __NA_, 0, MX51_PAD_CTRL_5)
|
||||
#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 IOMUX_PAD(0x798, 0x390, 3, 0xa18, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79c, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x79c, 0x394, 2, 0x91c, 2, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7a0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x7a0, 0x398, 2, 0x914, 2, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
|
||||
#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7a4, 0x39c, 1, 0x8d8, 2, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x7a4, 0x39c, 2, 0x918, 1, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(__NA_, 0x01c, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(__NA_, 0x020, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(__NA_, 0x024, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(__NA_, 0x028, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7a8, 0x3a0, 1, 0x8d4, 2, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7a8, 0x3a0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(__NA_, 0x02c, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(__NA_, 0x030, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(__NA_, 0x034, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(__NA_, 0x038, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7ac, 0x3a4, 1, 0x8e4, 2, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7ac, 0x3a4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(__NA_, 0x044, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(__NA_, 0x048, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(__NA_, 0x03c, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(__NA_, 0x040, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7b0, 0x3a8, 1, 0x8e8, 2, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x7bc, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_CLK__I2C1_SDA IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x9b4, 2, MX51_I2C_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
|
||||
#define MX51_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x7c4, 0x3bc, 2, 0x918, 3, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_DATA0__SD1_DAT4 IOMUX_PAD(0x7c4, 0x3bc, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 0x12, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 0x12, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_3__CCM_CLKO2 IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_3__GPT_CLKIN IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_4__GPT_CAPIN1 IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_5__CCM_CLKO IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_6__GPT_CAPIN2 IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_8__CCM_CLKO2 IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL)
|
||||
#define MX51_PAD_GPIO1_9__CCM_CLKO IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL)
|
||||
|
||||
#endif /* __MACH_IOMUX_MX51_H__ */
|
||||
@ -50,6 +50,7 @@
|
||||
#include "common.h"
|
||||
#include "devices-imx31.h"
|
||||
#include "crmregs-imx3.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx3.h"
|
||||
#include "ulpi.h"
|
||||
|
||||
@ -36,6 +36,7 @@
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx27.h"
|
||||
#include "ehci.h"
|
||||
#include "eukrea-baseboards.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx27.h"
|
||||
|
||||
@ -39,6 +39,7 @@
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx35.h"
|
||||
#include "ehci.h"
|
||||
#include "eukrea-baseboards.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx35.h"
|
||||
|
||||
@ -35,6 +35,7 @@
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx25.h"
|
||||
#include "ehci.h"
|
||||
#include "eukrea-baseboards.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx25.h"
|
||||
|
||||
@ -43,6 +43,7 @@
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx27.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx27.h"
|
||||
|
||||
|
||||
@ -1,77 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include "hardware.h"
|
||||
#include "common.h"
|
||||
#include "devices-imx27.h"
|
||||
#include "iomux-mx27.h"
|
||||
|
||||
static const int mx27ipcam_pins[] __initconst = {
|
||||
/* UART1 */
|
||||
PE12_PF_UART1_TXD,
|
||||
PE13_PF_UART1_RXD,
|
||||
/* FEC */
|
||||
PD0_AIN_FEC_TXD0,
|
||||
PD1_AIN_FEC_TXD1,
|
||||
PD2_AIN_FEC_TXD2,
|
||||
PD3_AIN_FEC_TXD3,
|
||||
PD4_AOUT_FEC_RX_ER,
|
||||
PD5_AOUT_FEC_RXD1,
|
||||
PD6_AOUT_FEC_RXD2,
|
||||
PD7_AOUT_FEC_RXD3,
|
||||
PD8_AF_FEC_MDIO,
|
||||
PD9_AIN_FEC_MDC,
|
||||
PD10_AOUT_FEC_CRS,
|
||||
PD11_AOUT_FEC_TX_CLK,
|
||||
PD12_AOUT_FEC_RXD0,
|
||||
PD13_AOUT_FEC_RX_DV,
|
||||
PD14_AOUT_FEC_RX_CLK,
|
||||
PD15_AOUT_FEC_COL,
|
||||
PD16_AIN_FEC_TX_ER,
|
||||
PF23_AIN_FEC_TX_EN,
|
||||
};
|
||||
|
||||
static void __init mx27ipcam_init(void)
|
||||
{
|
||||
imx27_soc_init();
|
||||
|
||||
mxc_gpio_setup_multiple_pins(mx27ipcam_pins, ARRAY_SIZE(mx27ipcam_pins),
|
||||
"mx27ipcam");
|
||||
|
||||
imx27_add_imx_uart0(NULL);
|
||||
imx27_add_fec(NULL);
|
||||
imx27_add_imx2_wdt();
|
||||
}
|
||||
|
||||
static void __init mx27ipcam_timer_init(void)
|
||||
{
|
||||
mx27_clocks_init(25000000);
|
||||
}
|
||||
|
||||
MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
|
||||
/* maintainer: Freescale Semiconductor, Inc. */
|
||||
.atag_offset = 0x100,
|
||||
.map_io = mx27_map_io,
|
||||
.init_early = imx27_init_early,
|
||||
.init_irq = mx27_init_irq,
|
||||
.init_time = mx27ipcam_timer_init,
|
||||
.init_machine = mx27ipcam_init,
|
||||
.restart = mxc_restart,
|
||||
MACHINE_END
|
||||
@ -1,83 +0,0 @@
|
||||
/*
|
||||
* Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
|
||||
* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
|
||||
* Copyright 2009 Daniel Schaeffer (daniel.schaeffer@timesys.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx27.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx27.h"
|
||||
|
||||
static const int mx27lite_pins[] __initconst = {
|
||||
/* UART1 */
|
||||
PE12_PF_UART1_TXD,
|
||||
PE13_PF_UART1_RXD,
|
||||
PE14_PF_UART1_CTS,
|
||||
PE15_PF_UART1_RTS,
|
||||
/* FEC */
|
||||
PD0_AIN_FEC_TXD0,
|
||||
PD1_AIN_FEC_TXD1,
|
||||
PD2_AIN_FEC_TXD2,
|
||||
PD3_AIN_FEC_TXD3,
|
||||
PD4_AOUT_FEC_RX_ER,
|
||||
PD5_AOUT_FEC_RXD1,
|
||||
PD6_AOUT_FEC_RXD2,
|
||||
PD7_AOUT_FEC_RXD3,
|
||||
PD8_AF_FEC_MDIO,
|
||||
PD9_AIN_FEC_MDC,
|
||||
PD10_AOUT_FEC_CRS,
|
||||
PD11_AOUT_FEC_TX_CLK,
|
||||
PD12_AOUT_FEC_RXD0,
|
||||
PD13_AOUT_FEC_RX_DV,
|
||||
PD14_AOUT_FEC_RX_CLK,
|
||||
PD15_AOUT_FEC_COL,
|
||||
PD16_AIN_FEC_TX_ER,
|
||||
PF23_AIN_FEC_TX_EN,
|
||||
};
|
||||
|
||||
static const struct imxuart_platform_data uart_pdata __initconst = {
|
||||
.flags = IMXUART_HAVE_RTSCTS,
|
||||
};
|
||||
|
||||
static void __init mx27lite_init(void)
|
||||
{
|
||||
imx27_soc_init();
|
||||
|
||||
mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
|
||||
"imx27lite");
|
||||
imx27_add_imx_uart0(&uart_pdata);
|
||||
imx27_add_fec(NULL);
|
||||
}
|
||||
|
||||
static void __init mx27lite_timer_init(void)
|
||||
{
|
||||
mx27_clocks_init(26000000);
|
||||
}
|
||||
|
||||
MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
|
||||
.atag_offset = 0x100,
|
||||
.map_io = mx27_map_io,
|
||||
.init_early = imx27_init_early,
|
||||
.init_irq = mx27_init_irq,
|
||||
.init_time = mx27lite_timer_init,
|
||||
.init_machine = mx27lite_init,
|
||||
.restart = mxc_restart,
|
||||
MACHINE_END
|
||||
@ -23,14 +23,13 @@ static void __init imx50_dt_init(void)
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static const char *imx50_dt_board_compat[] __initconst = {
|
||||
static const char * const imx50_dt_board_compat[] __initconst = {
|
||||
"fsl,imx50",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
|
||||
.map_io = mx53_map_io,
|
||||
.init_irq = mx53_init_irq,
|
||||
.init_irq = tzic_init_irq,
|
||||
.init_machine = imx50_dt_init,
|
||||
.dt_compat = imx50_dt_board_compat,
|
||||
.restart = mxc_restart,
|
||||
|
||||
@ -10,6 +10,7 @@
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
@ -17,27 +18,63 @@
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "mx51.h"
|
||||
#include "hardware.h"
|
||||
|
||||
static void __init imx51_init_early(void)
|
||||
{
|
||||
mxc_set_cpu_type(MXC_CPU_MX51);
|
||||
}
|
||||
|
||||
/*
|
||||
* The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
|
||||
* the Freescale marketing division. However this did not remove the
|
||||
* hardware from the chip which still needs to be configured for proper
|
||||
* IPU support.
|
||||
*/
|
||||
#define MX51_MIPI_HSC_BASE 0x83fdc000
|
||||
static void __init imx51_ipu_mipi_setup(void)
|
||||
{
|
||||
void __iomem *hsc_addr;
|
||||
|
||||
hsc_addr = ioremap(MX51_MIPI_HSC_BASE, SZ_16K);
|
||||
WARN_ON(!hsc_addr);
|
||||
|
||||
/* setup MIPI module to legacy mode */
|
||||
__raw_writel(0xf00, hsc_addr);
|
||||
|
||||
/* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
|
||||
__raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
|
||||
hsc_addr + 0x800);
|
||||
|
||||
iounmap(hsc_addr);
|
||||
}
|
||||
|
||||
static void __init imx51_dt_init(void)
|
||||
{
|
||||
struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
|
||||
|
||||
mxc_arch_reset_init_dt();
|
||||
imx51_ipu_mipi_setup();
|
||||
imx_src_init();
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
platform_device_register_full(&devinfo);
|
||||
}
|
||||
|
||||
static const char *imx51_dt_board_compat[] __initconst = {
|
||||
static void __init imx51_init_late(void)
|
||||
{
|
||||
mx51_neon_fixup();
|
||||
imx51_pm_init();
|
||||
}
|
||||
|
||||
static const char * const imx51_dt_board_compat[] __initconst = {
|
||||
"fsl,imx51",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
|
||||
.map_io = mx51_map_io,
|
||||
.init_early = imx51_init_early,
|
||||
.init_irq = mx51_init_irq,
|
||||
.init_irq = tzic_init_irq,
|
||||
.init_machine = imx51_dt_init,
|
||||
.init_late = imx51_init_late,
|
||||
.dt_compat = imx51_dt_board_compat,
|
||||
@ -22,24 +22,35 @@
|
||||
|
||||
#include "common.h"
|
||||
#include "hardware.h"
|
||||
#include "mx53.h"
|
||||
|
||||
static void __init imx53_init_early(void)
|
||||
{
|
||||
mxc_set_cpu_type(MXC_CPU_MX53);
|
||||
}
|
||||
|
||||
static void __init imx53_dt_init(void)
|
||||
{
|
||||
mxc_arch_reset_init_dt();
|
||||
imx_src_init();
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
|
||||
imx_aips_allow_unprivileged_access("fsl,imx53-aipstz");
|
||||
}
|
||||
|
||||
static const char *imx53_dt_board_compat[] __initconst = {
|
||||
static void __init imx53_init_late(void)
|
||||
{
|
||||
imx53_pm_init();
|
||||
}
|
||||
|
||||
static const char * const imx53_dt_board_compat[] __initconst = {
|
||||
"fsl,imx53",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
|
||||
.map_io = mx53_map_io,
|
||||
.init_early = imx53_init_early,
|
||||
.init_irq = mx53_init_irq,
|
||||
.init_irq = tzic_init_irq,
|
||||
.init_machine = imx53_dt_init,
|
||||
.init_late = imx53_init_late,
|
||||
.dt_compat = imx53_dt_board_compat,
|
||||
|
||||
@ -320,7 +320,7 @@ static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev)
|
||||
val >>= OCOTP_CFG3_SPEED_SHIFT;
|
||||
val &= 0x3;
|
||||
|
||||
if (val != OCOTP_CFG3_SPEED_1P2GHZ)
|
||||
if ((val != OCOTP_CFG3_SPEED_1P2GHZ) && cpu_is_imx6q())
|
||||
if (dev_pm_opp_disable(cpu_dev, 1200000000))
|
||||
pr_warn("failed to disable 1.2 GHz OPP\n");
|
||||
if (val < OCOTP_CFG3_SPEED_996MHZ)
|
||||
@ -396,7 +396,7 @@ static void __init imx6q_init_irq(void)
|
||||
irqchip_init();
|
||||
}
|
||||
|
||||
static const char *imx6q_dt_compat[] __initconst = {
|
||||
static const char * const imx6q_dt_compat[] __initconst = {
|
||||
"fsl,imx6dl",
|
||||
"fsl,imx6q",
|
||||
NULL,
|
||||
|
||||
@ -70,7 +70,7 @@ static void __init imx6sl_init_irq(void)
|
||||
irqchip_init();
|
||||
}
|
||||
|
||||
static const char *imx6sl_dt_compat[] __initconst = {
|
||||
static const char * const imx6sl_dt_compat[] __initconst = {
|
||||
"fsl,imx6sl",
|
||||
NULL,
|
||||
};
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "cpuidle.h"
|
||||
|
||||
static void __init imx6sx_init_machine(void)
|
||||
{
|
||||
@ -26,6 +27,7 @@ static void __init imx6sx_init_machine(void)
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
|
||||
|
||||
imx_anatop_init();
|
||||
imx6sx_pm_init();
|
||||
}
|
||||
|
||||
static void __init imx6sx_init_irq(void)
|
||||
@ -37,7 +39,12 @@ static void __init imx6sx_init_irq(void)
|
||||
irqchip_init();
|
||||
}
|
||||
|
||||
static const char *imx6sx_dt_compat[] __initconst = {
|
||||
static void __init imx6sx_init_late(void)
|
||||
{
|
||||
imx6q_cpuidle_init();
|
||||
}
|
||||
|
||||
static const char * const imx6sx_dt_compat[] __initconst = {
|
||||
"fsl,imx6sx",
|
||||
NULL,
|
||||
};
|
||||
@ -47,5 +54,6 @@ DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)")
|
||||
.init_irq = imx6sx_init_irq,
|
||||
.init_machine = imx6sx_init_machine,
|
||||
.dt_compat = imx6sx_dt_compat,
|
||||
.init_late = imx6sx_init_late,
|
||||
.restart = mxc_restart,
|
||||
MACHINE_END
|
||||
|
||||
@ -39,6 +39,7 @@
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx25.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx25.h"
|
||||
#include "mx25.h"
|
||||
|
||||
@ -40,6 +40,7 @@
|
||||
#include "3ds_debugboard.h"
|
||||
#include "common.h"
|
||||
#include "devices-imx27.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx27.h"
|
||||
#include "ulpi.h"
|
||||
|
||||
@ -40,6 +40,7 @@
|
||||
#include "3ds_debugboard.h"
|
||||
#include "common.h"
|
||||
#include "devices-imx31.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx3.h"
|
||||
#include "ulpi.h"
|
||||
|
||||
@ -45,6 +45,7 @@
|
||||
#include "board-mx31lilly.h"
|
||||
#include "common.h"
|
||||
#include "devices-imx31.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx3.h"
|
||||
#include "ulpi.h"
|
||||
|
||||
@ -42,6 +42,7 @@
|
||||
#include "board-mx31lite.h"
|
||||
#include "common.h"
|
||||
#include "devices-imx31.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx3.h"
|
||||
#include "ulpi.h"
|
||||
|
||||
@ -47,6 +47,7 @@
|
||||
#include "board-mx31moboard.h"
|
||||
#include "common.h"
|
||||
#include "devices-imx31.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx3.h"
|
||||
#include "ulpi.h"
|
||||
@ -434,10 +435,8 @@ static int __init moboard_usbh2_init(void)
|
||||
return -ENODEV;
|
||||
|
||||
pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
|
||||
if (IS_ERR(pdev))
|
||||
return PTR_ERR(pdev);
|
||||
|
||||
return 0;
|
||||
return PTR_ERR_OR_ZERO(pdev);
|
||||
}
|
||||
|
||||
static const struct gpio_led mx31moboard_leds[] __initconst = {
|
||||
|
||||
@ -50,6 +50,7 @@
|
||||
#include "3ds_debugboard.h"
|
||||
#include "common.h"
|
||||
#include "devices-imx35.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx35.h"
|
||||
|
||||
|
||||
@ -36,6 +36,7 @@
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx27.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx27.h"
|
||||
#include "ulpi.h"
|
||||
|
||||
@ -45,6 +45,7 @@
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx31.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx3.h"
|
||||
#include "pcm037.h"
|
||||
|
||||
@ -36,6 +36,7 @@
|
||||
#include "board-pcm038.h"
|
||||
#include "common.h"
|
||||
#include "devices-imx27.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx27.h"
|
||||
#include "ulpi.h"
|
||||
|
||||
@ -35,6 +35,7 @@
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx35.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx35.h"
|
||||
#include "ulpi.h"
|
||||
|
||||
@ -20,7 +20,7 @@ static void __init vf610_init_machine(void)
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static const char *vf610_dt_compat[] __initconst = {
|
||||
static const char * const vf610_dt_compat[] __initconst = {
|
||||
"fsl,vf610",
|
||||
NULL,
|
||||
};
|
||||
|
||||
@ -34,6 +34,7 @@
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx35.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx35.h"
|
||||
|
||||
|
||||
@ -1,155 +0,0 @@
|
||||
/*
|
||||
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*
|
||||
* Create static mapping between physical to virtual memory.
|
||||
*/
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "devices/devices-common.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-v3.h"
|
||||
|
||||
/*
|
||||
* Define the MX51 memory map.
|
||||
*/
|
||||
static struct map_desc mx51_io_desc[] __initdata = {
|
||||
imx_map_entry(MX51, TZIC, MT_DEVICE),
|
||||
imx_map_entry(MX51, IRAM, MT_DEVICE),
|
||||
imx_map_entry(MX51, AIPS1, MT_DEVICE),
|
||||
imx_map_entry(MX51, SPBA0, MT_DEVICE),
|
||||
imx_map_entry(MX51, AIPS2, MT_DEVICE),
|
||||
};
|
||||
|
||||
/*
|
||||
* Define the MX53 memory map.
|
||||
*/
|
||||
static struct map_desc mx53_io_desc[] __initdata = {
|
||||
imx_map_entry(MX53, TZIC, MT_DEVICE),
|
||||
imx_map_entry(MX53, AIPS1, MT_DEVICE),
|
||||
imx_map_entry(MX53, SPBA0, MT_DEVICE),
|
||||
imx_map_entry(MX53, AIPS2, MT_DEVICE),
|
||||
};
|
||||
|
||||
/*
|
||||
* This function initializes the memory map. It is called during the
|
||||
* system startup to create static physical to virtual memory mappings
|
||||
* for the IO modules.
|
||||
*/
|
||||
void __init mx51_map_io(void)
|
||||
{
|
||||
iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
|
||||
}
|
||||
|
||||
void __init mx53_map_io(void)
|
||||
{
|
||||
iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
|
||||
}
|
||||
|
||||
/*
|
||||
* The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
|
||||
* the Freescale marketing division. However this did not remove the
|
||||
* hardware from the chip which still needs to be configured for proper
|
||||
* IPU support.
|
||||
*/
|
||||
static void __init imx51_ipu_mipi_setup(void)
|
||||
{
|
||||
void __iomem *hsc_addr;
|
||||
hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR);
|
||||
|
||||
/* setup MIPI module to legacy mode */
|
||||
__raw_writel(0xf00, hsc_addr);
|
||||
|
||||
/* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
|
||||
__raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
|
||||
hsc_addr + 0x800);
|
||||
}
|
||||
|
||||
void __init imx51_init_early(void)
|
||||
{
|
||||
imx51_ipu_mipi_setup();
|
||||
mxc_set_cpu_type(MXC_CPU_MX51);
|
||||
mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
|
||||
imx_src_init();
|
||||
}
|
||||
|
||||
void __init imx53_init_early(void)
|
||||
{
|
||||
mxc_set_cpu_type(MXC_CPU_MX53);
|
||||
imx_src_init();
|
||||
}
|
||||
|
||||
void __init mx51_init_irq(void)
|
||||
{
|
||||
tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
|
||||
}
|
||||
|
||||
void __init mx53_init_irq(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
void __iomem *base;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx53-tzic");
|
||||
base = of_iomap(np, 0);
|
||||
WARN_ON(!base);
|
||||
|
||||
tzic_init_irq(base);
|
||||
}
|
||||
|
||||
static struct sdma_platform_data imx51_sdma_pdata __initdata = {
|
||||
.fw_name = "sdma-imx51.bin",
|
||||
};
|
||||
|
||||
static const struct resource imx51_audmux_res[] __initconst = {
|
||||
DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
|
||||
};
|
||||
|
||||
void __init imx51_soc_init(void)
|
||||
{
|
||||
mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
|
||||
mxc_device_init();
|
||||
|
||||
/* i.mx51 has the i.mx35 type gpio */
|
||||
mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
|
||||
mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
|
||||
mxc_register_gpio("imx35-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
|
||||
mxc_register_gpio("imx35-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
|
||||
/* i.mx51 has the i.mx35 type sdma */
|
||||
imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
|
||||
|
||||
/* Setup AIPS registers */
|
||||
imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
|
||||
imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
|
||||
|
||||
/* i.mx51 has the i.mx31 type audmux */
|
||||
platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
|
||||
ARRAY_SIZE(imx51_audmux_res));
|
||||
}
|
||||
|
||||
void __init imx51_init_late(void)
|
||||
{
|
||||
mx51_neon_fixup();
|
||||
imx5_pm_init();
|
||||
}
|
||||
|
||||
void __init imx53_init_late(void)
|
||||
{
|
||||
imx5_pm_init();
|
||||
}
|
||||
@ -1,18 +0,0 @@
|
||||
/*
|
||||
* Exported ksyms of ARCH_MX1
|
||||
*
|
||||
* Copyright (C) 2008, Darius Augulis <augulis.darius@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <linux/platform_data/camera-mx1.h>
|
||||
|
||||
/* IMX camera FIQ handler */
|
||||
EXPORT_SYMBOL(mx1_camera_sof_fiq_start);
|
||||
EXPORT_SYMBOL(mx1_camera_sof_fiq_end);
|
||||
@ -1,35 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
|
||||
*
|
||||
* Based on linux/arch/arm/lib/floppydma.S
|
||||
* Copyright (C) 1995, 1996 Russell King
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/assembler.h>
|
||||
|
||||
.text
|
||||
.global mx1_camera_sof_fiq_end
|
||||
.global mx1_camera_sof_fiq_start
|
||||
mx1_camera_sof_fiq_start:
|
||||
@ enable dma
|
||||
ldr r12, [r9]
|
||||
orr r12, r12, #0x00000001
|
||||
str r12, [r9]
|
||||
@ unmask DMA interrupt
|
||||
ldr r12, [r8]
|
||||
bic r12, r12, r13
|
||||
str r12, [r8]
|
||||
@ disable SOF interrupt
|
||||
ldr r12, [r10]
|
||||
bic r12, r12, #0x00010000
|
||||
str r12, [r10]
|
||||
@ clear SOF flag
|
||||
mov r12, #0x00010000
|
||||
str r12, [r11]
|
||||
@ return from FIQ
|
||||
subs pc, lr, #4
|
||||
mx1_camera_sof_fiq_end:
|
||||
@ -24,6 +24,7 @@
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx31.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx3.h"
|
||||
#include "ulpi.h"
|
||||
@ -213,10 +214,8 @@ static int __init devboard_usbh1_init(void)
|
||||
usbh1_pdata.otg = phy;
|
||||
|
||||
pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
|
||||
if (IS_ERR(pdev))
|
||||
return PTR_ERR(pdev);
|
||||
|
||||
return 0;
|
||||
return PTR_ERR_OR_ZERO(pdev);
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -28,6 +28,7 @@
|
||||
|
||||
#include "common.h"
|
||||
#include "devices-imx31.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx3.h"
|
||||
#include "ulpi.h"
|
||||
@ -327,10 +328,8 @@ static int __init marxbot_usbh1_init(void)
|
||||
usbh1_pdata.otg = phy;
|
||||
|
||||
pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
|
||||
if (IS_ERR(pdev))
|
||||
return PTR_ERR(pdev);
|
||||
|
||||
return 0;
|
||||
return PTR_ERR_OR_ZERO(pdev);
|
||||
}
|
||||
|
||||
static const struct fsl_usb2_platform_data usb_pdata __initconst = {
|
||||
|
||||
@ -28,6 +28,7 @@
|
||||
#include "board-mx31moboard.h"
|
||||
#include "common.h"
|
||||
#include "devices-imx31.h"
|
||||
#include "ehci.h"
|
||||
#include "hardware.h"
|
||||
#include "iomux-mx3.h"
|
||||
#include "ulpi.h"
|
||||
@ -141,10 +142,8 @@ static int __init smartbot_otg_host_init(void)
|
||||
return -ENODEV;
|
||||
|
||||
pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata);
|
||||
if (IS_ERR(pdev))
|
||||
return PTR_ERR(pdev);
|
||||
|
||||
return 0;
|
||||
return PTR_ERR_OR_ZERO(pdev);
|
||||
}
|
||||
#else
|
||||
static inline int smartbot_otg_host_init(void) { return 0; }
|
||||
|
||||
@ -1,346 +0,0 @@
|
||||
#ifndef __MACH_MX51_H__
|
||||
#define __MACH_MX51_H__
|
||||
|
||||
/*
|
||||
* IROM
|
||||
*/
|
||||
#define MX51_IROM_BASE_ADDR 0x0
|
||||
#define MX51_IROM_SIZE SZ_64K
|
||||
|
||||
/*
|
||||
* IRAM
|
||||
*/
|
||||
#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */
|
||||
#define MX51_IRAM_PARTITIONS 16
|
||||
#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
|
||||
|
||||
#define MX51_GPU_BASE_ADDR 0x20000000
|
||||
#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
|
||||
#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
|
||||
|
||||
/*
|
||||
* SPBA global module enabled #0
|
||||
*/
|
||||
#define MX51_SPBA0_BASE_ADDR 0x70000000
|
||||
#define MX51_SPBA0_SIZE SZ_1M
|
||||
|
||||
#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
|
||||
#define MX51_ESDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000)
|
||||
#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000)
|
||||
#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000)
|
||||
#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000)
|
||||
#define MX51_ESDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000)
|
||||
#define MX51_ESDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000)
|
||||
#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000)
|
||||
#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000)
|
||||
#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000)
|
||||
#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000)
|
||||
#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000)
|
||||
|
||||
/*
|
||||
* AIPS 1
|
||||
*/
|
||||
#define MX51_AIPS1_BASE_ADDR 0x73f00000
|
||||
#define MX51_AIPS1_SIZE SZ_1M
|
||||
|
||||
#define MX51_USB_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000)
|
||||
#define MX51_USB_OTG_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0000)
|
||||
#define MX51_USB_HS1_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0200)
|
||||
#define MX51_USB_HS2_BASE_ADDR (MX51_USB_BASE_ADDR + 0x0400)
|
||||
#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000)
|
||||
#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000)
|
||||
#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000)
|
||||
#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000)
|
||||
#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000)
|
||||
#define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000)
|
||||
#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000)
|
||||
#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000)
|
||||
#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000)
|
||||
#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000)
|
||||
#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000)
|
||||
#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000)
|
||||
#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000)
|
||||
#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000)
|
||||
#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000)
|
||||
#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000)
|
||||
#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000)
|
||||
#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000)
|
||||
#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000)
|
||||
|
||||
/*
|
||||
* AIPS 2
|
||||
*/
|
||||
#define MX51_AIPS2_BASE_ADDR 0x83f00000
|
||||
#define MX51_AIPS2_SIZE SZ_1M
|
||||
|
||||
#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000)
|
||||
#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000)
|
||||
#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000)
|
||||
#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000)
|
||||
#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000)
|
||||
#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000)
|
||||
#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000)
|
||||
#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000)
|
||||
#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000)
|
||||
#define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000)
|
||||
#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000)
|
||||
#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000)
|
||||
#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000)
|
||||
#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000)
|
||||
#define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000)
|
||||
#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000)
|
||||
#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000)
|
||||
#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000)
|
||||
#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000)
|
||||
#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000)
|
||||
#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000)
|
||||
#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000)
|
||||
#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000)
|
||||
#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00)
|
||||
#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000)
|
||||
#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000)
|
||||
#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000)
|
||||
#define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000)
|
||||
#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000)
|
||||
#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000)
|
||||
#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000)
|
||||
#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000)
|
||||
|
||||
#define MX51_CSD0_BASE_ADDR 0x90000000
|
||||
#define MX51_CSD1_BASE_ADDR 0xa0000000
|
||||
#define MX51_CS0_BASE_ADDR 0xb0000000
|
||||
#define MX51_CS1_BASE_ADDR 0xb8000000
|
||||
#define MX51_CS2_BASE_ADDR 0xc0000000
|
||||
#define MX51_CS3_BASE_ADDR 0xc8000000
|
||||
#define MX51_CS4_BASE_ADDR 0xcc000000
|
||||
#define MX51_CS5_BASE_ADDR 0xce000000
|
||||
|
||||
/*
|
||||
* NFC
|
||||
*/
|
||||
#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* NAND flash AXI */
|
||||
#define MX51_NFC_AXI_SIZE SZ_64K
|
||||
|
||||
#define MX51_GPU2D_BASE_ADDR 0xd0000000
|
||||
#define MX51_TZIC_BASE_ADDR 0xe0000000
|
||||
#define MX51_TZIC_SIZE SZ_16K
|
||||
|
||||
#define MX51_IO_P2V(x) IMX_IO_P2V(x)
|
||||
#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x))
|
||||
|
||||
/*
|
||||
* defines for SPBA modules
|
||||
*/
|
||||
#define MX51_SPBA_SDHC1 0x04
|
||||
#define MX51_SPBA_SDHC2 0x08
|
||||
#define MX51_SPBA_UART3 0x0c
|
||||
#define MX51_SPBA_CSPI1 0x10
|
||||
#define MX51_SPBA_SSI2 0x14
|
||||
#define MX51_SPBA_SDHC3 0x20
|
||||
#define MX51_SPBA_SDHC4 0x24
|
||||
#define MX51_SPBA_SPDIF 0x28
|
||||
#define MX51_SPBA_ATA 0x30
|
||||
#define MX51_SPBA_SLIM 0x34
|
||||
#define MX51_SPBA_HSI2C 0x38
|
||||
#define MX51_SPBA_CTRL 0x3c
|
||||
|
||||
/*
|
||||
* Defines for modules using static and dynamic DMA channels
|
||||
*/
|
||||
#define MX51_MXC_DMA_CHANNEL_IRAM 30
|
||||
#define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#ifdef CONFIG_SDMA_IRAM
|
||||
#define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1)
|
||||
#else /*CONFIG_SDMA_IRAM */
|
||||
#define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#endif /*CONFIG_SDMA_IRAM */
|
||||
#define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
|
||||
#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
|
||||
|
||||
#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
|
||||
|
||||
/*
|
||||
* DMA request assignments
|
||||
*/
|
||||
#define MX51_DMA_REQ_VPU 0
|
||||
#define MX51_DMA_REQ_GPC 1
|
||||
#define MX51_DMA_REQ_ATA_RX 2
|
||||
#define MX51_DMA_REQ_ATA_TX 3
|
||||
#define MX51_DMA_REQ_ATA_TX_END 4
|
||||
#define MX51_DMA_REQ_SLIM_B 5
|
||||
#define MX51_DMA_REQ_CSPI1_RX 6
|
||||
#define MX51_DMA_REQ_CSPI1_TX 7
|
||||
#define MX51_DMA_REQ_CSPI2_RX 8
|
||||
#define MX51_DMA_REQ_CSPI2_TX 9
|
||||
#define MX51_DMA_REQ_HS_I2C_TX 10
|
||||
#define MX51_DMA_REQ_HS_I2C_RX 11
|
||||
#define MX51_DMA_REQ_FIRI_RX 12
|
||||
#define MX51_DMA_REQ_FIRI_TX 13
|
||||
#define MX51_DMA_REQ_EXTREQ1 14
|
||||
#define MX51_DMA_REQ_GPU 15
|
||||
#define MX51_DMA_REQ_UART2_RX 16
|
||||
#define MX51_DMA_REQ_UART2_TX 17
|
||||
#define MX51_DMA_REQ_UART1_RX 18
|
||||
#define MX51_DMA_REQ_UART1_TX 19
|
||||
#define MX51_DMA_REQ_SDHC1 20
|
||||
#define MX51_DMA_REQ_SDHC2 21
|
||||
#define MX51_DMA_REQ_SSI2_RX1 22
|
||||
#define MX51_DMA_REQ_SSI2_TX1 23
|
||||
#define MX51_DMA_REQ_SSI2_RX0 24
|
||||
#define MX51_DMA_REQ_SSI2_TX0 25
|
||||
#define MX51_DMA_REQ_SSI1_RX1 26
|
||||
#define MX51_DMA_REQ_SSI1_TX1 27
|
||||
#define MX51_DMA_REQ_SSI1_RX0 28
|
||||
#define MX51_DMA_REQ_SSI1_TX0 29
|
||||
#define MX51_DMA_REQ_EMI_RD 30
|
||||
#define MX51_DMA_REQ_CTI2_0 31
|
||||
#define MX51_DMA_REQ_EMI_WR 32
|
||||
#define MX51_DMA_REQ_CTI2_1 33
|
||||
#define MX51_DMA_REQ_EPIT2 34
|
||||
#define MX51_DMA_REQ_SSI3_RX1 35
|
||||
#define MX51_DMA_REQ_IPU 36
|
||||
#define MX51_DMA_REQ_SSI3_TX1 37
|
||||
#define MX51_DMA_REQ_CSPI_RX 38
|
||||
#define MX51_DMA_REQ_CSPI_TX 39
|
||||
#define MX51_DMA_REQ_SDHC3 40
|
||||
#define MX51_DMA_REQ_SDHC4 41
|
||||
#define MX51_DMA_REQ_SLIM_B_TX 42
|
||||
#define MX51_DMA_REQ_UART3_RX 43
|
||||
#define MX51_DMA_REQ_UART3_TX 44
|
||||
#define MX51_DMA_REQ_SPDIF 45
|
||||
#define MX51_DMA_REQ_SSI3_RX0 46
|
||||
#define MX51_DMA_REQ_SSI3_TX0 47
|
||||
|
||||
/*
|
||||
* Interrupt numbers
|
||||
*/
|
||||
#include <asm/irq.h>
|
||||
#define MX51_INT_BASE (NR_IRQS_LEGACY + 0)
|
||||
#define MX51_INT_RESV0 (NR_IRQS_LEGACY + 0)
|
||||
#define MX51_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
|
||||
#define MX51_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
|
||||
#define MX51_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
|
||||
#define MX51_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
|
||||
#define MX51_INT_RESV5 (NR_IRQS_LEGACY + 5)
|
||||
#define MX51_INT_SDMA (NR_IRQS_LEGACY + 6)
|
||||
#define MX51_INT_IOMUX (NR_IRQS_LEGACY + 7)
|
||||
#define MX51_INT_NFC (NR_IRQS_LEGACY + 8)
|
||||
#define MX51_INT_VPU (NR_IRQS_LEGACY + 9)
|
||||
#define MX51_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
|
||||
#define MX51_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
|
||||
#define MX51_INT_GPU (NR_IRQS_LEGACY + 12)
|
||||
#define MX51_INT_RESV13 (NR_IRQS_LEGACY + 13)
|
||||
#define MX51_INT_USB_HS1 (NR_IRQS_LEGACY + 14)
|
||||
#define MX51_INT_EMI (NR_IRQS_LEGACY + 15)
|
||||
#define MX51_INT_USB_HS2 (NR_IRQS_LEGACY + 16)
|
||||
#define MX51_INT_USB_HS3 (NR_IRQS_LEGACY + 17)
|
||||
#define MX51_INT_USB_OTG (NR_IRQS_LEGACY + 18)
|
||||
#define MX51_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
|
||||
#define MX51_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
|
||||
#define MX51_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
|
||||
#define MX51_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
|
||||
#define MX51_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
|
||||
#define MX51_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
|
||||
#define MX51_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
|
||||
#define MX51_INT_RTIC (NR_IRQS_LEGACY + 26)
|
||||
#define MX51_INT_CSU (NR_IRQS_LEGACY + 27)
|
||||
#define MX51_INT_SLIM_B (NR_IRQS_LEGACY + 28)
|
||||
#define MX51_INT_SSI1 (NR_IRQS_LEGACY + 29)
|
||||
#define MX51_INT_SSI2 (NR_IRQS_LEGACY + 30)
|
||||
#define MX51_INT_UART1 (NR_IRQS_LEGACY + 31)
|
||||
#define MX51_INT_UART2 (NR_IRQS_LEGACY + 32)
|
||||
#define MX51_INT_UART3 (NR_IRQS_LEGACY + 33)
|
||||
#define MX51_INT_RESV34 (NR_IRQS_LEGACY + 34)
|
||||
#define MX51_INT_RESV35 (NR_IRQS_LEGACY + 35)
|
||||
#define MX51_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
|
||||
#define MX51_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
|
||||
#define MX51_INT_CSPI (NR_IRQS_LEGACY + 38)
|
||||
#define MX51_INT_GPT (NR_IRQS_LEGACY + 39)
|
||||
#define MX51_INT_EPIT1 (NR_IRQS_LEGACY + 40)
|
||||
#define MX51_INT_EPIT2 (NR_IRQS_LEGACY + 41)
|
||||
#define MX51_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
|
||||
#define MX51_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
|
||||
#define MX51_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
|
||||
#define MX51_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
|
||||
#define MX51_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
|
||||
#define MX51_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
|
||||
#define MX51_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
|
||||
#define MX51_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
|
||||
#define MX51_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
|
||||
#define MX51_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
|
||||
#define MX51_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
|
||||
#define MX51_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
|
||||
#define MX51_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
|
||||
#define MX51_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
|
||||
#define MX51_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
|
||||
#define MX51_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
|
||||
#define MX51_INT_WDOG1 (NR_IRQS_LEGACY + 58)
|
||||
#define MX51_INT_WDOG2 (NR_IRQS_LEGACY + 59)
|
||||
#define MX51_INT_KPP (NR_IRQS_LEGACY + 60)
|
||||
#define MX51_INT_PWM1 (NR_IRQS_LEGACY + 61)
|
||||
#define MX51_INT_I2C1 (NR_IRQS_LEGACY + 62)
|
||||
#define MX51_INT_I2C2 (NR_IRQS_LEGACY + 63)
|
||||
#define MX51_INT_HS_I2C (NR_IRQS_LEGACY + 64)
|
||||
#define MX51_INT_RESV65 (NR_IRQS_LEGACY + 65)
|
||||
#define MX51_INT_RESV66 (NR_IRQS_LEGACY + 66)
|
||||
#define MX51_INT_SIM_IPB (NR_IRQS_LEGACY + 67)
|
||||
#define MX51_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
|
||||
#define MX51_INT_IIM (NR_IRQS_LEGACY + 69)
|
||||
#define MX51_INT_ATA (NR_IRQS_LEGACY + 70)
|
||||
#define MX51_INT_CCM1 (NR_IRQS_LEGACY + 71)
|
||||
#define MX51_INT_CCM2 (NR_IRQS_LEGACY + 72)
|
||||
#define MX51_INT_GPC1 (NR_IRQS_LEGACY + 73)
|
||||
#define MX51_INT_GPC2 (NR_IRQS_LEGACY + 74)
|
||||
#define MX51_INT_SRC (NR_IRQS_LEGACY + 75)
|
||||
#define MX51_INT_NM (NR_IRQS_LEGACY + 76)
|
||||
#define MX51_INT_PMU (NR_IRQS_LEGACY + 77)
|
||||
#define MX51_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
|
||||
#define MX51_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
|
||||
#define MX51_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
|
||||
#define MX51_INT_MCG_ERR (NR_IRQS_LEGACY + 81)
|
||||
#define MX51_INT_MCG_TMR (NR_IRQS_LEGACY + 82)
|
||||
#define MX51_INT_MCG_FUNC (NR_IRQS_LEGACY + 83)
|
||||
#define MX51_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
|
||||
#define MX51_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
|
||||
#define MX51_INT_RESV86 (NR_IRQS_LEGACY + 86)
|
||||
#define MX51_INT_FEC (NR_IRQS_LEGACY + 87)
|
||||
#define MX51_INT_OWIRE (NR_IRQS_LEGACY + 88)
|
||||
#define MX51_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
|
||||
#define MX51_INT_SJC (NR_IRQS_LEGACY + 90)
|
||||
#define MX51_INT_SPDIF (NR_IRQS_LEGACY + 91)
|
||||
#define MX51_INT_TVE (NR_IRQS_LEGACY + 92)
|
||||
#define MX51_INT_FIRI (NR_IRQS_LEGACY + 93)
|
||||
#define MX51_INT_PWM2 (NR_IRQS_LEGACY + 94)
|
||||
#define MX51_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
|
||||
#define MX51_INT_SSI3 (NR_IRQS_LEGACY + 96)
|
||||
#define MX51_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
|
||||
#define MX51_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
|
||||
#define MX51_INT_SMC_RX (NR_IRQS_LEGACY + 99)
|
||||
#define MX51_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
|
||||
#define MX51_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
|
||||
#define MX51_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
|
||||
|
||||
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
|
||||
extern int mx51_revision(void);
|
||||
extern void mx51_display_revision(void);
|
||||
#endif
|
||||
|
||||
#endif /* ifndef __MACH_MX51_H__ */
|
||||
@ -1,342 +0,0 @@
|
||||
#ifndef __MACH_MX53_H__
|
||||
#define __MACH_MX53_H__
|
||||
|
||||
/*
|
||||
* IROM
|
||||
*/
|
||||
#define MX53_IROM_BASE_ADDR 0x0
|
||||
#define MX53_IROM_SIZE SZ_64K
|
||||
|
||||
/* TZIC */
|
||||
#define MX53_TZIC_BASE_ADDR 0x0FFFC000
|
||||
#define MX53_TZIC_SIZE SZ_16K
|
||||
|
||||
/*
|
||||
* AHCI SATA
|
||||
*/
|
||||
#define MX53_SATA_BASE_ADDR 0x10000000
|
||||
|
||||
/*
|
||||
* NFC
|
||||
*/
|
||||
#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */
|
||||
#define MX53_NFC_AXI_SIZE SZ_64K
|
||||
|
||||
/*
|
||||
* IRAM
|
||||
*/
|
||||
#define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */
|
||||
#define MX53_IRAM_PARTITIONS 16
|
||||
#define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */
|
||||
|
||||
/*
|
||||
* Graphics Memory of GPU
|
||||
*/
|
||||
#define MX53_IPU_CTRL_BASE_ADDR 0x18000000
|
||||
#define MX53_GPU2D_BASE_ADDR 0x20000000
|
||||
#define MX53_GPU_BASE_ADDR 0x30000000
|
||||
#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000
|
||||
|
||||
#define MX53_DEBUG_BASE_ADDR 0x40000000
|
||||
#define MX53_DEBUG_SIZE SZ_1M
|
||||
#define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000)
|
||||
#define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000)
|
||||
#define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000)
|
||||
#define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000)
|
||||
#define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000)
|
||||
#define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000)
|
||||
#define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000)
|
||||
#define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000)
|
||||
|
||||
/*
|
||||
* SPBA global module enabled #0
|
||||
*/
|
||||
#define MX53_SPBA0_BASE_ADDR 0x50000000
|
||||
#define MX53_SPBA0_SIZE SZ_1M
|
||||
|
||||
#define MX53_ESDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000)
|
||||
#define MX53_ESDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000)
|
||||
#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000)
|
||||
#define MX53_ECSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000)
|
||||
#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000)
|
||||
#define MX53_ESDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000)
|
||||
#define MX53_ESDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000)
|
||||
#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000)
|
||||
#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000)
|
||||
#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000)
|
||||
#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000)
|
||||
#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000)
|
||||
#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000)
|
||||
|
||||
/*
|
||||
* AIPS 1
|
||||
*/
|
||||
#define MX53_AIPS1_BASE_ADDR 0x53F00000
|
||||
#define MX53_AIPS1_SIZE SZ_1M
|
||||
|
||||
#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000)
|
||||
#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000)
|
||||
#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000)
|
||||
#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000)
|
||||
#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000)
|
||||
#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000)
|
||||
#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000)
|
||||
#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000)
|
||||
#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000)
|
||||
#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000)
|
||||
#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000)
|
||||
#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000)
|
||||
#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000)
|
||||
#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000)
|
||||
#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000)
|
||||
#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000)
|
||||
#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000)
|
||||
#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000)
|
||||
#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000)
|
||||
#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000)
|
||||
#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000)
|
||||
#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000)
|
||||
#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000)
|
||||
#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000)
|
||||
#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000)
|
||||
#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000)
|
||||
|
||||
/*
|
||||
* AIPS 2
|
||||
*/
|
||||
#define MX53_AIPS2_BASE_ADDR 0x63F00000
|
||||
#define MX53_AIPS2_SIZE SZ_1M
|
||||
|
||||
#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000)
|
||||
#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000)
|
||||
#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000)
|
||||
#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000)
|
||||
#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000)
|
||||
#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000)
|
||||
#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000)
|
||||
#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000)
|
||||
#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000)
|
||||
#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000)
|
||||
#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000)
|
||||
#define MX53_ECSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000)
|
||||
#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000)
|
||||
#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000)
|
||||
#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000)
|
||||
#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000)
|
||||
#define MX53_CSPI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000)
|
||||
#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000)
|
||||
#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000)
|
||||
#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000)
|
||||
#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000)
|
||||
#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000)
|
||||
#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000)
|
||||
#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000)
|
||||
#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000)
|
||||
#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000)
|
||||
#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00)
|
||||
#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000)
|
||||
#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000)
|
||||
#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000)
|
||||
#define MX53_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000)
|
||||
#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000)
|
||||
#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000)
|
||||
#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000)
|
||||
#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000)
|
||||
|
||||
/*
|
||||
* Memory regions and CS
|
||||
*/
|
||||
#define MX53_CSD0_BASE_ADDR 0x70000000
|
||||
#define MX53_CSD1_BASE_ADDR 0xB0000000
|
||||
#define MX53_CS0_BASE_ADDR 0xF0000000
|
||||
#define MX53_CS1_32MB_BASE_ADDR 0xF2000000
|
||||
#define MX53_CS1_64MB_BASE_ADDR 0xF4000000
|
||||
#define MX53_CS2_64MB_BASE_ADDR 0xF4000000
|
||||
#define MX53_CS2_96MB_BASE_ADDR 0xF6000000
|
||||
#define MX53_CS3_BASE_ADDR 0xF6000000
|
||||
|
||||
#define MX53_IO_P2V(x) IMX_IO_P2V(x)
|
||||
#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x))
|
||||
|
||||
/*
|
||||
* defines for SPBA modules
|
||||
*/
|
||||
#define MX53_SPBA_SDHC1 0x04
|
||||
#define MX53_SPBA_SDHC2 0x08
|
||||
#define MX53_SPBA_UART3 0x0C
|
||||
#define MX53_SPBA_CSPI1 0x10
|
||||
#define MX53_SPBA_SSI2 0x14
|
||||
#define MX53_SPBA_SDHC3 0x20
|
||||
#define MX53_SPBA_SDHC4 0x24
|
||||
#define MX53_SPBA_SPDIF 0x28
|
||||
#define MX53_SPBA_ATA 0x30
|
||||
#define MX53_SPBA_SLIM 0x34
|
||||
#define MX53_SPBA_HSI2C 0x38
|
||||
#define MX53_SPBA_CTRL 0x3C
|
||||
|
||||
/*
|
||||
* DMA request assignments
|
||||
*/
|
||||
#define MX53_DMA_REQ_SSI3_TX0 47
|
||||
#define MX53_DMA_REQ_SSI3_RX0 46
|
||||
#define MX53_DMA_REQ_SSI3_TX1 45
|
||||
#define MX53_DMA_REQ_SSI3_RX1 44
|
||||
#define MX53_DMA_REQ_UART3_TX 43
|
||||
#define MX53_DMA_REQ_UART3_RX 42
|
||||
#define MX53_DMA_REQ_ESAI_TX 41
|
||||
#define MX53_DMA_REQ_ESAI_RX 40
|
||||
#define MX53_DMA_REQ_CSPI_TX 39
|
||||
#define MX53_DMA_REQ_CSPI_RX 38
|
||||
#define MX53_DMA_REQ_ASRC_DMA6 37
|
||||
#define MX53_DMA_REQ_ASRC_DMA5 36
|
||||
#define MX53_DMA_REQ_ASRC_DMA4 35
|
||||
#define MX53_DMA_REQ_ASRC_DMA3 34
|
||||
#define MX53_DMA_REQ_ASRC_DMA2 33
|
||||
#define MX53_DMA_REQ_ASRC_DMA1 32
|
||||
#define MX53_DMA_REQ_EMI_WR 31
|
||||
#define MX53_DMA_REQ_EMI_RD 30
|
||||
#define MX53_DMA_REQ_SSI1_TX0 29
|
||||
#define MX53_DMA_REQ_SSI1_RX0 28
|
||||
#define MX53_DMA_REQ_SSI1_TX1 27
|
||||
#define MX53_DMA_REQ_SSI1_RX1 26
|
||||
#define MX53_DMA_REQ_SSI2_TX0 25
|
||||
#define MX53_DMA_REQ_SSI2_RX0 24
|
||||
#define MX53_DMA_REQ_SSI2_TX1 23
|
||||
#define MX53_DMA_REQ_SSI2_RX1 22
|
||||
#define MX53_DMA_REQ_I2C2_SDHC2 21
|
||||
#define MX53_DMA_REQ_I2C1_SDHC1 20
|
||||
#define MX53_DMA_REQ_UART1_TX 19
|
||||
#define MX53_DMA_REQ_UART1_RX 18
|
||||
#define MX53_DMA_REQ_UART5_TX 17
|
||||
#define MX53_DMA_REQ_UART5_RX 16
|
||||
#define MX53_DMA_REQ_SPDIF_TX 15
|
||||
#define MX53_DMA_REQ_SPDIF_RX 14
|
||||
#define MX53_DMA_REQ_UART2_FIRI_TX 13
|
||||
#define MX53_DMA_REQ_UART2_FIRI_RX 12
|
||||
#define MX53_DMA_REQ_SDHC4 11
|
||||
#define MX53_DMA_REQ_I2C3_SDHC3 10
|
||||
#define MX53_DMA_REQ_CSPI2_TX 9
|
||||
#define MX53_DMA_REQ_CSPI2_RX 8
|
||||
#define MX53_DMA_REQ_CSPI1_TX 7
|
||||
#define MX53_DMA_REQ_CSPI1_RX 6
|
||||
#define MX53_DMA_REQ_IPU 5
|
||||
#define MX53_DMA_REQ_ATA_TX_END 4
|
||||
#define MX53_DMA_REQ_ATA_UART4_TX 3
|
||||
#define MX53_DMA_REQ_ATA_UART4_RX 2
|
||||
#define MX53_DMA_REQ_GPC 1
|
||||
#define MX53_DMA_REQ_VPU 0
|
||||
|
||||
/*
|
||||
* Interrupt numbers
|
||||
*/
|
||||
#include <asm/irq.h>
|
||||
#define MX53_INT_RESV0 (NR_IRQS_LEGACY + 0)
|
||||
#define MX53_INT_ESDHC1 (NR_IRQS_LEGACY + 1)
|
||||
#define MX53_INT_ESDHC2 (NR_IRQS_LEGACY + 2)
|
||||
#define MX53_INT_ESDHC3 (NR_IRQS_LEGACY + 3)
|
||||
#define MX53_INT_ESDHC4 (NR_IRQS_LEGACY + 4)
|
||||
#define MX53_INT_DAP (NR_IRQS_LEGACY + 5)
|
||||
#define MX53_INT_SDMA (NR_IRQS_LEGACY + 6)
|
||||
#define MX53_INT_IOMUX (NR_IRQS_LEGACY + 7)
|
||||
#define MX53_INT_NFC (NR_IRQS_LEGACY + 8)
|
||||
#define MX53_INT_VPU (NR_IRQS_LEGACY + 9)
|
||||
#define MX53_INT_IPU_ERR (NR_IRQS_LEGACY + 10)
|
||||
#define MX53_INT_IPU_SYN (NR_IRQS_LEGACY + 11)
|
||||
#define MX53_INT_GPU (NR_IRQS_LEGACY + 12)
|
||||
#define MX53_INT_UART4 (NR_IRQS_LEGACY + 13)
|
||||
#define MX53_INT_USB_H1 (NR_IRQS_LEGACY + 14)
|
||||
#define MX53_INT_EMI (NR_IRQS_LEGACY + 15)
|
||||
#define MX53_INT_USB_H2 (NR_IRQS_LEGACY + 16)
|
||||
#define MX53_INT_USB_H3 (NR_IRQS_LEGACY + 17)
|
||||
#define MX53_INT_USB_OTG (NR_IRQS_LEGACY + 18)
|
||||
#define MX53_INT_SAHARA_H0 (NR_IRQS_LEGACY + 19)
|
||||
#define MX53_INT_SAHARA_H1 (NR_IRQS_LEGACY + 20)
|
||||
#define MX53_INT_SCC_SMN (NR_IRQS_LEGACY + 21)
|
||||
#define MX53_INT_SCC_STZ (NR_IRQS_LEGACY + 22)
|
||||
#define MX53_INT_SCC_SCM (NR_IRQS_LEGACY + 23)
|
||||
#define MX53_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
|
||||
#define MX53_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
|
||||
#define MX53_INT_RTIC (NR_IRQS_LEGACY + 26)
|
||||
#define MX53_INT_CSU (NR_IRQS_LEGACY + 27)
|
||||
#define MX53_INT_SATA (NR_IRQS_LEGACY + 28)
|
||||
#define MX53_INT_SSI1 (NR_IRQS_LEGACY + 29)
|
||||
#define MX53_INT_SSI2 (NR_IRQS_LEGACY + 30)
|
||||
#define MX53_INT_UART1 (NR_IRQS_LEGACY + 31)
|
||||
#define MX53_INT_UART2 (NR_IRQS_LEGACY + 32)
|
||||
#define MX53_INT_UART3 (NR_IRQS_LEGACY + 33)
|
||||
#define MX53_INT_RTC (NR_IRQS_LEGACY + 34)
|
||||
#define MX53_INT_PTP (NR_IRQS_LEGACY + 35)
|
||||
#define MX53_INT_ECSPI1 (NR_IRQS_LEGACY + 36)
|
||||
#define MX53_INT_ECSPI2 (NR_IRQS_LEGACY + 37)
|
||||
#define MX53_INT_CSPI (NR_IRQS_LEGACY + 38)
|
||||
#define MX53_INT_GPT (NR_IRQS_LEGACY + 39)
|
||||
#define MX53_INT_EPIT1 (NR_IRQS_LEGACY + 40)
|
||||
#define MX53_INT_EPIT2 (NR_IRQS_LEGACY + 41)
|
||||
#define MX53_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
|
||||
#define MX53_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
|
||||
#define MX53_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
|
||||
#define MX53_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
|
||||
#define MX53_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
|
||||
#define MX53_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
|
||||
#define MX53_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
|
||||
#define MX53_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
|
||||
#define MX53_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
|
||||
#define MX53_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
|
||||
#define MX53_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
|
||||
#define MX53_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
|
||||
#define MX53_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
|
||||
#define MX53_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
|
||||
#define MX53_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
|
||||
#define MX53_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
|
||||
#define MX53_INT_WDOG1 (NR_IRQS_LEGACY + 58)
|
||||
#define MX53_INT_WDOG2 (NR_IRQS_LEGACY + 59)
|
||||
#define MX53_INT_KPP (NR_IRQS_LEGACY + 60)
|
||||
#define MX53_INT_PWM1 (NR_IRQS_LEGACY + 61)
|
||||
#define MX53_INT_I2C1 (NR_IRQS_LEGACY + 62)
|
||||
#define MX53_INT_I2C2 (NR_IRQS_LEGACY + 63)
|
||||
#define MX53_INT_I2C3 (NR_IRQS_LEGACY + 64)
|
||||
#define MX53_INT_MLB (NR_IRQS_LEGACY + 65)
|
||||
#define MX53_INT_ASRC (NR_IRQS_LEGACY + 66)
|
||||
#define MX53_INT_SPDIF (NR_IRQS_LEGACY + 67)
|
||||
#define MX53_INT_SIM_DAT (NR_IRQS_LEGACY + 68)
|
||||
#define MX53_INT_IIM (NR_IRQS_LEGACY + 69)
|
||||
#define MX53_INT_ATA (NR_IRQS_LEGACY + 70)
|
||||
#define MX53_INT_CCM1 (NR_IRQS_LEGACY + 71)
|
||||
#define MX53_INT_CCM2 (NR_IRQS_LEGACY + 72)
|
||||
#define MX53_INT_GPC1 (NR_IRQS_LEGACY + 73)
|
||||
#define MX53_INT_GPC2 (NR_IRQS_LEGACY + 74)
|
||||
#define MX53_INT_SRC (NR_IRQS_LEGACY + 75)
|
||||
#define MX53_INT_NM (NR_IRQS_LEGACY + 76)
|
||||
#define MX53_INT_PMU (NR_IRQS_LEGACY + 77)
|
||||
#define MX53_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
|
||||
#define MX53_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
|
||||
#define MX53_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
|
||||
#define MX53_INT_ESAI (NR_IRQS_LEGACY + 81)
|
||||
#define MX53_INT_CAN1 (NR_IRQS_LEGACY + 82)
|
||||
#define MX53_INT_CAN2 (NR_IRQS_LEGACY + 83)
|
||||
#define MX53_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
|
||||
#define MX53_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
|
||||
#define MX53_INT_UART5 (NR_IRQS_LEGACY + 86)
|
||||
#define MX53_INT_FEC (NR_IRQS_LEGACY + 87)
|
||||
#define MX53_INT_OWIRE (NR_IRQS_LEGACY + 88)
|
||||
#define MX53_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
|
||||
#define MX53_INT_SJC (NR_IRQS_LEGACY + 90)
|
||||
#define MX53_INT_TVE (NR_IRQS_LEGACY + 92)
|
||||
#define MX53_INT_FIRI (NR_IRQS_LEGACY + 93)
|
||||
#define MX53_INT_PWM2 (NR_IRQS_LEGACY + 94)
|
||||
#define MX53_INT_SLIM_EXP (NR_IRQS_LEGACY + 95)
|
||||
#define MX53_INT_SSI3 (NR_IRQS_LEGACY + 96)
|
||||
#define MX53_INT_EMI_BOOT (NR_IRQS_LEGACY + 97)
|
||||
#define MX53_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
|
||||
#define MX53_INT_SMC_RX (NR_IRQS_LEGACY + 99)
|
||||
#define MX53_INT_VPU_IDLE (NR_IRQS_LEGACY + 100)
|
||||
#define MX53_INT_EMI_NFC (NR_IRQS_LEGACY + 101)
|
||||
#define MX53_INT_GPU_IDLE (NR_IRQS_LEGACY + 102)
|
||||
#define MX53_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
|
||||
#define MX53_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
|
||||
#define MX53_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
|
||||
#define MX53_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
|
||||
#define MX53_INT_GPIO7_LOW (NR_IRQS_LEGACY + 107)
|
||||
#define MX53_INT_GPIO7_HIGH (NR_IRQS_LEGACY + 108)
|
||||
|
||||
#endif /* ifndef __MACH_MX53_H__ */
|
||||
@ -154,10 +154,17 @@ extern unsigned int __mxc_cpu_type;
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef CONFIG_SOC_IMX6SL
|
||||
static inline bool cpu_is_imx6sl(void)
|
||||
{
|
||||
return __mxc_cpu_type == MXC_CPU_IMX6SL;
|
||||
}
|
||||
#else
|
||||
static inline bool cpu_is_imx6sl(void)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline bool cpu_is_imx6dl(void)
|
||||
{
|
||||
|
||||
@ -19,9 +19,26 @@
|
||||
|
||||
#include "common.h"
|
||||
#include "cpuidle.h"
|
||||
#include "crm-regs-imx5.h"
|
||||
#include "hardware.h"
|
||||
|
||||
#define MXC_CCM_CLPCR 0x54
|
||||
#define MXC_CCM_CLPCR_LPM_OFFSET 0
|
||||
#define MXC_CCM_CLPCR_LPM_MASK 0x3
|
||||
#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
|
||||
#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
|
||||
#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
|
||||
|
||||
#define MXC_CORTEXA8_PLAT_LPC 0xc
|
||||
#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
|
||||
#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
|
||||
|
||||
#define MXC_SRPG_NEON_SRPGCR 0x280
|
||||
#define MXC_SRPG_ARM_SRPGCR 0x2a0
|
||||
#define MXC_SRPG_EMPGC0_SRPGCR 0x2c0
|
||||
#define MXC_SRPG_EMPGC1_SRPGCR 0x2d0
|
||||
|
||||
#define MXC_SRPGCR_PCR 1
|
||||
|
||||
/*
|
||||
* The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit.
|
||||
* This is also the lowest power state possible without affecting
|
||||
@ -32,6 +49,30 @@
|
||||
*/
|
||||
#define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF
|
||||
|
||||
struct imx5_pm_data {
|
||||
phys_addr_t cortex_addr;
|
||||
phys_addr_t gpc_addr;
|
||||
};
|
||||
|
||||
static const struct imx5_pm_data imx51_pm_data __initconst = {
|
||||
.cortex_addr = 0x83fa0000,
|
||||
.gpc_addr = 0x73fd8000,
|
||||
};
|
||||
|
||||
static const struct imx5_pm_data imx53_pm_data __initconst = {
|
||||
.cortex_addr = 0x63fa0000,
|
||||
.gpc_addr = 0x53fd8000,
|
||||
};
|
||||
|
||||
static void __iomem *ccm_base;
|
||||
static void __iomem *cortex_base;
|
||||
static void __iomem *gpc_base;
|
||||
|
||||
void __init imx5_pm_set_ccm_base(void __iomem *base)
|
||||
{
|
||||
ccm_base = base;
|
||||
}
|
||||
|
||||
/*
|
||||
* set cpu low power mode before WFI instruction. This function is called
|
||||
* mx5 because it can be used for mx51, and mx53.
|
||||
@ -43,12 +84,16 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
|
||||
int stop_mode = 0;
|
||||
|
||||
/* always allow platform to issue a deep sleep mode request */
|
||||
plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) &
|
||||
plat_lpc = __raw_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) &
|
||||
~(MXC_CORTEXA8_PLAT_LPC_DSM);
|
||||
ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK);
|
||||
arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR);
|
||||
empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR);
|
||||
empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR);
|
||||
ccm_clpcr = __raw_readl(ccm_base + MXC_CCM_CLPCR) &
|
||||
~(MXC_CCM_CLPCR_LPM_MASK);
|
||||
arm_srpgcr = __raw_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) &
|
||||
~(MXC_SRPGCR_PCR);
|
||||
empgc0 = __raw_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) &
|
||||
~(MXC_SRPGCR_PCR);
|
||||
empgc1 = __raw_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) &
|
||||
~(MXC_SRPGCR_PCR);
|
||||
|
||||
switch (mode) {
|
||||
case WAIT_CLOCKED:
|
||||
@ -82,17 +127,17 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
|
||||
return;
|
||||
}
|
||||
|
||||
__raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
|
||||
__raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
|
||||
__raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
|
||||
__raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
|
||||
__raw_writel(plat_lpc, cortex_base + MXC_CORTEXA8_PLAT_LPC);
|
||||
__raw_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR);
|
||||
__raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR);
|
||||
__raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR);
|
||||
|
||||
if (stop_mode) {
|
||||
empgc0 |= MXC_SRPGCR_PCR;
|
||||
empgc1 |= MXC_SRPGCR_PCR;
|
||||
|
||||
__raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR);
|
||||
__raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);
|
||||
__raw_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
|
||||
__raw_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
|
||||
}
|
||||
}
|
||||
|
||||
@ -114,8 +159,8 @@ static int mx5_suspend_enter(suspend_state_t state)
|
||||
flush_cache_all();
|
||||
|
||||
/*clear the EMPGC0/1 bits */
|
||||
__raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
|
||||
__raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
|
||||
__raw_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
|
||||
__raw_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
|
||||
}
|
||||
cpu_do_idle();
|
||||
|
||||
@ -149,7 +194,7 @@ static void imx5_pm_idle(void)
|
||||
imx5_cpu_do_idle();
|
||||
}
|
||||
|
||||
static int __init imx5_pm_common_init(void)
|
||||
static int __init imx5_pm_common_init(const struct imx5_pm_data *data)
|
||||
{
|
||||
int ret;
|
||||
struct clk *gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
|
||||
@ -163,15 +208,28 @@ static int __init imx5_pm_common_init(void)
|
||||
|
||||
arm_pm_idle = imx5_pm_idle;
|
||||
|
||||
cortex_base = ioremap(data->cortex_addr, SZ_16K);
|
||||
gpc_base = ioremap(data->gpc_addr, SZ_16K);
|
||||
WARN_ON(!ccm_base || !cortex_base || !gpc_base);
|
||||
|
||||
/* Set the registers to the default cpu idle state. */
|
||||
mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);
|
||||
|
||||
return imx5_cpuidle_init();
|
||||
ret = imx5_cpuidle_init();
|
||||
if (ret)
|
||||
pr_warn("%s: cpuidle init failed %d\n", __func__, ret);
|
||||
|
||||
suspend_set_ops(&mx5_suspend_ops);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __init imx5_pm_init(void)
|
||||
void __init imx51_pm_init(void)
|
||||
{
|
||||
int ret = imx5_pm_common_init();
|
||||
if (!ret)
|
||||
suspend_set_ops(&mx5_suspend_ops);
|
||||
imx5_pm_common_init(&imx51_pm_data);
|
||||
}
|
||||
|
||||
void __init imx53_pm_init(void)
|
||||
{
|
||||
imx5_pm_common_init(&imx53_pm_data);
|
||||
}
|
||||
|
||||
@ -129,6 +129,14 @@ static const u32 imx6sl_mmdc_io_offset[] __initconst = {
|
||||
0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */
|
||||
};
|
||||
|
||||
static const u32 imx6sx_mmdc_io_offset[] __initconst = {
|
||||
0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
|
||||
0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
|
||||
0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
|
||||
0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
|
||||
0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
|
||||
};
|
||||
|
||||
static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
|
||||
.cpu_type = MXC_CPU_IMX6Q,
|
||||
.mmdc_compat = "fsl,imx6q-mmdc",
|
||||
@ -159,6 +167,16 @@ static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
|
||||
.mmdc_io_offset = imx6sl_mmdc_io_offset,
|
||||
};
|
||||
|
||||
static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
|
||||
.cpu_type = MXC_CPU_IMX6SX,
|
||||
.mmdc_compat = "fsl,imx6sx-mmdc",
|
||||
.src_compat = "fsl,imx6sx-src",
|
||||
.iomuxc_compat = "fsl,imx6sx-iomuxc",
|
||||
.gpc_compat = "fsl,imx6sx-gpc",
|
||||
.mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
|
||||
.mmdc_io_offset = imx6sx_mmdc_io_offset,
|
||||
};
|
||||
|
||||
/*
|
||||
* This structure is for passing necessary data for low level ocram
|
||||
* suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
|
||||
@ -181,11 +199,13 @@ struct imx6_cpu_pm_info {
|
||||
u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
|
||||
} __aligned(8);
|
||||
|
||||
void imx6q_set_int_mem_clk_lpm(void)
|
||||
void imx6q_set_int_mem_clk_lpm(bool enable)
|
||||
{
|
||||
u32 val = readl_relaxed(ccm_base + CGPR);
|
||||
|
||||
val |= BM_CGPR_INT_MEM_CLK_LPM;
|
||||
val &= ~BM_CGPR_INT_MEM_CLK_LPM;
|
||||
if (enable)
|
||||
val |= BM_CGPR_INT_MEM_CLK_LPM;
|
||||
writel_relaxed(val, ccm_base + CGPR);
|
||||
}
|
||||
|
||||
@ -254,6 +274,14 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
|
||||
break;
|
||||
case STOP_POWER_ON:
|
||||
val |= 0x2 << BP_CLPCR_LPM;
|
||||
val &= ~BM_CLPCR_VSTBY;
|
||||
val &= ~BM_CLPCR_SBYOS;
|
||||
if (cpu_is_imx6sl())
|
||||
val |= BM_CLPCR_BYPASS_PMIC_READY;
|
||||
if (cpu_is_imx6sl() || cpu_is_imx6sx())
|
||||
val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
|
||||
else
|
||||
val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
|
||||
break;
|
||||
case WAIT_UNCLOCKED_POWER_OFF:
|
||||
val |= 0x1 << BP_CLPCR_LPM;
|
||||
@ -265,12 +293,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
|
||||
val |= 0x3 << BP_CLPCR_STBY_COUNT;
|
||||
val |= BM_CLPCR_VSTBY;
|
||||
val |= BM_CLPCR_SBYOS;
|
||||
if (cpu_is_imx6sl()) {
|
||||
if (cpu_is_imx6sl())
|
||||
val |= BM_CLPCR_BYPASS_PMIC_READY;
|
||||
if (cpu_is_imx6sl() || cpu_is_imx6sx())
|
||||
val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
|
||||
} else {
|
||||
else
|
||||
val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
@ -314,8 +342,22 @@ static int imx6q_suspend_finish(unsigned long val)
|
||||
static int imx6q_pm_enter(suspend_state_t state)
|
||||
{
|
||||
switch (state) {
|
||||
case PM_SUSPEND_STANDBY:
|
||||
imx6q_set_lpm(STOP_POWER_ON);
|
||||
imx6q_set_int_mem_clk_lpm(true);
|
||||
imx_gpc_pre_suspend(false);
|
||||
if (cpu_is_imx6sl())
|
||||
imx6sl_set_wait_clk(true);
|
||||
/* Zzz ... */
|
||||
cpu_do_idle();
|
||||
if (cpu_is_imx6sl())
|
||||
imx6sl_set_wait_clk(false);
|
||||
imx_gpc_post_resume();
|
||||
imx6q_set_lpm(WAIT_CLOCKED);
|
||||
break;
|
||||
case PM_SUSPEND_MEM:
|
||||
imx6q_set_lpm(STOP_POWER_OFF);
|
||||
imx6q_set_int_mem_clk_lpm(false);
|
||||
imx6q_enable_wb(true);
|
||||
/*
|
||||
* For suspend into ocram, asm code already take care of
|
||||
@ -323,7 +365,7 @@ static int imx6q_pm_enter(suspend_state_t state)
|
||||
*/
|
||||
if (!imx6_suspend_in_ocram_fn)
|
||||
imx6q_enable_rbc(true);
|
||||
imx_gpc_pre_suspend();
|
||||
imx_gpc_pre_suspend(true);
|
||||
imx_anatop_pre_suspend();
|
||||
imx_set_cpu_jump(0, v7_cpu_resume);
|
||||
/* Zzz ... */
|
||||
@ -334,6 +376,7 @@ static int imx6q_pm_enter(suspend_state_t state)
|
||||
imx_gpc_post_resume();
|
||||
imx6q_enable_rbc(false);
|
||||
imx6q_enable_wb(false);
|
||||
imx6q_set_int_mem_clk_lpm(true);
|
||||
imx6q_set_lpm(WAIT_CLOCKED);
|
||||
break;
|
||||
default:
|
||||
@ -343,9 +386,14 @@ static int imx6q_pm_enter(suspend_state_t state)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int imx6q_pm_valid(suspend_state_t state)
|
||||
{
|
||||
return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
|
||||
}
|
||||
|
||||
static const struct platform_suspend_ops imx6q_pm_ops = {
|
||||
.enter = imx6q_pm_enter,
|
||||
.valid = suspend_valid_only_mem,
|
||||
.valid = imx6q_pm_valid,
|
||||
};
|
||||
|
||||
void __init imx6q_pm_set_ccm_base(void __iomem *base)
|
||||
@ -549,3 +597,8 @@ void __init imx6sl_pm_init(void)
|
||||
{
|
||||
imx6_pm_common_init(&imx6sl_pm_data);
|
||||
}
|
||||
|
||||
void __init imx6sx_pm_init(void)
|
||||
{
|
||||
imx6_pm_common_init(&imx6sx_pm_data);
|
||||
}
|
||||
|
||||
@ -42,7 +42,10 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
|
||||
{
|
||||
unsigned int wcr_enable;
|
||||
|
||||
if (wdog_clk)
|
||||
if (!wdog_base)
|
||||
goto reset_fallback;
|
||||
|
||||
if (!IS_ERR(wdog_clk))
|
||||
clk_enable(wdog_clk);
|
||||
|
||||
if (cpu_is_mx1())
|
||||
@ -70,6 +73,7 @@ void mxc_restart(enum reboot_mode mode, const char *cmd)
|
||||
/* delay to allow the serial port to show the message */
|
||||
mdelay(50);
|
||||
|
||||
reset_fallback:
|
||||
/* we'll take a jump through zero as a poor second */
|
||||
soft_restart(0);
|
||||
}
|
||||
@ -79,13 +83,10 @@ void __init mxc_arch_reset_init(void __iomem *base)
|
||||
wdog_base = base;
|
||||
|
||||
wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
|
||||
if (IS_ERR(wdog_clk)) {
|
||||
if (IS_ERR(wdog_clk))
|
||||
pr_warn("%s: failed to get wdog clock\n", __func__);
|
||||
wdog_clk = NULL;
|
||||
return;
|
||||
}
|
||||
|
||||
clk_prepare(wdog_clk);
|
||||
else
|
||||
clk_prepare(wdog_clk);
|
||||
}
|
||||
|
||||
void __init mxc_arch_reset_init_dt(void)
|
||||
@ -97,13 +98,10 @@ void __init mxc_arch_reset_init_dt(void)
|
||||
WARN_ON(!wdog_base);
|
||||
|
||||
wdog_clk = of_clk_get(np, 0);
|
||||
if (IS_ERR(wdog_clk)) {
|
||||
if (IS_ERR(wdog_clk))
|
||||
pr_warn("%s: failed to get wdog clock\n", __func__);
|
||||
wdog_clk = NULL;
|
||||
return;
|
||||
}
|
||||
|
||||
clk_prepare(wdog_clk);
|
||||
else
|
||||
clk_prepare(wdog_clk);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
|
||||
@ -290,25 +290,20 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __init mxc_timer_init(void __iomem *base, int irq)
|
||||
static void __init _mxc_timer_init(int irq,
|
||||
struct clk *clk_per, struct clk *clk_ipg)
|
||||
{
|
||||
uint32_t tctl_val;
|
||||
struct clk *timer_clk;
|
||||
struct clk *timer_ipg_clk;
|
||||
|
||||
timer_clk = clk_get_sys("imx-gpt.0", "per");
|
||||
if (IS_ERR(timer_clk)) {
|
||||
if (IS_ERR(clk_per)) {
|
||||
pr_err("i.MX timer: unable to get clk\n");
|
||||
return;
|
||||
}
|
||||
|
||||
timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
|
||||
if (!IS_ERR(timer_ipg_clk))
|
||||
clk_prepare_enable(timer_ipg_clk);
|
||||
if (!IS_ERR(clk_ipg))
|
||||
clk_prepare_enable(clk_ipg);
|
||||
|
||||
clk_prepare_enable(timer_clk);
|
||||
|
||||
timer_base = base;
|
||||
clk_prepare_enable(clk_per);
|
||||
|
||||
/*
|
||||
* Initialise to a known state (all timers off, and timing reset)
|
||||
@ -325,21 +320,45 @@ void __init mxc_timer_init(void __iomem *base, int irq)
|
||||
__raw_writel(tctl_val, timer_base + MXC_TCTL);
|
||||
|
||||
/* init and register the timer to the framework */
|
||||
mxc_clocksource_init(timer_clk);
|
||||
mxc_clockevent_init(timer_clk);
|
||||
mxc_clocksource_init(clk_per);
|
||||
mxc_clockevent_init(clk_per);
|
||||
|
||||
/* Make irqs happen */
|
||||
setup_irq(irq, &mxc_timer_irq);
|
||||
}
|
||||
|
||||
void __init mxc_timer_init_dt(struct device_node *np)
|
||||
void __init mxc_timer_init(void __iomem *base, int irq)
|
||||
{
|
||||
void __iomem *base;
|
||||
struct clk *clk_per = clk_get_sys("imx-gpt.0", "per");
|
||||
struct clk *clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
|
||||
|
||||
timer_base = base;
|
||||
|
||||
_mxc_timer_init(irq, clk_per, clk_ipg);
|
||||
}
|
||||
|
||||
static void __init mxc_timer_init_dt(struct device_node *np)
|
||||
{
|
||||
struct clk *clk_per, *clk_ipg;
|
||||
int irq;
|
||||
|
||||
base = of_iomap(np, 0);
|
||||
WARN_ON(!base);
|
||||
if (timer_base)
|
||||
return;
|
||||
|
||||
timer_base = of_iomap(np, 0);
|
||||
WARN_ON(!timer_base);
|
||||
irq = irq_of_parse_and_map(np, 0);
|
||||
|
||||
mxc_timer_init(base, irq);
|
||||
clk_per = of_clk_get_by_name(np, "per");
|
||||
clk_ipg = of_clk_get_by_name(np, "ipg");
|
||||
|
||||
_mxc_timer_init(irq, clk_per, clk_ipg);
|
||||
}
|
||||
CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt);
|
||||
CLOCKSOURCE_OF_DECLARE(mx25_timer, "fsl,imx25-gpt", mxc_timer_init_dt);
|
||||
CLOCKSOURCE_OF_DECLARE(mx50_timer, "fsl,imx50-gpt", mxc_timer_init_dt);
|
||||
CLOCKSOURCE_OF_DECLARE(mx51_timer, "fsl,imx51-gpt", mxc_timer_init_dt);
|
||||
CLOCKSOURCE_OF_DECLARE(mx53_timer, "fsl,imx53-gpt", mxc_timer_init_dt);
|
||||
CLOCKSOURCE_OF_DECLARE(mx6q_timer, "fsl,imx6q-gpt", mxc_timer_init_dt);
|
||||
CLOCKSOURCE_OF_DECLARE(mx6sl_timer, "fsl,imx6sl-gpt", mxc_timer_init_dt);
|
||||
CLOCKSOURCE_OF_DECLARE(mx6sx_timer, "fsl,imx6sx-gpt", mxc_timer_init_dt);
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/irqdomain.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/exception.h>
|
||||
@ -153,13 +154,16 @@ static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
|
||||
* interrupts. It registers the interrupt enable and disable functions
|
||||
* to the kernel for each interrupt source.
|
||||
*/
|
||||
void __init tzic_init_irq(void __iomem *irqbase)
|
||||
void __init tzic_init_irq(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
int irq_base;
|
||||
int i;
|
||||
|
||||
tzic_base = irqbase;
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
|
||||
tzic_base = of_iomap(np, 0);
|
||||
WARN_ON(!tzic_base);
|
||||
|
||||
/* put the TZIC into the reset value with
|
||||
* all interrupts disabled
|
||||
*/
|
||||
@ -181,7 +185,6 @@ void __init tzic_init_irq(void __iomem *irqbase)
|
||||
irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
|
||||
WARN_ON(irq_base < 0);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
|
||||
domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
|
||||
&irq_domain_simple_ops, NULL);
|
||||
WARN_ON(!domain);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user