Commit Graph

176 Commits

Author SHA1 Message Date
Enric Balletbo i Serra
2542373195 soc: mediatek: mmsys: Fix missing UFOE component in mt8173 table routing
The UFOE (data compression engine) component needs to be enabled to have
the imgtec gpu driver working. If we don't enable it we see a black screen.
Looks like when we switched to use and array for setting the routing
registers in commit 440147639a ("soc: mediatek: mmsys: Use an array for
setting the routing registers") we missed to add this component in the new
routing table, it was present before that commit, so fix it by adding
this component in the mt8173 routing table.

Fixes: 440147639a ("soc: mediatek: mmsys: Use an array for setting the routing registers")
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: Eizan Miyamoto <eizan@chromium.org>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20210625062448.3462177-1-enric.balletbo@collabora.com
[mb: taking into account mask value]
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-08-06 16:43:23 +02:00
Fabien Parent
bc3fc5c051 soc: mediatek: mmsys: add MT8365 support
Add DSI mmsys connections for the MT8365 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20210519161847.3747352-3-fparent@baylibre.com
[mb: take the mask field into account]
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-08-06 16:43:23 +02:00
CK Hu
7bdcead7a7 soc: mmsys: mediatek: add mask to mmsys routes
SOUT has many bits and need to be cleared before set new value.
Write only could do the clear, but for MOUT, it clears bits that
should not be cleared. So use a mask to reset only the needed bits.

this fixes HDMI issues on MT7623/BPI-R2 since 5.13

Fixes: 440147639a ("soc: mediatek: mmsys: Use an array for setting the routing registers")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Link: https://lore.kernel.org/r/20210729070549.5514-1-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-08-04 19:05:46 +02:00
Bilal Wasim
114956518c soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD
The mfg_async power domain in mt8173 is used to power up imgtec
gpu. This domain requires the da9211 regulator to be enabled before
the power domain can be enabled successfully.

Signed-off-by: Bilal Wasim <Bilal.Wasim@imgtec.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Link: https://lore.kernel.org/r/20210701114012.RESEND.2.I2e1bf1b589f9138ba6f89791ed9f1e9f3ddd0a5d@changeid
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-07-12 12:26:29 +02:00
Bilal Wasim
fb6d1d3b25 soc: mediatek: pm-domains: Use correct mask for bus_prot_clr
When "bus_prot_reg_update" is true, the driver should use
INFRA_TOPAXI_PROTECTEN for both setting and clearing the bus
protection. However, the driver does not use this mask for
clearing bus protection which causes failure when booting
the imgtec gpu.

Corrected and tested with mt8173 chromebook.

Signed-off-by: Bilal Wasim <Bilal.Wasim@imgtec.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Link: https://lore.kernel.org/r/20210701114012.RESEND.1.I27436c29c3bede46dcf86df696f48683662d1ec1@changeid
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-07-12 12:26:28 +02:00
Henry Chen
e88edc977b soc: mediatek: pwrap: add pwrap driver for MT8195 SoC
MT8195 are highly integrated SoC and use PMIC_MT6359 for
power management. This patch adds pwrap master driver to
access PMIC_MT6359.

Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210602112050.12338-3-james.lo@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-06-03 19:41:26 +02:00
Weiyi Lu
f0fce06e34 soc: mtk-pm-domains: Fix the clock prepared issue
In this new power domain driver, when adding one power domain
it will prepare the dependent clocks at the same.
So we only do clk_bulk_enable/disable control during power ON/OFF.
When system suspend, the pm runtime framework will forcely power off
power domains. However, the dependent clocks are disabled but kept
prepared.

In MediaTek clock drivers, PLL would be turned ON when we do
clk_bulk_prepare control.

Clock hierarchy:
PLL -->
       DIV_CK -->
                 CLK_MUX
                 (may be dependent clocks)
                         -->
                             SUBSYS_CG
                             (may be dependent clocks)

It will lead some unexpected clock states during system suspend.
This patch will fix by doing prepare_enable/disable_unprepare on
dependent clocks at the same time while we are going to power on/off
any power domain.

Fixes: 59b644b01c ("soc: mediatek: Add MediaTek SCPSYS power domains")
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: chun-jie.chen <chun-jie.chen@mediatek.com>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20210601035905.2970384-1-hsinyi@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-06-02 13:53:31 +02:00
Hsin-Yi Wang
eed6ff1bb2 soc: mtk-pm-domains: do not register smi node as syscon
Mediatek requires mmsys clocks to be unprepared during suspend,
otherwise system has chances to hang.

syscon_regmap_lookup_by_phandle_optional() will attach and prepare the
first clock in smi node, leading to additional prepare to the clock
which is not balanced with the prepare/unprepare pair in resume/suspend
callbacks.

If a power domain node requests an smi node and the smi node's first
clock is an mmsys clock, it will results in an unstable suspend resume.

Fixes: f414854c88 ("soc: mediatek: pm-domains: Add SMI block as bus protection block")
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: chun-jie.chen <chun-jie.chen@mediatek.com>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20210601035905.2970384-2-hsinyi@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-06-02 13:53:31 +02:00
Zou Wei
ba96de3ae5 soc: mediatek: add missing MODULE_DEVICE_TABLE
This patch adds missing MODULE_DEVICE_TABLE definition which generates
correct modalias for automatic loading of this driver when it is built
as an external module.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zou Wei <zou_wei@huawei.com>
Link: https://lore.kernel.org/r/1620705350-104687-1-git-send-email-zou_wei@huawei.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-05-12 18:29:37 +02:00
Fabien Parent
060f7875bd soc: mediatek: mmsys: Add support for MT8167 SoC
Add routing table for DSI on MT8167 SoC. The registers are mostly
incompatible with the current defines, so new one for MT8167 are added.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20210405200354.2194930-2-fparent@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-04-06 12:57:10 +02:00
Enric Balletbo i Serra
60d93f64a8 soc: mediatek: pm-domains: Add a power domain names for mt8167
Add the power domains names for the mt8167 SoC.

Fixes: 207f13b419 ("soc: mediatek: pm-domains: Add support for mt8167")
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Link: https://lore.kernel.org/r/20210225175000.824661-4-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-04-01 11:36:04 +02:00
Enric Balletbo i Serra
3edc01bc53 soc: mediatek: pm-domains: Add a power domain names for mt8192
Add the power domains names for the mt8192 SoC.

Fixes: a49d5e7a89 ("soc: mediatek: pm-domains: Add support for mt8192")
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Link: https://lore.kernel.org/r/20210225175000.824661-3-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-04-01 11:36:04 +02:00
Enric Balletbo i Serra
e57b811225 soc: mediatek: pm-domains: Add a power domain names for mt8183
Add the power domains names for the mt8183 SoC. This removes the debugfs
errors like the following:

  debugfs: Directory 'power-domain' with parent 'pm_genpd' already present!

Fixes: eb9fa767fb ("soc: mediatek: pm-domains: Add support for mt8183")
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Link: https://lore.kernel.org/r/20210225175000.824661-2-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-04-01 11:36:04 +02:00
Enric Balletbo i Serra
022b02b450 soc: mediatek: pm-domains: Add a meaningful power domain name
Add the power domains names to the power domain struct so we
have meaningful name for every power domain. This also removes the
following debugfs error message.

  [    2.242068] debugfs: Directory 'power-domain' with parent 'pm_genpd' already present!
  [    2.249949] debugfs: Directory 'power-domain' with parent 'pm_genpd' already present!
  [    2.257784] debugfs: Directory 'power-domain' with parent 'pm_genpd' already present!
  ...

Fixes: 59b644b01c ("soc: mediatek: Add MediaTek SCPSYS power domains")
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Link: https://lore.kernel.org/r/20210225175000.824661-1-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-04-01 11:36:04 +02:00
Wei Yongjun
b23ab27b9a soc: mediatek: Make symbol 'mtk_mutex_driver' static
The sparse tool complains as follows:

drivers/soc/mediatek/mtk-mutex.c:464:24: warning:
 symbol 'mtk_mutex_driver' was not declared. Should it be static?

This symbol is not used outside of mtk-mutex.c, so this
commit marks it static.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://lore.kernel.org/r/20210210075656.1096251-1-weiyongjun1@huawei.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-04-01 11:27:54 +02:00
Hsin-Yi Wang
1ff1270fca soc: mediatek: mmsys: Add mt8183 mmsys routing table
mt8183 has different routing registers than mt8173.

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20210330110423.3542163-1-hsinyi@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-31 13:52:52 +02:00
Hsin-Hsiung Wang
9161385d53 soc: mediatek: pwrap: add pwrap driver for MT6873/8192 SoCs
MT6873/8192 are highly integrated SoCs and use PMIC_MT6359 for
power management. This patch adds pwrap master driver to
access PMIC_MT6359.

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Link: https://lore.kernel.org/r/1615563286-22126-5-git-send-email-hsin-hsiung.wang@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-30 12:24:09 +02:00
Hsin-Hsiung Wang
9d498d0b40 soc: mediatek: pwrap: add arbiter capability
Add arbiter capability for pwrap driver.
The arbiter capability uses new design to judge the priority and latency
for multi-channel.
The design with arbiter support cannot change the watchdog timer.
This patch is preparing for adding mt6873/8192 pwrap support.

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Link: https://lore.kernel.org/r/1615563286-22126-3-git-send-email-hsin-hsiung.wang@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-30 12:24:09 +02:00
Hsin-Hsiung Wang
d337ed031d soc: mediatek: pwrap: use BIT() macro
Use a better BIT() marco for the bit definition.
No functional changes, cleanup only.

Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Link: https://lore.kernel.org/r/1615563286-22126-2-git-send-email-hsin-hsiung.wang@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-30 12:24:09 +02:00
Enric Balletbo i Serra
9950588a45 soc: mediatek: pm-domains: Fix missing error code in scpsys_add_subdomain()
Adding one power domain in scpsys_add_subdomain is missing to assign an
error code when it fails. Fix that assigning an error code to 'ret',
this also fixes the follwowing smatch warning.

  drivers/soc/mediatek/mtk-pm-domains.c:492 scpsys_add_subdomain() warn: missing error code 'ret'

Fixes: dd65030295 ("soc: mediatek: pm-domains: Don't print an error if child domain is deferred")
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20210303091054.796975-1-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-30 11:52:44 +02:00
CK Hu
440147639a soc: mediatek: mmsys: Use an array for setting the routing registers
Actually, setting the registers for routing, use multiple 'if-else' for different
routes, but this code would be more and more complicated while we
support more and more SoCs. Change that and use a table per SoC so the
code will be more portable and clear.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20210317181711.795245-3-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-30 11:07:31 +02:00
CK Hu
ce15e7faa2 soc: mediatek: mmsys: Create struct mtk_mmsys to store context data
Apart from the driver data, in order to extend the driver to support more
and more SoCs, we will need to store other configuration data. So, create
a mtk_mmsys struct to encapsulate all that information.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://lore.kernel.org/r/20210317181711.795245-2-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-30 11:07:31 +02:00
Yongqiang Niu
0412120153 soc: mediatek: add mtk mutex support for MT8183
Add mtk mutex support for MT8183 SoC.

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Link: https://lore.kernel.org/r/20210129092209.2584718-8-hsinyi@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-17 17:30:57 +01:00
Linus Torvalds
d99676af54 drm pull for 5.12-rc1
docs:
 - lots of updated docs
 
 core:
 - require crtc to have unique primary plane
 - fourcc macro fix
 - PCI bar quirk for bar resizing
 - don't sent hotplug on error
 - move vm code to legacy
 - nuke hose only used on old oboslete alpha
 
 dma-buf:
 - kernel doc updates
 - improved lock tracking
 
 dp/hdmi:
 - DP-HDMI2.1 protocol converter support
 
 ttm:
 - bo size handling cleanup
 - release a pinned bo warning
 - cleanup lru handler
 - avoid using pages with drm_prime_sg_to_page_addr_arrays
 
 cma-helper:
 - prime/mmap fixes
 
 bridge:
 - add DP support
 
 gma500:
 - remove gma3600 support
 
 i915:
 - try eDP fast/narrow link again with fallback
 - Intel eDP backlight control
 - replace display register read/write macros
 - refactor intel_display.c
 - display power improvements
 - HPD code cleanup
 - Rocketlake display fixes
 - Power/backlight/RPM fixes
 - DG1 display fix
 - IVB/BYT clear residuals security fix again
 - make i915 mitigations options via parameter
 - HSW GT1 GPU hangs fixes
 - DG1 workaround hang fixes
 - TGL DMAR hang avoidance
 - Lots of GT fixes
 - follow on fixes for residuals clear
 - gen7 per-engine-reset support
 - HDCP2.2 + HDCP1.4 GEN12 DP MST support
 - TGL clear color support
 - backlight refactoring
 - VRR/Adaptive sync enabling on DP/EDP for TGL+
 - async flips for all ilk+
 
 amdgpu:
 - rework IH ring handling (Vega/Navi)
 - rework HDP handling (Vega/Navi)
 - swSMU updates for renoir/vangogh
 - Sienna Cichild overdrive support
 - FP16 on DCE8-11 support
 - GPU reset on navy flounder/vangogh
 - SMU profile fixes for APU
 - SR-IOV fixes
 - Vangogh SMU fixes
 - fan speed control fixes
 
 amdkfd:
 - config handling fix
 - buffer free fix
 - recursive lock warnings fix
 
 nouveau:
 - Turing MMU fault recovery fixes
 - mDP connectors reporting fix
 - audio locking fixes
 - rework engines/instances code to support new scheme
 
 tegra:
 - VIC newer firmware support
 - display/gr2d fixes for older tegra
 - pm reference leak fix
 
 mediatek:
 - SOC MT8183 support
 - decouple sub driver + share mtk mutex driver
 
 radeon:
 - PCI resource fix for some platforms
 
 ingenic:
 - pm support
 - 8-bit delta RGB panels
 
 vmwgfx:
 - managed driver helpers
 
 vc4:
 - BCM2711 DSI1 support
 - converted to atomic helpers
 - enable 10/12 bpc outputs
 - gem prime mmap helpers
 - CEC fix
 
 omap:
 - use degamma table
 - CTM support
 - rework DSI support
 
 imx:
 - stack usage fixes
 - drm managed support
 - imx-tve clock provider leak fix
 -
 
 rcar-du:
 - default mode fixes
 - conversion to managed API
 
 hisilicon:
 - use simple encoder
 
 vkms:
 - writeback connector support
 
 d3:
 - BT2020 support
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJgL1RCAAoJEAx081l5xIa+BxoP/325goULPaGBwUKgVkSl6mTT
 Ror0r8U3ifQHrqPk57C5b4GfvNuJ8vJZC13GYiiwooPn/+sifbl8haMRQWKyH4fz
 PThm9vroIQZ8VC+fqixgrOwFKEwkKqucZ3f7dEj8paBVVcO9DcBIaSeO4QW2EAR/
 n2r7nHtFxVHYEwiOnJvIeWIh1dAmudr/U6pHyB6PnuofVgqveXHT5+mmkY51pJqF
 sn2Y+Ye3tP5+FDlKkueg8JUteyFRTGz1g7JQThxSI//b/+p4MmmRX03qcWvIIkOX
 XiNlP73Ssh7PPMcUgwFmvKbMfm9sfpwf7yX3nqzaAQAHZGufznxX0k50BRkxWyYL
 eMVxRs5/Vl5JAn3vhspAUZhc4BgOcJm9L4zazb7YqDghwpohSnXk/riunUevqFCf
 Dgsc8N63nft8WEBk3aB6loRpDDpo5rm8gVpl5LKk1YXT92o9x4eP+/B1+kf2RepM
 52H3CKD1GLK3ayJlRNa/ljE2qXaQru+PmjCxORgDPEZ7SXdb8q5bfH0MjCB4vEBp
 YIybWYIDQzRBKglN5qMQ3XNIgv95oqrxXKaDFFtp8lMEjVG0v+y2antzFHftXS2g
 Cj0aeyBx4PC3pNbZe54npEhFwVIs7NFXX9brpQnnLJvQj/Qp+GEhf8uqiCUJNnYA
 AF7qRRL0bBGTeiJGt4nM
 =TeKl
 -----END PGP SIGNATURE-----

Merge tag 'drm-next-2021-02-19' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie:
 "A pretty normal tree, lots of refactoring across the board, ttm, i915,
  nouveau, and bunch of features in various drivers.

  docs:
   - lots of updated docs

  core:
   - require crtc to have unique primary plane
   - fourcc macro fix
   - PCI bar quirk for bar resizing
   - don't sent hotplug on error
   - move vm code to legacy
   - nuke hose only used on old oboslete alpha

  dma-buf:
   - kernel doc updates
   - improved lock tracking

  dp/hdmi:
   - DP-HDMI2.1 protocol converter support

  ttm:
   - bo size handling cleanup
   - release a pinned bo warning
   - cleanup lru handler
   - avoid using pages with drm_prime_sg_to_page_addr_arrays

  cma-helper:
   - prime/mmap fixes

  bridge:
   - add DP support

  gma500:
   - remove gma3600 support

  i915:
   - try eDP fast/narrow link again with fallback
   - Intel eDP backlight control
   - replace display register read/write macros
   - refactor intel_display.c
   - display power improvements
   - HPD code cleanup
   - Rocketlake display fixes
   - Power/backlight/RPM fixes
   - DG1 display fix
   - IVB/BYT clear residuals security fix again
   - make i915 mitigations options via parameter
   - HSW GT1 GPU hangs fixes
   - DG1 workaround hang fixes
   - TGL DMAR hang avoidance
   - Lots of GT fixes
   - follow on fixes for residuals clear
   - gen7 per-engine-reset support
   - HDCP2.2 + HDCP1.4 GEN12 DP MST support
   - TGL clear color support
   - backlight refactoring
   - VRR/Adaptive sync enabling on DP/EDP for TGL+
   - async flips for all ilk+

  amdgpu:
   - rework IH ring handling (Vega/Navi)
   - rework HDP handling (Vega/Navi)
   - swSMU updates for renoir/vangogh
   - Sienna Cichild overdrive support
   - FP16 on DCE8-11 support
   - GPU reset on navy flounder/vangogh
   - SMU profile fixes for APU
   - SR-IOV fixes
   - Vangogh SMU fixes
   - fan speed control fixes

  amdkfd:
   - config handling fix
   - buffer free fix
   - recursive lock warnings fix

  nouveau:
   - Turing MMU fault recovery fixes
   - mDP connectors reporting fix
   - audio locking fixes
   - rework engines/instances code to support new scheme

  tegra:
   - VIC newer firmware support
   - display/gr2d fixes for older tegra
   - pm reference leak fix

  mediatek:
   - SOC MT8183 support
   - decouple sub driver + share mtk mutex driver

  radeon:
   - PCI resource fix for some platforms

  ingenic:
   - pm support
   - 8-bit delta RGB panels

  vmwgfx:
   - managed driver helpers

  vc4:
   - BCM2711 DSI1 support
   - converted to atomic helpers
   - enable 10/12 bpc outputs
   - gem prime mmap helpers
   - CEC fix

  omap:
   - use degamma table
   - CTM support
   - rework DSI support

  imx:
   - stack usage fixes
   - drm managed support
   - imx-tve clock provider leak fix
-

  rcar-du:
   - default mode fixes
   - conversion to managed API

  hisilicon:
   - use simple encoder

  vkms:
   - writeback connector support

  d3:
   - BT2020 support"

* tag 'drm-next-2021-02-19' of git://anongit.freedesktop.org/drm/drm: (1459 commits)
  drm/amdgpu: Set reference clock to 100Mhz on Renoir (v2)
  drm/radeon: OLAND boards don't have VCE
  drm/amdkfd: Fix recursive lock warnings
  drm/amd/display: Add FPU wrappers to dcn21_validate_bandwidth()
  drm/amd/display: Fix potential integer overflow
  drm/amdgpu/display: remove hdcp_srm sysfs on device removal
  drm/amdgpu: fix CGTS_TCC_DISABLE register offset on gfx10.3
  drm/i915/gt: Correct surface base address for renderclear
  drm/i915: Disallow plane x+w>stride on ilk+ with X-tiling
  drm/nouveau/top/ga100: initial support
  drm/nouveau/top: add ioctrl/nvjpg
  drm/nouveau/privring: rename from ibus
  drm/nouveau/nvkm: remove nvkm_subdev.index
  drm/nouveau/nvkm: determine subdev id/order from layout
  drm/nouveau/vic: switch to instanced constructor
  drm/nouveau/sw: switch to instanced constructor
  drm/nouveau/sec2: switch to instanced constructor
  drm/nouveau/sec: switch to instanced constructor
  drm/nouveau/pm: switch to instanced constructor
  drm/nouveau/nvenc: switch to instanced constructor
  ...
2021-02-21 14:44:44 -08:00
CK Hu
e1e4f7fea3 soc / drm: mediatek: Move mtk mutex driver to soc folder
mtk mutex is used by DRM and MDP driver, and its function is SoC-specific,
so move it to soc folder.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-02-04 22:55:46 +08:00
Enric Balletbo i Serra
dd65030295 soc: mediatek: pm-domains: Don't print an error if child domain is deferred
Child domains can be deferred by the core because one of its resources
is not available yet, in such case, it will print an error, but
later it will succeed to probe. Fix that using the dev_err_probe()
function so it only prints an error on a real error.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Link: https://lore.kernel.org/r/20210113213012.67643-1-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-01-31 15:59:16 +01:00
Hsin-Yi Wang
1b18c0558d soc: mediatek: pm-domains: Add domain regulator supply
Some power domains (eg. mfg) needs to turn on power supply before power
on.

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20210129101208.2625249-3-hsinyi@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-01-31 15:47:49 +01:00
Chun-Kuang Hu
1570db1da9 soc: mediatek: cmdq: Remove cmdq_pkt_flush()
rx_callback is a standard mailbox callback mechanism and could
cover the function of proprietary cmdq_task_cb, so it is better
to use the standard one instead of the proprietary one. But
register rx_callback should before mbox_request_channel(),
so remove cmdq_pkt_flush() and let client driver implement
its own synchronous flush.

Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://lore.kernel.org/r/20201202235856.7652-1-chunkuang.hu@kernel.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-01-31 12:35:46 +01:00
Fabien Parent
207f13b419 soc: mediatek: pm-domains: Add support for mt8167
Add the needed board data to support mt8167 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201209133238.384030-2-fparent@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-01-31 11:19:30 +01:00
Enric Balletbo i Serra
1dcdee6ee8 soc: mediatek: mmsys: Specify HAS_IOMEM dependency for MTK_MMSYS
Because mtk-mmsys uses the 'devm_platform_ioremap_resource' function, it
should depend on HAS_IOMEM.

Fixes: cc6576029a ("soc: mediatek: mmsys: Use devm_platform_ioremap_resource()")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/20201203121447.3366406-1-enric.balletbo@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-12-10 15:33:56 +01:00
Enric Balletbo i Serra
cc6576029a soc: mediatek: mmsys: Use devm_platform_ioremap_resource()
For the common platform_get_resource()+devm_platform_ioremap() combination,
there is a helper, so use it and make the code a bit more compact.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://lore.kernel.org/r/20201006193320.405529-3-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-11-28 00:37:12 +01:00
Yongqiang Niu
51c0e618b2 soc / drm: mediatek: Move DDP component defines into mtk-mmsys.h
MMSYS is the driver which controls the routing of these DDP components,
so the definition of the mtk_ddp_comp_id enum should be placed in mtk-mmsys.h

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://lore.kernel.org/r/20201006193320.405529-2-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-11-28 00:34:23 +01:00
Neal Liu
0890beb226 soc: mediatek: add mt6779 devapc driver
MediaTek bus fabric provides TrustZone security support and data
protection to prevent slaves from being accessed by unexpected
masters.
The security violation is logged and sent to the processor for
further analysis or countermeasures.

Any occurrence of security violation would raise an interrupt, and
it will be handled by mtk-devapc driver. The violation
information is printed in order to find the murderer.

Signed-off-by: Neal Liu <neal.liu@mediatek.com>
Link: https://lore.kernel.org/r/1602732039-12179-3-git-send-email-neal.liu@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-11-28 00:28:25 +01:00
Chun-Kuang Hu
a69dcdfc2d soc / drm: mediatek: cmdq: Remove timeout handler in helper function
For each client driver, its timeout handler need to dump hardware register
or its state machine information, and their way to detect timeout are
also different, so remove timeout handler in helper function and
let client driver implement its own timeout handler.

Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/20201102000438.29225-1-chunkuang.hu@kernel.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-11-27 23:35:34 +01:00
Weiyi Lu
a49d5e7a89 soc: mediatek: pm-domains: Add support for mt8192
Add the needed board data to support mt8192 SoC.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: Weiyi Lu <weiyi.lu@mediatek.com>
Link: https://lore.kernel.org/r/20201030113622.201188-17-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-11-27 12:04:43 +01:00
Weiyi Lu
c1f3163d8f soc: mediatek: pm-domains: Add default power off flag
For some power domain, like conn on MT8192, it should be default OFF.
Because the power on/off control relies the function of connectivity chip
and its firmware. And if project choose other chip vendor solution,
those necessary connectivity functions will not provided.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201030113622.201188-16-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-11-27 12:04:43 +01:00
Matthias Brugger
eb9fa767fb soc: mediatek: pm-domains: Add support for mt8183
Add the needed board data to support mt8183 SoC.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201030113622.201188-12-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-11-27 12:04:43 +01:00
Matthias Brugger
1d4597fa18 soc: mediatek: pm-domains: Allow bus protection to ignore clear ack
In some cases the hardware does not create an acknowledgment of the
bus protection clearing. Add a flag to the bus protection indicating
that a clear event will be ignored.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201030113622.201188-10-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-11-27 12:04:43 +01:00
Matthias Brugger
123e8b4fd0 soc: mediatek: pm-domains: Add subsystem clocks
For the bus protection operations, some subsystem clocks need to be enabled
before releasing the protection. This patch identifies the subsystem clocks
by it's name.

Suggested-by: Weiyi Lu <weiyi.lu@mediatek.com>
[Adapted the patch to the mtk-pm-domains driver]
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201030113622.201188-9-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-11-27 12:04:43 +01:00
Matthias Brugger
58a17e310a soc: mediatek: pm-domains: Add extra sram control
For some power domains like vpu_core on MT8183 whose sram need to do clock
and internal isolation while power on/off sram. We add a cap
"MTK_SCPD_SRAM_ISO" to judge if we need to do the extra sram isolation
control or not.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201030113622.201188-8-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-11-27 12:04:43 +01:00
Matthias Brugger
f414854c88 soc: mediatek: pm-domains: Add SMI block as bus protection block
Apart from the infracfg block, the SMI block is used to enable the bus
protection for some power domains. Add support for this block.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201030113622.201188-7-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-11-27 12:04:42 +01:00
Matthias Brugger
928296ea5d soc: mediatek: pm_domains: Make bus protection generic
Bus protection is not exclusively done by calling the infracfg misc driver.
Make the calls for setting and clearing the bus protection generic so
that we can use other blocks for it as well.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201030113622.201188-6-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-11-27 12:04:42 +01:00
Matthias Brugger
916d6d71ba soc: mediatek: pm-domains: Add bus protection protocol
Bus protection will need to update more then one register
in infracfg. Add support for several operations.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201030113622.201188-5-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-11-27 12:04:42 +01:00
Enric Balletbo i Serra
59b644b01c soc: mediatek: Add MediaTek SCPSYS power domains
The System Control Processor System (SCPSYS) has several power management
related tasks in the system. This driver implements support to handle
the different power domains supported in order to meet high performance
and low power requirements.

Co-developed-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201030113622.201188-3-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-11-27 12:04:42 +01:00
Nicolas Boichat
4007844b05 soc: mediatek: Check if power domains can be powered on at boot time
In the error case, where a power domain cannot be powered on
successfully at boot time (in mtk_register_power_domains),
pm_genpd_init would still be called with is_off=false, and the
system would later try to disable the power domain again, triggering
warnings as disabled clocks are disabled again (and other potential
issues).

Also print a warning splat in that case, as this should never
happen.

Fixes: c84e358718 ("soc: Mediatek: Add SCPSYS power domain driver")
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Link: https://lore.kernel.org/r/20200928113107.v2.1.I5e6f8c262031d0451fe7241b744f4f3111c1ce71@changeid
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-10-26 10:45:04 +01:00
Dennis YC Hsieh
23c22299cd soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api
Add clear parameter to let client decide if
event should be clear to 0 after GCE receive it.

Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://lore.kernel.org/r/1594136714-11650-9-git-send-email-dennis-yc.hsieh@mediatek.com
[mb: fix commit message]
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25 17:27:39 +02:00
Dennis YC Hsieh
946f1792d3 soc: mediatek: cmdq: add jump function
Add jump function so that client can jump to any address which
contains instruction.

Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
Link: https://lore.kernel.org/r/1594136714-11650-8-git-send-email-dennis-yc.hsieh@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25 17:27:38 +02:00
Dennis YC Hsieh
88a2ffc48d soc: mediatek: cmdq: add write_s_mask value function
add write_s_mask_value function in cmdq helper functions which
writes a constant value to address with mask and large dma
access support.

Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
Link: https://lore.kernel.org/r/1594136714-11650-7-git-send-email-dennis-yc.hsieh@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25 17:27:36 +02:00
Dennis YC Hsieh
1af43fce81 soc: mediatek: cmdq: add write_s value function
add write_s function in cmdq helper functions which
writes a constant value to address with large dma
access support.

Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
Link: https://lore.kernel.org/r/1594136714-11650-6-git-send-email-dennis-yc.hsieh@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25 17:27:35 +02:00
Dennis YC Hsieh
d3b04aab06 soc: mediatek: cmdq: add read_s function
Add read_s function in cmdq helper functions which support read value from
register or dma physical address into gce internal register.

Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com>
Link: https://lore.kernel.org/r/1594136714-11650-5-git-send-email-dennis-yc.hsieh@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2020-09-25 17:27:34 +02:00