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soc: mediatek: pm-domains: Add support for mt8192
Add the needed board data to support mt8192 SoC. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Tested-by: Weiyi Lu <weiyi.lu@mediatek.com> Link: https://lore.kernel.org/r/20201030113622.201188-17-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Weiyi Lu
Matthias Brugger
parent
c1f3163d8f
commit
a49d5e7a89
292
drivers/soc/mediatek/mt8192-pm-domains.h
Normal file
292
drivers/soc/mediatek/mt8192-pm-domains.h
Normal file
@ -0,0 +1,292 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
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#define __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
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#include "mtk-pm-domains.h"
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#include <dt-bindings/power/mt8192-power.h>
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/*
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* MT8192 power domain support
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*/
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static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
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[MT8192_POWER_DOMAIN_AUDIO] = {
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.sta_mask = BIT(21),
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.ctl_offs = 0x0354,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO,
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MT8192_TOP_AXI_PROT_EN_2_SET,
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MT8192_TOP_AXI_PROT_EN_2_CLR,
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MT8192_TOP_AXI_PROT_EN_2_STA1),
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},
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},
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[MT8192_POWER_DOMAIN_CONN] = {
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.sta_mask = PWR_STATUS_CONN,
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.ctl_offs = 0x0304,
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.sram_pdn_bits = 0,
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.sram_pdn_ack_bits = 0,
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.bp_infracfg = {
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN,
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MT8192_TOP_AXI_PROT_EN_SET,
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MT8192_TOP_AXI_PROT_EN_CLR,
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MT8192_TOP_AXI_PROT_EN_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND,
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MT8192_TOP_AXI_PROT_EN_SET,
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MT8192_TOP_AXI_PROT_EN_CLR,
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MT8192_TOP_AXI_PROT_EN_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN,
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MT8192_TOP_AXI_PROT_EN_1_SET,
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MT8192_TOP_AXI_PROT_EN_1_CLR,
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MT8192_TOP_AXI_PROT_EN_1_STA1),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8192_POWER_DOMAIN_MFG0] = {
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.sta_mask = BIT(2),
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.ctl_offs = 0x0308,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8192_POWER_DOMAIN_MFG1] = {
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.sta_mask = BIT(3),
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.ctl_offs = 0x030c,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1,
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MT8192_TOP_AXI_PROT_EN_1_SET,
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MT8192_TOP_AXI_PROT_EN_1_CLR,
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MT8192_TOP_AXI_PROT_EN_1_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1,
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MT8192_TOP_AXI_PROT_EN_2_SET,
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MT8192_TOP_AXI_PROT_EN_2_CLR,
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MT8192_TOP_AXI_PROT_EN_2_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1,
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MT8192_TOP_AXI_PROT_EN_SET,
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MT8192_TOP_AXI_PROT_EN_CLR,
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MT8192_TOP_AXI_PROT_EN_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND,
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MT8192_TOP_AXI_PROT_EN_2_SET,
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MT8192_TOP_AXI_PROT_EN_2_CLR,
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MT8192_TOP_AXI_PROT_EN_2_STA1),
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},
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},
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[MT8192_POWER_DOMAIN_MFG2] = {
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.sta_mask = BIT(4),
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.ctl_offs = 0x0310,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8192_POWER_DOMAIN_MFG3] = {
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.sta_mask = BIT(5),
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.ctl_offs = 0x0314,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8192_POWER_DOMAIN_MFG4] = {
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.sta_mask = BIT(6),
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.ctl_offs = 0x0318,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8192_POWER_DOMAIN_MFG5] = {
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.sta_mask = BIT(7),
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.ctl_offs = 0x031c,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8192_POWER_DOMAIN_MFG6] = {
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.sta_mask = BIT(8),
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.ctl_offs = 0x0320,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8192_POWER_DOMAIN_DISP] = {
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.sta_mask = BIT(20),
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.ctl_offs = 0x0350,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP,
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MT8192_TOP_AXI_PROT_EN_MM_SET,
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MT8192_TOP_AXI_PROT_EN_MM_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_STA1),
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BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP,
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MT8192_TOP_AXI_PROT_EN_MM_2_SET,
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MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_DISP,
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MT8192_TOP_AXI_PROT_EN_SET,
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MT8192_TOP_AXI_PROT_EN_CLR,
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MT8192_TOP_AXI_PROT_EN_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND,
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MT8192_TOP_AXI_PROT_EN_MM_SET,
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MT8192_TOP_AXI_PROT_EN_MM_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND,
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MT8192_TOP_AXI_PROT_EN_MM_2_SET,
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MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
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},
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},
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[MT8192_POWER_DOMAIN_IPE] = {
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.sta_mask = BIT(14),
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.ctl_offs = 0x0338,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE,
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MT8192_TOP_AXI_PROT_EN_MM_SET,
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MT8192_TOP_AXI_PROT_EN_MM_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND,
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MT8192_TOP_AXI_PROT_EN_MM_SET,
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MT8192_TOP_AXI_PROT_EN_MM_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_STA1),
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},
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},
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[MT8192_POWER_DOMAIN_ISP] = {
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.sta_mask = BIT(12),
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.ctl_offs = 0x0330,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP,
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MT8192_TOP_AXI_PROT_EN_MM_2_SET,
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MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND,
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MT8192_TOP_AXI_PROT_EN_MM_2_SET,
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MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
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},
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},
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[MT8192_POWER_DOMAIN_ISP2] = {
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.sta_mask = BIT(13),
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.ctl_offs = 0x0334,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2,
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MT8192_TOP_AXI_PROT_EN_MM_SET,
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MT8192_TOP_AXI_PROT_EN_MM_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND,
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MT8192_TOP_AXI_PROT_EN_MM_SET,
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MT8192_TOP_AXI_PROT_EN_MM_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_STA1),
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},
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},
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[MT8192_POWER_DOMAIN_MDP] = {
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.sta_mask = BIT(19),
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.ctl_offs = 0x034c,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP,
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MT8192_TOP_AXI_PROT_EN_MM_2_SET,
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MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND,
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MT8192_TOP_AXI_PROT_EN_MM_2_SET,
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MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
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},
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},
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[MT8192_POWER_DOMAIN_VENC] = {
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.sta_mask = BIT(17),
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.ctl_offs = 0x0344,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC,
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MT8192_TOP_AXI_PROT_EN_MM_SET,
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MT8192_TOP_AXI_PROT_EN_MM_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND,
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MT8192_TOP_AXI_PROT_EN_MM_SET,
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MT8192_TOP_AXI_PROT_EN_MM_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_STA1),
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},
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},
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[MT8192_POWER_DOMAIN_VDEC] = {
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.sta_mask = BIT(15),
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.ctl_offs = 0x033c,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC,
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MT8192_TOP_AXI_PROT_EN_MM_SET,
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MT8192_TOP_AXI_PROT_EN_MM_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND,
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MT8192_TOP_AXI_PROT_EN_MM_SET,
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MT8192_TOP_AXI_PROT_EN_MM_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_STA1),
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},
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},
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[MT8192_POWER_DOMAIN_VDEC2] = {
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.sta_mask = BIT(16),
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.ctl_offs = 0x0340,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8192_POWER_DOMAIN_CAM] = {
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.sta_mask = BIT(23),
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.ctl_offs = 0x035c,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.bp_infracfg = {
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_CAM,
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MT8192_TOP_AXI_PROT_EN_2_SET,
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MT8192_TOP_AXI_PROT_EN_2_CLR,
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MT8192_TOP_AXI_PROT_EN_2_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM,
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MT8192_TOP_AXI_PROT_EN_MM_SET,
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MT8192_TOP_AXI_PROT_EN_MM_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CAM,
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MT8192_TOP_AXI_PROT_EN_1_SET,
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MT8192_TOP_AXI_PROT_EN_1_CLR,
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MT8192_TOP_AXI_PROT_EN_1_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND,
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MT8192_TOP_AXI_PROT_EN_MM_SET,
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MT8192_TOP_AXI_PROT_EN_MM_CLR,
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MT8192_TOP_AXI_PROT_EN_MM_STA1),
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BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM,
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MT8192_TOP_AXI_PROT_EN_VDNR_SET,
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MT8192_TOP_AXI_PROT_EN_VDNR_CLR,
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MT8192_TOP_AXI_PROT_EN_VDNR_STA1),
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},
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},
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[MT8192_POWER_DOMAIN_CAM_RAWA] = {
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.sta_mask = BIT(24),
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.ctl_offs = 0x0360,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8192_POWER_DOMAIN_CAM_RAWB] = {
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.sta_mask = BIT(25),
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.ctl_offs = 0x0364,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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[MT8192_POWER_DOMAIN_CAM_RAWC] = {
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.sta_mask = BIT(26),
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.ctl_offs = 0x0368,
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.sram_pdn_bits = GENMASK(8, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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},
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};
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static const struct scpsys_soc_data mt8192_scpsys_data = {
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.domains_data = scpsys_domain_data_mt8192,
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.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8192),
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.pwr_sta_offs = 0x016c,
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.pwr_sta2nd_offs = 0x0170,
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};
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#endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */
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@ -17,6 +17,7 @@
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#include "mt8173-pm-domains.h"
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#include "mt8183-pm-domains.h"
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#include "mt8192-pm-domains.h"
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#define MTK_POLL_DELAY_US 10
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#define MTK_POLL_TIMEOUT USEC_PER_SEC
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@ -521,6 +522,10 @@ static const struct of_device_id scpsys_of_match[] = {
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.compatible = "mediatek,mt8183-power-controller",
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.data = &mt8183_scpsys_data,
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},
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{
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.compatible = "mediatek,mt8192-power-controller",
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.data = &mt8192_scpsys_data,
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},
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{ }
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};
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@ -2,6 +2,62 @@
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#ifndef __SOC_MEDIATEK_INFRACFG_H
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#define __SOC_MEDIATEK_INFRACFG_H
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#define MT8192_TOP_AXI_PROT_EN_STA1 0x228
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#define MT8192_TOP_AXI_PROT_EN_1_STA1 0x258
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#define MT8192_TOP_AXI_PROT_EN_SET 0x2a0
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#define MT8192_TOP_AXI_PROT_EN_CLR 0x2a4
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#define MT8192_TOP_AXI_PROT_EN_1_SET 0x2a8
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#define MT8192_TOP_AXI_PROT_EN_1_CLR 0x2ac
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#define MT8192_TOP_AXI_PROT_EN_MM_SET 0x2d4
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#define MT8192_TOP_AXI_PROT_EN_MM_CLR 0x2d8
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#define MT8192_TOP_AXI_PROT_EN_MM_STA1 0x2ec
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#define MT8192_TOP_AXI_PROT_EN_2_SET 0x714
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#define MT8192_TOP_AXI_PROT_EN_2_CLR 0x718
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#define MT8192_TOP_AXI_PROT_EN_2_STA1 0x724
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#define MT8192_TOP_AXI_PROT_EN_VDNR_SET 0xb84
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#define MT8192_TOP_AXI_PROT_EN_VDNR_CLR 0xb88
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#define MT8192_TOP_AXI_PROT_EN_VDNR_STA1 0xb90
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#define MT8192_TOP_AXI_PROT_EN_MM_2_SET 0xdcc
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#define MT8192_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0
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#define MT8192_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8
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#define MT8192_TOP_AXI_PROT_EN_DISP (BIT(6) | BIT(23))
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#define MT8192_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(18))
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#define MT8192_TOP_AXI_PROT_EN_CONN_2ND BIT(14)
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#define MT8192_TOP_AXI_PROT_EN_MFG1 GENMASK(22, 21)
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#define MT8192_TOP_AXI_PROT_EN_1_CONN BIT(10)
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#define MT8192_TOP_AXI_PROT_EN_1_MFG1 BIT(21)
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#define MT8192_TOP_AXI_PROT_EN_1_CAM BIT(22)
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#define MT8192_TOP_AXI_PROT_EN_2_CAM BIT(0)
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#define MT8192_TOP_AXI_PROT_EN_2_ADSP BIT(3)
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#define MT8192_TOP_AXI_PROT_EN_2_AUDIO BIT(4)
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#define MT8192_TOP_AXI_PROT_EN_2_MFG1 GENMASK(6, 5)
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#define MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND BIT(7)
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#define MT8192_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2))
|
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#define MT8192_TOP_AXI_PROT_EN_MM_DISP (BIT(0) | BIT(2) | \
|
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BIT(10) | BIT(12) | \
|
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BIT(14) | BIT(16) | \
|
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BIT(24) | BIT(26))
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND (BIT(1) | BIT(3))
|
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#define MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND (BIT(1) | BIT(3) | \
|
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BIT(15) | BIT(17) | \
|
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BIT(25) | BIT(27))
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_ISP2 BIT(14)
|
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#define MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND BIT(15)
|
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#define MT8192_TOP_AXI_PROT_EN_MM_IPE BIT(16)
|
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#define MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND BIT(17)
|
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#define MT8192_TOP_AXI_PROT_EN_MM_VDEC BIT(24)
|
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#define MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND BIT(25)
|
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#define MT8192_TOP_AXI_PROT_EN_MM_VENC BIT(26)
|
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#define MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(27)
|
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#define MT8192_TOP_AXI_PROT_EN_MM_2_ISP BIT(8)
|
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#define MT8192_TOP_AXI_PROT_EN_MM_2_DISP (BIT(8) | BIT(12))
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND BIT(9)
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND (BIT(9) | BIT(13))
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP BIT(12)
|
||||
#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13)
|
||||
#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21)
|
||||
|
||||
#define MT8183_TOP_AXI_PROT_EN_STA1 0x228
|
||||
#define MT8183_TOP_AXI_PROT_EN_STA1_1 0x258
|
||||
#define MT8183_TOP_AXI_PROT_EN_SET 0x2a0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user