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gpio fixes for v6.0-rc6
- fix the level-low interrupt type support in gpio-mpc8xxx - convert another two drivers to using immputable irq chips - MAINTAINERS update -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEFp3rbAvDxGAT0sefEacuoBRx13IFAmMkJ+EACgkQEacuoBRx 13JTBhAAgd37u3Q0XiLSGgKOwHlrD08d2n814Rs5TQf3vAlD5aHpz3z1ezqPmOhM 31fB8ottUHhP91qyTsNxPEY1wy+Pp6GSvUQGApLwqLN5K2EbxolbdXARSt9zLUvs L8oOJKt+SUEETNCjcxQW1CMMLZ8lWy0P9I/vv51fdYbVOKJldxHskO8F2OCiaKjI Z6ZCFVHSP1zi3RNQYqBH1Rr5Ow34CeAc74u/F5ygD4yluNQKu5BkThiGpBSKwqyh IvyYfYoo/RGQOwWxiv72gfRfwAC/ebyILz9MsdyotpUOj3OyzHrKo8KQmh82zcTP khQcLdCYlc5FmHgE8wxfK/sqckFqVBdm/iQQTIS2FD2hsH67QgMg/cVk8eZ9xRS7 wWf1z+jnC5JEJy3fjV6gGXKSfLsi0VxcPapAgmG8X6v9bglocTDSDfSf68ZkwEkE CTkjTPls1QwdfBFos0HY5mA07IpnFJWeNcaYdo8VTx5G7wX7m4C5iwvWoF3Zav0M RS7OkgihUOGjn3hIvQXu/PvdzpnPI+bQUqmr75aKFkAffxOB/eZc2W9+JogzfLpZ JoP6r0juZXy88W5/jpLS47n028hf8M9nw5F6GtI3CHFdbPJ47po9OjIVYY/bpK3p OOls6tMCf4NQrslon1kYcjR7lGzSW3oasQvLyhgYW1ICDUu5oMk= =/cR5 -----END PGP SIGNATURE----- Merge tag 'gpio-fixes-for-v6.0-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux Pull gpio fixes from Bartosz Golaszewski: - fix the level-low interrupt type support in gpio-mpc8xxx - convert another two drivers to using immutable irq chips - MAINTAINERS update * tag 'gpio-fixes-for-v6.0-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: gpio: mt7621: Make the irqchip immutable gpio: ixp4xx: Make irqchip immutable MAINTAINERS: Update HiSilicon GPIO Driver maintainer gpio: mpc8xxx: Fix support for IRQ_TYPE_LEVEL_LOW flow_type in mpc85xx
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commit
a335366bad
@ -9122,7 +9122,7 @@ S: Maintained
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F: drivers/dma/hisi_dma.c
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HISILICON GPIO DRIVER
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M: Luo Jiaxing <luojiaxing@huawei.com>
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M: Jay Fang <f.fangjian@huawei.com>
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L: linux-gpio@vger.kernel.org
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S: Maintained
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F: drivers/gpio/gpio-hisi.c
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@ -63,6 +63,14 @@ static void ixp4xx_gpio_irq_ack(struct irq_data *d)
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__raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS);
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}
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static void ixp4xx_gpio_mask_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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irq_chip_mask_parent(d);
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gpiochip_disable_irq(gc, d->hwirq);
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}
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static void ixp4xx_gpio_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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@ -72,6 +80,7 @@ static void ixp4xx_gpio_irq_unmask(struct irq_data *d)
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if (!(g->irq_edge & BIT(d->hwirq)))
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ixp4xx_gpio_irq_ack(d);
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gpiochip_enable_irq(gc, d->hwirq);
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irq_chip_unmask_parent(d);
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}
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@ -149,12 +158,14 @@ static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
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}
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static struct irq_chip ixp4xx_gpio_irqchip = {
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static const struct irq_chip ixp4xx_gpio_irqchip = {
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.name = "IXP4GPIO",
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.irq_ack = ixp4xx_gpio_irq_ack,
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.irq_mask = irq_chip_mask_parent,
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.irq_mask = ixp4xx_gpio_mask_irq,
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.irq_unmask = ixp4xx_gpio_irq_unmask,
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.irq_set_type = ixp4xx_gpio_irq_set_type,
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.flags = IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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static int ixp4xx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
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@ -263,7 +274,7 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev)
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g->gc.owner = THIS_MODULE;
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girq = &g->gc.irq;
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girq->chip = &ixp4xx_gpio_irqchip;
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gpio_irq_chip_set_chip(girq, &ixp4xx_gpio_irqchip);
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girq->fwnode = g->fwnode;
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girq->parent_domain = parent;
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girq->child_to_parent_hwirq = ixp4xx_gpio_child_to_parent_hwirq;
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@ -169,6 +169,7 @@ static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
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switch (flow_type) {
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_LEVEL_LOW:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
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gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
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@ -112,6 +112,8 @@ mediatek_gpio_irq_unmask(struct irq_data *d)
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unsigned long flags;
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u32 rise, fall, high, low;
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gpiochip_enable_irq(gc, d->hwirq);
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spin_lock_irqsave(&rg->lock, flags);
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rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
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fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
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@ -143,6 +145,8 @@ mediatek_gpio_irq_mask(struct irq_data *d)
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mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
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mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
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spin_unlock_irqrestore(&rg->lock, flags);
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gpiochip_disable_irq(gc, d->hwirq);
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}
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static int
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@ -204,6 +208,16 @@ mediatek_gpio_xlate(struct gpio_chip *chip,
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return gpio % MTK_BANK_WIDTH;
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}
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static const struct irq_chip mt7621_irq_chip = {
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.name = "mt7621-gpio",
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.irq_mask_ack = mediatek_gpio_irq_mask,
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.irq_mask = mediatek_gpio_irq_mask,
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.irq_unmask = mediatek_gpio_irq_unmask,
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.irq_set_type = mediatek_gpio_irq_type,
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.flags = IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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static int
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mediatek_gpio_bank_probe(struct device *dev, int bank)
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{
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@ -238,11 +252,6 @@ mediatek_gpio_bank_probe(struct device *dev, int bank)
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return -ENOMEM;
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rg->chip.offset = bank * MTK_BANK_WIDTH;
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rg->irq_chip.name = dev_name(dev);
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rg->irq_chip.irq_unmask = mediatek_gpio_irq_unmask;
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rg->irq_chip.irq_mask = mediatek_gpio_irq_mask;
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rg->irq_chip.irq_mask_ack = mediatek_gpio_irq_mask;
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rg->irq_chip.irq_set_type = mediatek_gpio_irq_type;
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if (mtk->gpio_irq) {
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struct gpio_irq_chip *girq;
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@ -262,7 +271,7 @@ mediatek_gpio_bank_probe(struct device *dev, int bank)
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}
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girq = &rg->chip.irq;
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girq->chip = &rg->irq_chip;
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gpio_irq_chip_set_chip(girq, &mt7621_irq_chip);
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/* This will let us handle the parent IRQ in the driver */
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girq->parent_handler = NULL;
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girq->num_parents = 0;
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