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i2c: tegra: Remove i2c_dev.clk_divisor_non_hs_mode member
The "non_hs_mode" divisor value is fixed, thus there is no need to have the variable i2c_dev.clk_divisor_non_hs_mode struct member. Let's remove it and move the mode selection into tegra_i2c_init() where it can be united with the timing selection. Reviewed-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
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@ -250,7 +250,6 @@ struct tegra_i2c_hw_feature {
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* @msg_buf_remaining: size of unsent data in the message buffer
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* @msg_read: identifies read transfers
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* @bus_clk_rate: current I2C bus clock rate
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* @clk_divisor_non_hs_mode: clock divider for non-high-speed modes
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* @is_multimaster_mode: track if I2C controller is in multi-master mode
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* @tx_dma_chan: DMA transmit channel
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* @rx_dma_chan: DMA receive channel
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@ -281,7 +280,6 @@ struct tegra_i2c_dev {
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size_t msg_buf_remaining;
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int msg_read;
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u32 bus_clk_rate;
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u16 clk_divisor_non_hs_mode;
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bool is_multimaster_mode;
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struct dma_chan *tx_dma_chan;
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struct dma_chan *rx_dma_chan;
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@ -783,6 +781,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
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u32 val;
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int err;
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u32 clk_divisor, clk_multiplier;
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u32 non_hs_mode;
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u32 tsu_thd;
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u8 tlow, thigh;
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@ -805,24 +804,33 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
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if (i2c_dev->is_vi)
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tegra_i2c_vi_init(i2c_dev);
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/* Make sure clock divisor programmed correctly */
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clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
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i2c_dev->hw->clk_divisor_hs_mode) |
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FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE,
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i2c_dev->clk_divisor_non_hs_mode);
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i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
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if (i2c_dev->bus_clk_rate > I2C_MAX_STANDARD_MODE_FREQ &&
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i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
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switch (i2c_dev->bus_clk_rate) {
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case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ:
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default:
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tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
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thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
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tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
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} else {
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if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ)
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non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
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else
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non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
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break;
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case 0 ... I2C_MAX_STANDARD_MODE_FREQ:
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tlow = i2c_dev->hw->tlow_std_mode;
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thigh = i2c_dev->hw->thigh_std_mode;
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tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
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non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
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break;
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}
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/* Make sure clock divisor programmed correctly */
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clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
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i2c_dev->hw->clk_divisor_hs_mode) |
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FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);
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i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
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if (i2c_dev->hw->has_interface_timing_reg) {
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val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
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FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
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@ -837,7 +845,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
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i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
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clk_multiplier = tlow + thigh + 2;
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clk_multiplier *= i2c_dev->clk_divisor_non_hs_mode + 1;
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clk_multiplier *= non_hs_mode + 1;
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err = clk_set_rate(i2c_dev->div_clk,
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i2c_dev->bus_clk_rate * clk_multiplier);
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@ -1751,18 +1759,6 @@ static int tegra_i2c_probe(struct platform_device *pdev)
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goto unprepare_fast_clk;
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}
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if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ &&
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i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_PLUS_FREQ)
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i2c_dev->clk_divisor_non_hs_mode =
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i2c_dev->hw->clk_divisor_fast_plus_mode;
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else if (i2c_dev->bus_clk_rate > I2C_MAX_STANDARD_MODE_FREQ &&
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i2c_dev->bus_clk_rate <= I2C_MAX_FAST_MODE_FREQ)
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i2c_dev->clk_divisor_non_hs_mode =
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i2c_dev->hw->clk_divisor_fast_mode;
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else
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i2c_dev->clk_divisor_non_hs_mode =
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i2c_dev->hw->clk_divisor_std_mode;
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ret = clk_prepare(i2c_dev->div_clk);
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if (ret < 0) {
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dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret);
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