riscv: sifive: Apply errata "cip-453" patch

Add sign extension to the $badaddr before addressing the instruction page
fault and instruction access fault to workaround the issue "cip-453".

To avoid affecting the existing code sequence, this patch will creates two
trampolines to add sign extension to the $badaddr. By the "alternative"
mechanism, these two trampolines will replace the original exception
handler of instruction page fault and instruction access fault in the
excp_vect_table. In this case, only the specific SiFive CPU core jumps to
the do_page_fault and do_trap_insn_fault through these two trampolines.
Other CPUs are not affected.

Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Vincent Chen 2021-03-22 22:26:05 +08:00 committed by Palmer Dabbelt
parent 1a0e5dbd37
commit 800149a77c
No known key found for this signature in database
GPG Key ID: 2E1319F35FBB1889
6 changed files with 94 additions and 3 deletions

View File

@ -19,4 +19,15 @@ config ERRATA_SIFIVE
Otherwise, please say "N" here to avoid unnecessary overhead.
config ERRATA_SIFIVE_CIP_453
bool "Apply SiFive errata CIP-453"
depends on ERRATA_SIFIVE
default y
help
This will apply the SiFive CIP-453 errata to add sign extension
to the $badaddr when exception type is instruction page fault
and instruction access fault.
If you don't know what to do here, say "Y".
endmenu

View File

@ -1 +1,2 @@
obj-y += errata_cip_453.o
obj-y += errata.o

View File

@ -16,6 +16,26 @@ struct errata_info_t {
bool (*check_func)(unsigned long arch_id, unsigned long impid);
};
static bool errata_cip_453_check_func(unsigned long arch_id, unsigned long impid)
{
/*
* Affected cores:
* Architecture ID: 0x8000000000000007
* Implement ID: 0x20181004 <= impid <= 0x20191105
*/
if (arch_id != 0x8000000000000007 ||
(impid < 0x20181004 || impid > 0x20191105))
return false;
return true;
}
static struct errata_info_t errata_list[ERRATA_SIFIVE_NUMBER] = {
{
.name = "cip-453",
.check_func = errata_cip_453_check_func
},
};
static u32 __init sifive_errata_probe(unsigned long archid, unsigned long impid)
{
int idx;

View File

@ -0,0 +1,38 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2021 SiFive
*/
#include <linux/linkage.h>
#include <asm/asm.h>
#include <asm/asm-offsets.h>
#include <asm/alternative.h>
.macro ADD_SIGN_EXT pt_reg badaddr tmp_reg
REG_L \badaddr, PT_BADADDR(\pt_reg)
li \tmp_reg,1
slli \tmp_reg,\tmp_reg,0x26
and \tmp_reg,\tmp_reg,\badaddr
beqz \tmp_reg, 1f
li \tmp_reg,-1
slli \tmp_reg,\tmp_reg,0x27
or \badaddr,\tmp_reg,\badaddr
REG_S \badaddr, PT_BADADDR(\pt_reg)
1:
.endm
ENTRY(sifive_cip_453_page_fault_trp)
ADD_SIGN_EXT a0, t0, t1
#ifdef CONFIG_MMU
la t0, do_page_fault
#else
la t0, do_trap_unknown
#endif
jr t0
END(sifive_cip_453_page_fault_trp)
ENTRY(sifive_cip_453_insn_fault_trp)
ADD_SIGN_EXT a0, t0, t1
la t0, do_trap_insn_fault
jr t0
END(sifive_cip_453_insn_fault_trp)

View File

@ -5,8 +5,27 @@
#ifndef ASM_ERRATA_LIST_H
#define ASM_ERRATA_LIST_H
#include <asm/alternative.h>
#include <asm/vendorid_list.h>
#ifdef CONFIG_ERRATA_SIFIVE
#define ERRATA_SIFIVE_NUMBER 0
#define ERRATA_SIFIVE_CIP_453 0
#define ERRATA_SIFIVE_NUMBER 1
#endif
#ifdef __ASSEMBLY__
#define ALT_INSN_FAULT(x) \
ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), \
__stringify(RISCV_PTR sifive_cip_453_insn_fault_trp), \
SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \
CONFIG_ERRATA_SIFIVE_CIP_453)
#define ALT_PAGE_FAULT(x) \
ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), \
__stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \
SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \
CONFIG_ERRATA_SIFIVE_CIP_453)
#endif /* __ASSEMBLY__ */
#endif

View File

@ -12,6 +12,7 @@
#include <asm/unistd.h>
#include <asm/thread_info.h>
#include <asm/asm-offsets.h>
#include <asm/errata_list.h>
#if !IS_ENABLED(CONFIG_PREEMPTION)
.set resume_kernel, restore_all
@ -450,7 +451,7 @@ ENDPROC(__switch_to)
/* Exception vector table */
ENTRY(excp_vect_table)
RISCV_PTR do_trap_insn_misaligned
RISCV_PTR do_trap_insn_fault
ALT_INSN_FAULT(RISCV_PTR do_trap_insn_fault)
RISCV_PTR do_trap_insn_illegal
RISCV_PTR do_trap_break
RISCV_PTR do_trap_load_misaligned
@ -461,7 +462,8 @@ ENTRY(excp_vect_table)
RISCV_PTR do_trap_ecall_s
RISCV_PTR do_trap_unknown
RISCV_PTR do_trap_ecall_m
RISCV_PTR do_page_fault /* instruction page fault */
/* instruciton page fault */
ALT_PAGE_FAULT(RISCV_PTR do_page_fault)
RISCV_PTR do_page_fault /* load page fault */
RISCV_PTR do_trap_unknown
RISCV_PTR do_page_fault /* store page fault */