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pinctrl: qcom: sdm845: Expose ufs_reset as gpio
The ufs_reset pin is expected to be wired to the reset pin of the primary UFS memory but is pretty much just a general purpose output pinr Reorder the pins and expose it as gpio 150, so that the UFS driver can toggle it. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -79,7 +79,7 @@ to specify in a pin configuration subnode:
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gpio0-gpio149
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Supports mux, bias and drive-strength
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sdc2_clk, sdc2_cmd, sdc2_data
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sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset
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Supports bias and drive-strength
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- function:
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@ -420,10 +420,10 @@ DECLARE_MSM_GPIO_PINS(147);
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DECLARE_MSM_GPIO_PINS(148);
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DECLARE_MSM_GPIO_PINS(149);
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static const unsigned int sdc2_clk_pins[] = { 150 };
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static const unsigned int sdc2_cmd_pins[] = { 151 };
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static const unsigned int sdc2_data_pins[] = { 152 };
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static const unsigned int ufs_reset_pins[] = { 153 };
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static const unsigned int ufs_reset_pins[] = { 150 };
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static const unsigned int sdc2_clk_pins[] = { 151 };
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static const unsigned int sdc2_cmd_pins[] = { 152 };
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static const unsigned int sdc2_data_pins[] = { 153 };
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enum sdm845_functions {
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msm_mux_gpio,
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@ -1271,10 +1271,10 @@ static const struct msm_pingroup sdm845_groups[] = {
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PINGROUP(147, NORTH, _, _, _, _, _, _, _, _, _, _),
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PINGROUP(148, NORTH, _, _, _, _, _, _, _, _, _, _),
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PINGROUP(149, NORTH, _, _, _, _, _, _, _, _, _, _),
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UFS_RESET(ufs_reset, 0x99f000),
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SDC_QDSD_PINGROUP(sdc2_clk, 0x99a000, 14, 6),
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SDC_QDSD_PINGROUP(sdc2_cmd, 0x99a000, 11, 3),
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SDC_QDSD_PINGROUP(sdc2_data, 0x99a000, 9, 0),
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UFS_RESET(ufs_reset, 0x99f000),
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};
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static const struct msm_pinctrl_soc_data sdm845_pinctrl = {
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@ -1284,7 +1284,7 @@ static const struct msm_pinctrl_soc_data sdm845_pinctrl = {
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.nfunctions = ARRAY_SIZE(sdm845_functions),
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.groups = sdm845_groups,
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.ngroups = ARRAY_SIZE(sdm845_groups),
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.ngpios = 150,
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.ngpios = 151,
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};
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static int sdm845_pinctrl_probe(struct platform_device *pdev)
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