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https://github.com/torvalds/linux.git
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pinctrl: Add drive strength support for BM1880 SoC
Add drive strength support for Bitmain BM1880 SoC. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Manivannan Sadhasivam
Linus Walleij
parent
7ea6a2edbf
commit
9f1e3c5966
@ -4,8 +4,6 @@
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*
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* Copyright (c) 2019 Linaro Ltd.
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*
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* TODO: Drive strength support
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*/
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#include <linux/io.h>
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@ -29,6 +27,7 @@
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* @ngroups: Number of @groups
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* @funcs: Pinmux functions
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* @nfuncs: Number of @funcs
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* @pconf: Pinconf data
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*/
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struct bm1880_pinctrl {
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void __iomem *base;
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@ -37,6 +36,7 @@ struct bm1880_pinctrl {
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unsigned int ngroups;
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const struct bm1880_pinmux_function *funcs;
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unsigned int nfuncs;
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const struct bm1880_pinconf_data *pinconf;
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};
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/**
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@ -69,6 +69,14 @@ struct bm1880_pinmux_function {
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u8 mux_shift;
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};
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/**
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* struct bm1880_pinconf_data - pinconf data
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* @drv_bits: Drive strength bit width
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*/
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struct bm1880_pinconf_data {
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u32 drv_bits;
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};
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static const struct pinctrl_pin_desc bm1880_pins[] = {
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PINCTRL_PIN(0, "MIO0"),
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PINCTRL_PIN(1, "MIO1"),
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@ -785,6 +793,126 @@ static const struct bm1880_pinmux_function bm1880_pmux_functions[] = {
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BM1880_PINMUX_FUNCTION(spi0, 1),
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};
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#define BM1880_PINCONF_DAT(_width) \
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{ \
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.drv_bits = _width, \
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}
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static const struct bm1880_pinconf_data bm1880_pinconf[] = {
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x03),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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BM1880_PINCONF_DAT(0x02),
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};
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static int bm1880_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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@ -878,9 +1006,145 @@ static int bm1880_pinmux_set_mux(struct pinctrl_dev *pctldev,
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#define BM1880_PINCONF_PULLCTRL(pin) BM1880_PINCONF(pin, 0)
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#define BM1880_PINCONF_PULLUP(pin) BM1880_PINCONF(pin, 1)
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#define BM1880_PINCONF_PULLDOWN(pin) BM1880_PINCONF(pin, 2)
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#define BM1880_PINCONF_DRV(pin) BM1880_PINCONF(pin, 6)
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#define BM1880_PINCONF_SCHMITT(pin) BM1880_PINCONF(pin, 9)
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#define BM1880_PINCONF_SLEW(pin) BM1880_PINCONF(pin, 10)
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static int bm1880_pinconf_drv_set(unsigned int mA, u32 width,
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u32 *regval, u32 bit_offset)
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{
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u32 _regval;
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_regval = *regval;
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/*
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* There are two sets of drive strength bit width exposed by the
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* SoC at 4mA step, hence we need to handle them separately.
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*/
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if (width == 0x03) {
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switch (mA) {
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case 4:
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_regval &= ~(width << bit_offset);
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_regval |= (0 << bit_offset);
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break;
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case 8:
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_regval &= ~(width << bit_offset);
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_regval |= (1 << bit_offset);
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break;
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case 12:
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_regval &= ~(width << bit_offset);
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_regval |= (2 << bit_offset);
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break;
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case 16:
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_regval &= ~(width << bit_offset);
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_regval |= (3 << bit_offset);
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break;
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case 20:
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_regval &= ~(width << bit_offset);
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_regval |= (4 << bit_offset);
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break;
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case 24:
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_regval &= ~(width << bit_offset);
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_regval |= (5 << bit_offset);
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break;
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case 28:
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_regval &= ~(width << bit_offset);
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_regval |= (6 << bit_offset);
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break;
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case 32:
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_regval &= ~(width << bit_offset);
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_regval |= (7 << bit_offset);
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break;
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default:
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return -EINVAL;
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}
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} else {
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switch (mA) {
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case 4:
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_regval &= ~(width << bit_offset);
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_regval |= (0 << bit_offset);
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break;
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case 8:
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_regval &= ~(width << bit_offset);
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_regval |= (1 << bit_offset);
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break;
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case 12:
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_regval &= ~(width << bit_offset);
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_regval |= (2 << bit_offset);
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break;
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case 16:
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_regval &= ~(width << bit_offset);
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_regval |= (3 << bit_offset);
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break;
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default:
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return -EINVAL;
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}
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}
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*regval = _regval;
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return 0;
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}
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static int bm1880_pinconf_drv_get(u32 width, u32 drv)
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{
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int ret = -ENOTSUPP;
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/*
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* There are two sets of drive strength bit width exposed by the
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* SoC at 4mA step, hence we need to handle them separately.
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*/
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if (width == 0x03) {
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switch (drv) {
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case 0:
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ret = 4;
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break;
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case 1:
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ret = 8;
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break;
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case 2:
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ret = 12;
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break;
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case 3:
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ret = 16;
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break;
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case 4:
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ret = 20;
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break;
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case 5:
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ret = 24;
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break;
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case 6:
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ret = 28;
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break;
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case 7:
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ret = 32;
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break;
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default:
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break;
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}
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} else {
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switch (drv) {
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case 0:
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ret = 4;
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break;
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case 1:
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ret = 8;
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break;
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case 2:
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ret = 12;
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break;
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case 3:
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ret = 16;
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break;
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default:
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break;
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}
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}
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return ret;
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}
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static int bm1880_pinconf_cfg_get(struct pinctrl_dev *pctldev,
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unsigned int pin,
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unsigned long *config)
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@ -889,6 +1153,7 @@ static int bm1880_pinconf_cfg_get(struct pinctrl_dev *pctldev,
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unsigned int param = pinconf_to_config_param(*config);
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unsigned int arg = 0;
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u32 regval, offset, bit_offset;
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int ret;
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offset = (pin >> 1) << 2;
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regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset);
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@ -914,6 +1179,15 @@ static int bm1880_pinconf_cfg_get(struct pinctrl_dev *pctldev,
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bit_offset = BM1880_PINCONF_SLEW(pin);
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arg = !!(regval & BIT(bit_offset));
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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bit_offset = BM1880_PINCONF_DRV(pin);
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ret = bm1880_pinconf_drv_get(pctrl->pinconf[pin].drv_bits,
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!!(regval & BIT(bit_offset)));
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if (ret < 0)
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return ret;
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arg = ret;
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break;
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default:
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return -ENOTSUPP;
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}
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@ -930,7 +1204,7 @@ static int bm1880_pinconf_cfg_set(struct pinctrl_dev *pctldev,
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{
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struct bm1880_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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u32 regval, offset, bit_offset;
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int i;
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int i, ret;
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offset = (pin >> 1) << 2;
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regval = readl_relaxed(pctrl->base + BM1880_REG_MUX + offset);
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@ -966,6 +1240,15 @@ static int bm1880_pinconf_cfg_set(struct pinctrl_dev *pctldev,
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else
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regval &= ~BIT(bit_offset);
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break;
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case PIN_CONFIG_DRIVE_STRENGTH:
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bit_offset = BM1880_PINCONF_DRV(pin);
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ret = bm1880_pinconf_drv_set(arg,
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pctrl->pinconf[pin].drv_bits,
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®val, bit_offset);
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if (ret < 0)
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return ret;
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break;
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default:
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dev_warn(pctldev->dev,
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"unsupported configuration parameter '%u'\n",
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@ -1041,6 +1324,7 @@ static int bm1880_pinctrl_probe(struct platform_device *pdev)
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pctrl->ngroups = ARRAY_SIZE(bm1880_pctrl_groups);
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pctrl->funcs = bm1880_pmux_functions;
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pctrl->nfuncs = ARRAY_SIZE(bm1880_pmux_functions);
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pctrl->pinconf = bm1880_pinconf;
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pctrl->pctrldev = devm_pinctrl_register(&pdev->dev, &bm1880_desc,
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pctrl);
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