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Allwinner DT changes for 4.15, take 2

Browse Source 
Two long awaited changes:
   - Reintroduction of the new EMAC DT bindings that got reverted at the
     last minute in 4.13
   - Introduction of the AXP803/813 PMIC support
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Merge tag 'sunxi-dt-for-4.15-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt

Pull "Allwinner DT changes for 4.15, take 2" from Maxime Ripard:

Here are a few commits that would be great to get in 4.15, given how
long they've been hanging around.

The first and most important one is the reintroduction of the EMAC DT
changes after they've been reverted at the last minute in 4.13.

There's a arm64 patch that crept in because the H5 and H3 share a
common DTSI that is located in arch/arm, and merging that patch
through the arm64 PR, especially given the pull requests that have
already been sent, would just have generated too many conflicts.

* tag 'sunxi-dt-for-4.15-2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  ARM: dts: sun8i: a711: Enable USB OTG
  ARM: dts: sun8i: a711: Add regulator support
  ARM: dts: sun8i: a83t: bananapi-m3: Enable AP6212 WiFi on mmc1
  ARM: dts: sun8i: a83t: cubietruck-plus: Enable AP6330 WiFi on mmc1
  ARM: dts: sun8i: a83t: Move mmc1 pinctrl setting to dtsi file
  ARM: dts: sun8i: a83t: allwinner-h8homlet-v2: Add AXP818 regulator nodes
  ARM: dts: sun8i: a83t: bananapi-m3: Add AXP813 regulator nodes
  ARM: dts: sun8i: a83t: cubietruck-plus: Add AXP818 regulator nodes
  ARM: dts: sunxi: Add dtsi for AXP81x PMIC
  arm64: dts: allwinner: H5: Restore EMAC changes
  ARM: dts: sunxi: Restore EMAC changes (boards)
  ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac
  arm: dts: sunxi: h3/h5: Restore EMAC changes
  dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
  dt-bindings: net: Restore sun8i dwmac binding
This commit is contained in:
Arnd Bergmann 2017-11-07 16:12:46 +01:00
commit 0b30cf2fb4
21 changed files with 1211 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

207
Documentation/devicetree/bindings/net/dwmac-sun8i.txt Normal file
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@ -0,0 +1,207 @@
* Allwinner sun8i GMAC ethernet controller
This device is a platform glue layer for stmmac.
Please see stmmac.txt for the other unchanged properties.
Required properties:
- compatible: must be one of the following string:
"allwinner,sun8i-a83t-emac"
"allwinner,sun8i-h3-emac"
"allwinner,sun8i-v3s-emac"
"allwinner,sun50i-a64-emac"
- reg: address and length of the register for the device.
- interrupts: interrupt for the device
- interrupt-names: must be "macirq"
- clocks: A phandle to the reference clock for this device
- clock-names: must be "stmmaceth"
- resets: A phandle to the reset control for this device
- reset-names: must be "stmmaceth"
- phy-mode: See ethernet.txt
- phy-handle: See ethernet.txt
- #address-cells: shall be 1
- #size-cells: shall be 0
- syscon: A phandle to the syscon of the SoC with one of the following
compatible string:
- allwinner,sun8i-h3-system-controller
- allwinner,sun8i-v3s-system-controller
- allwinner,sun50i-a64-system-controller
- allwinner,sun8i-a83t-system-controller
Optional properties:
- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)
- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)
Both delay properties need to be a multiple of 100. They control the delay for
external PHY.
Optional properties for the following compatibles:
- "allwinner,sun8i-h3-emac",
- "allwinner,sun8i-v3s-emac":
- allwinner,leds-active-low: EPHY LEDs are active low
Required child node of emac:
- mdio bus node: should be named mdio with compatible "snps,dwmac-mdio"
Required properties of the mdio node:
- #address-cells: shall be 1
- #size-cells: shall be 0
The device node referenced by "phy" or "phy-handle" must be a child node
of the mdio node. See phy.txt for the generic PHY bindings.
The following compatibles require that the emac node have a mdio-mux child
node called "mdio-mux":
- "allwinner,sun8i-h3-emac"
- "allwinner,sun8i-v3s-emac":
Required properties for the mdio-mux node:
- compatible = "allwinner,sun8i-h3-mdio-mux"
- mdio-parent-bus: a phandle to EMAC mdio
- one child mdio for the integrated mdio with the compatible
"allwinner,sun8i-h3-mdio-internal"
- one child mdio for the external mdio if present (V3s have none)
Required properties for the mdio-mux children node:
- reg: 1 for internal MDIO bus, 2 for external MDIO bus
The following compatibles require a PHY node representing the integrated
PHY, under the integrated MDIO bus node if an mdio-mux node is used:
- "allwinner,sun8i-h3-emac",
- "allwinner,sun8i-v3s-emac":
Additional information regarding generic multiplexer properties can be found
at Documentation/devicetree/bindings/net/mdio-mux.txt
Required properties of the integrated phy node:
- clocks: a phandle to the reference clock for the EPHY
- resets: a phandle to the reset control for the EPHY
- Must be a child of the integrated mdio
Example with integrated PHY:
emac: ethernet@1c0b000 {
compatible = "allwinner,sun8i-h3-emac";
syscon = <&syscon>;
reg = <0x01c0b000 0x104>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
};
mdio-mux {
compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux";
#address-cells = <1>;
#size-cells = <0>;
mdio-parent-bus = <&mdio>;
int_mdio: mdio@1 {
compatible = "allwinner,sun8i-h3-mdio-internal";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
int_mii_phy: ethernet-phy@1 {
reg = <1>;
clocks = <&ccu CLK_BUS_EPHY>;
resets = <&ccu RST_BUS_EPHY>;
phy-is-integrated;
};
};
ext_mdio: mdio@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
Example with external PHY:
emac: ethernet@1c0b000 {
compatible = "allwinner,sun8i-h3-emac";
syscon = <&syscon>;
reg = <0x01c0b000 0x104>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
allwinner,leds-active-low;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
};
mdio-mux {
compatible = "allwinner,sun8i-h3-mdio-mux";
#address-cells = <1>;
#size-cells = <0>;
mdio-parent-bus = <&mdio>;
int_mdio: mdio@1 {
compatible = "allwinner,sun8i-h3-mdio-internal";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
int_mii_phy: ethernet-phy@1 {
reg = <1>;
clocks = <&ccu CLK_BUS_EPHY>;
resets = <&ccu RST_BUS_EPHY>;
};
};
ext_mdio: mdio@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
ext_rgmii_phy: ethernet-phy@1 {
reg = <1>;
};
}:
};
};
Example with SoC without integrated PHY
emac: ethernet@1c0b000 {
compatible = "allwinner,sun8i-a83t-emac";
syscon = <&syscon>;
reg = <0x01c0b000 0x104>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
mdio: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ext_rgmii_phy: ethernet-phy@1 {
reg = <1>;
};
};
};

139
arch/arm/boot/dts/axp81x.dtsi Normal file
View File

@ -0,0 +1,139 @@
/*
* Copyright 2017 Chen-Yu Tsai
*
* Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/* AXP813/818 Integrated Power Management Chip */
&axp81x {
interrupt-controller;
#interrupt-cells = <1>;
regulators {
/* Default work frequency for buck regulators */
x-powers,dcdc-freq = <3000>;
reg_dcdc1: dcdc1 {
};
reg_dcdc2: dcdc2 {
};
reg_dcdc3: dcdc3 {
};
reg_dcdc4: dcdc4 {
};
reg_dcdc5: dcdc5 {
};
reg_dcdc6: dcdc6 {
};
reg_dcdc7: dcdc7 {
};
reg_aldo1: aldo1 {
};
reg_aldo2: aldo2 {
};
reg_aldo3: aldo3 {
};
reg_dldo1: dldo1 {
};
reg_dldo2: dldo2 {
};
reg_dldo3: dldo3 {
};
reg_dldo4: dldo4 {
};
reg_eldo1: eldo1 {
};
reg_eldo2: eldo2 {
};
reg_eldo3: eldo3 {
};
reg_fldo1: fldo1 {
};
reg_fldo2: fldo2 {
};
reg_fldo3: fldo3 {
};
reg_ldo_io0: ldo-io0 {
/* Disable by default to avoid conflicts with GPIO */
status = "disabled";
};
reg_ldo_io1: ldo-io1 {
/* Disable by default to avoid conflicts with GPIO */
status = "disabled";
};
reg_rtc_ldo: rtc-ldo {
/* RTC_LDO is a fixed, always-on regulator */
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_sw: sw {
};
reg_drivevbus: drivevbus {
status = "disabled";
};
};
};

147
arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
View File

@ -43,7 +43,8 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
@ -56,6 +57,26 @@
chosen {
stdout-path = "serial0:115200n8";
};
reg_usb0_vbus: reg-usb0-vbus {
compatible = "regulator-fixed";
regulator-name = "usb0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
enable-active-high;
gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
};
reg_usb1_vbus: reg-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
enable-active-high;
gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
};
};
&ehci0 {
@ -65,7 +86,7 @@
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_vcc3v0>;
vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
bus-width = <4>;
cd-inverted;
@ -75,7 +96,8 @@
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_emmc_pins>;
vmmc-supply = <&reg_vcc3v0>;
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
@ -86,16 +108,6 @@
status = "okay";
};
&reg_usb0_vbus {
gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
status = "okay";
};
&reg_usb1_vbus {
gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
status = "okay";
};
&r_rsb {
status = "okay";
@ -104,6 +116,8 @@
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
eldoin-supply = <&reg_dcdc1>;
swin-supply = <&reg_dcdc1>;
};
ac100: codec@e89 {
@ -131,6 +145,113 @@
};
};
#include "axp81x.dtsi"
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-1v8";
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dram-pll";
};
&reg_aldo3 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
&reg_dcdc1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3";
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpua";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpub";
};
&reg_dcdc4 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-gpu";
};
&reg_dcdc5 {
regulator-always-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc-dram";
};
&reg_dcdc6 {
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdd-sys";
};
&reg_dldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-mipi";
};
&reg_dldo4 {
/*
* The PHY requires 20ms after all voltages are applied until core
* logic is ready and 30ms after the reset pin is de-asserted.
* Set a 100ms delay to account for PMIC ramp time and board traces.
*/
regulator-enable-ramp-delay = <100000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-ephy";
};
&reg_fldo1 {
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1320000>;
regulator-name = "vdd12-hsic";
};
&reg_fldo2 {
/*
* Despite the embedded CPUs core not being used in any way,
* this must remain on or the system will hang.
*/
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpus";
};
&reg_rtc_ldo {
regulator-name = "vcc-rtc";
};
&reg_sw {
regulator-name = "vcc-wifi";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;

169
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
View File

@ -44,7 +44,6 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
@ -59,6 +58,27 @@
chosen {
stdout-path = "serial0:115200n8";
};
reg_usb1_vbus: reg-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
enable-active-high;
gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&ac100_rtc 1>;
clock-names = "ext_clock";
/* The WiFi low power clock must be 32768 Hz */
assigned-clocks = <&ac100_rtc 1>;
assigned-clock-rates = <32768>;
/* enables internal regulator and de-asserts reset */
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
};
};
&ehci0 {
@ -71,17 +91,35 @@
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_vcc3v3>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
cd-inverted;
status = "okay";
};
&mmc1 {
vmmc-supply = <&reg_dldo1>;
vqmmc-supply = <&reg_dldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&r_pio>;
interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_emmc_pins>;
vmmc-supply = <&reg_vcc3v3>;
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
@ -96,6 +134,10 @@
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
eldoin-supply = <&reg_dcdc1>;
fldoin-supply = <&reg_dcdc5>;
swin-supply = <&reg_dcdc1>;
x-powers,drive-vbus-en;
};
ac100: codec@e89 {
@ -123,17 +165,126 @@
};
};
&reg_usb1_vbus {
gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
#include "axp81x.dtsi"
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-1v8";
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dram-pll";
};
&reg_aldo3 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
&reg_dcdc1 {
/* schematics says 3.1V but FEX file says 3.3V */
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3";
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpua";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpub";
};
&reg_dcdc4 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-gpu";
};
&reg_dcdc5 {
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vcc-dram";
};
&reg_dcdc6 {
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdd-sys";
};
&reg_dldo1 {
/*
* This powers both the WiFi/BT module's main power, I/O supply,
* and external pull-ups on all the data lines. It should be set
* to the same voltage as the I/O supply (DCDC1 in this case) to
* avoid any leakage or mismatch.
*/
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi";
};
&reg_dldo3 {
regulator-always-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc-pd";
};
&reg_drivevbus {
regulator-name = "usb0-vbus";
status = "okay";
};
&reg_vcc3v0 {
status = "disabled";
&reg_fldo1 {
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1320000>;
regulator-name = "vdd12-hsic";
};
&reg_vcc5v0 {
status = "disabled";
&reg_fldo2 {
/*
* Despite the embedded CPUs core not being used in any way,
* this must remain on or the system will hang.
*/
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpus";
};
&reg_rtc_ldo {
regulator-name = "vcc-rtc";
};
&reg_sw {
/*
* The PHY requires 20ms after all voltages
* are applied until core logic is ready and
* 30ms after the reset pin is de-asserted.
* Set a 100ms delay to account for PMIC
* ramp time and board traces.
*/
regulator-enable-ramp-delay = <100000>;
regulator-name = "vcc-ephy";
};
&uart0 {

187
arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
View File

@ -44,7 +44,6 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
@ -95,6 +94,26 @@
refclk-frequency = <19200000>;
};
reg_usb1_vbus: reg-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
enable-active-high;
gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */
};
reg_usb2_vbus: reg-usb2-vbus {
compatible = "regulator-fixed";
regulator-name = "usb2-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
enable-active-high;
gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "On-board SPDIF";
@ -112,6 +131,17 @@
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&ac100_rtc 1>;
clock-names = "ext_clock";
/* The WiFi low power clock must be 32768 Hz */
assigned-clocks = <&ac100_rtc 1>;
assigned-clock-rates = <32768>;
/* enables internal regulator and de-asserts reset */
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
};
};
&ehci0 {
@ -127,17 +157,26 @@
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_vcc3v3>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
cd-inverted;
status = "okay";
};
&mmc1 {
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_sw>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_emmc_pins>;
vmmc-supply = <&reg_vcc3v3>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
@ -152,6 +191,9 @@
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
eldoin-supply = <&reg_dcdc1>;
swin-supply = <&reg_dcdc1>;
x-powers,drive-vbus-en;
};
ac100: codec@e89 {
@ -179,22 +221,143 @@
};
};
&reg_usb1_vbus {
gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */
#include "axp81x.dtsi"
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-1v8";
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dram-pll";
};
&reg_aldo3 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
&reg_dcdc1 {
/*
* The schematics say this should be 3.3V, but the FEX file says
* it should be 3V. The latter makes sense, as the WiFi module's
* I/O is indirectly powered from DCDC1, through SW. It is rated
* at 2.98V maximum.
*/
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-3v";
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpua";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpub";
};
&reg_dcdc4 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-gpu";
};
&reg_dcdc5 {
regulator-always-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc-dram";
};
&reg_dcdc6 {
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdd-sys";
};
&reg_dldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "dp-pwr";
};
&reg_dldo3 {
regulator-always-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "ephy-io";
};
&reg_dldo4 {
/*
* The PHY requires 20ms after all voltages are applied until core
* logic is ready and 30ms after the reset pin is de-asserted.
* Set a 100ms delay to account for PMIC ramp time and board traces.
*/
regulator-enable-ramp-delay = <100000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "ephy";
};
&reg_drivevbus {
regulator-name = "usb0-vbus";
status = "okay";
};
&reg_usb2_vbus {
gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
status = "okay";
&reg_eldo1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "dp-bridge-1";
};
&reg_vcc3v0 {
status = "disabled";
&reg_eldo2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "dp-bridge-2";
};
&reg_vcc5v0 {
status = "disabled";
&reg_fldo1 {
/* TODO should be handled by USB PHY */
regulator-always-on;
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1320000>;
regulator-name = "vdd12-hsic";
};
&reg_fldo2 {
/*
* Despite the embedded CPUs core not being used in any way,
* this must remain on or the system will hang.
*/
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpus";
};
&reg_rtc_ldo {
regulator-name = "vcc-rtc";
};
&reg_sw {
regulator-name = "vcc-wifi-io";
};
&spdif {

176
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
View File

@ -43,7 +43,8 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
#include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "TBS A711 Tablet";
@ -105,7 +106,7 @@
};
&mmc0 {
vmmc-supply = <&reg_vcc3v3>;
vmmc-supply = <&reg_dcdc1>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
@ -115,10 +116,8 @@
&mmc1 {
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc3v3>;
vmmc-supply = <&reg_dldo1>;
vqmmc-supply = <&reg_dldo1>;
non-removable;
wakeup-source;
status = "okay";
@ -135,8 +134,8 @@
&mmc2 {
pinctrl-0 = <&mmc2_8bit_emmc_pins>;
pinctrl-names = "default";
vmmc-supply = <&reg_vcc3v3>;
vqmmc-supply = <&reg_vcc3v3>;
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
@ -146,11 +145,12 @@
&r_rsb {
status = "okay";
axp813: pmic@3a3 {
compatible = "x-powers,axp813";
axp81x: pmic@3a3 {
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
swin-supply = <&reg_dcdc1>;
x-powers,drive-vbus-en;
};
ac100: codec@e89 {
@ -179,6 +179,149 @@
};
#include "axp81x.dtsi"
&reg_aldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-1.8";
};
&reg_aldo2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-name = "vdd-drampll";
};
&reg_aldo3 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-name = "avcc";
};
&reg_dcdc1 {
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
regulator-always-on;
regulator-name = "vcc-io";
};
&reg_dcdc2 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-name = "vdd-cpu-A";
};
&reg_dcdc3 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-name = "vdd-cpu-B";
};
&reg_dcdc4 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-gpu";
};
&reg_dcdc5 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-name = "vcc-dram";
};
&reg_dcdc6 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
regulator-name = "vdd-sys";
};
&reg_dldo1 {
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
regulator-name = "vcc-wifi-io";
};
&reg_dldo2 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <4200000>;
regulator-name = "vcc-mipi";
};
&reg_dldo3 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vdd-csi";
};
&reg_dldo4 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "avdd-csi";
};
&reg_drivevbus {
regulator-name = "usb0-vbus";
status = "okay";
};
&reg_eldo1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dvdd-csi-r";
};
&reg_eldo2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-dsi";
};
&reg_eldo3 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dvdd-csi-f";
};
&reg_fldo1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vcc-hsic";
};
&reg_fldo2 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-name = "vdd-cpus";
};
&reg_ldo_io0 {
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
regulator-name = "vcc-ctp";
status = "okay";
};
&reg_ldo_io1 {
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
regulator-name = "vcc-vb";
status = "okay";
};
&reg_sw {
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
regulator-name = "vcc-lcd";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
@ -192,8 +335,15 @@
status = "okay";
};
&usbphy {
usb1_vbus_supply = <&reg_vcc5v0>;
usb2_vbus_supply = <&reg_vcc5v0>;
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
usb0_vbus-supply = <&reg_drivevbus>;
usb1_vbus_supply = <&reg_vmain>;
usb2_vbus_supply = <&reg_vmain>;
status = "okay";
};

2
arch/arm/boot/dts/sun8i-a83t.dtsi
View File

@ -212,6 +212,8 @@
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;

9
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
View File

@ -56,6 +56,8 @@
aliases {
serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
ethernet0 = &emac;
ethernet1 = &xr819;
};
@ -102,6 +104,13 @@
status = "okay";
};
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>;

19
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
View File

@ -52,6 +52,7 @@
compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
};
@ -111,6 +112,24 @@
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
allwinner,leds-active-low;
status = "okay";
};
&external_mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;

29
arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
View File

@ -51,6 +51,16 @@
ethernet1 = &sdio_wifi;
};
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
regulator-name = "gmac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <100000>;
enable-active-high;
gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
@ -66,6 +76,25 @@
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
allwinner,leds-active-low;
status = "okay";
};
&external_mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
};
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;

7
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
View File

@ -46,3 +46,10 @@
model = "FriendlyARM NanoPi NEO";
compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
};
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};

8
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
View File

@ -54,6 +54,7 @@
aliases {
serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
ethernet0 = &emac;
ethernet1 = &rtl8189;
};
@ -117,6 +118,13 @@
status = "okay";
};
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;

8
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
View File

@ -52,6 +52,7 @@
compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
@ -97,6 +98,13 @@
status = "okay";
};
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;

5
arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
View File

@ -53,6 +53,11 @@
};
};
&emac {
/* LEDs changed to active high on the plus */
/delete-property/ allwinner,leds-active-low;
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins_a>;

8
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
View File

@ -52,6 +52,7 @@
compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
@ -113,6 +114,13 @@
status = "okay";
};
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;

22
arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
View File

@ -47,6 +47,10 @@
model = "Xunlong Orange Pi Plus / Plus 2";
compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
aliases {
ethernet0 = &emac;
};
reg_gmac_3v3: gmac-3v3 {
compatible = "regulator-fixed";
regulator-name = "gmac-3v3";
@ -74,6 +78,24 @@
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
allwinner,leds-active-low;
status = "okay";
};
&external_mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_pins>;

16
arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
View File

@ -61,3 +61,19 @@
gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
};
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
status = "okay";
};
&external_mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};

49
arch/arm/boot/dts/sunxi-h3-h5.dtsi
View File

@ -396,6 +396,55 @@
clocks = <&osc24M>;
};
emac: ethernet@1c30000 {
compatible = "allwinner,sun8i-h3-emac";
syscon = <&syscon>;
reg = <0x01c30000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
resets = <&ccu RST_BUS_EMAC>;
reset-names = "stmmaceth";
clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
};
mdio-mux {
compatible = "allwinner,sun8i-h3-mdio-mux";
#address-cells = <1>;
#size-cells = <0>;
mdio-parent-bus = <&mdio>;
/* Only one MDIO is usable at the time */
internal_mdio: mdio@1 {
compatible = "allwinner,sun8i-h3-mdio-internal";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
int_mii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
clocks = <&ccu CLK_BUS_EPHY>;
resets = <&ccu RST_BUS_EPHY>;
};
};
external_mdio: mdio@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
spi0: spi@1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;

17
arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
View File

@ -50,6 +50,7 @@
compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
@ -108,6 +109,22 @@
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
status = "okay";
};
&external_mdio {
ext_rgmii_phy: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;

17
arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
View File

@ -59,6 +59,7 @@
};
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
@ -136,6 +137,22 @@
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
status = "okay";
};
&external_mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;

17
arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
View File

@ -54,6 +54,7 @@
compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
@ -143,6 +144,22 @@
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
status = "okay";
};
&external_mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;