2012-05-22 02:50:07 +00:00
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#define pr_fmt(fmt) "SMP alternatives: " fmt
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2006-03-23 10:59:32 +00:00
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#include <linux/module.h>
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2006-10-18 05:47:25 +00:00
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#include <linux/sched.h>
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2008-05-12 19:21:01 +00:00
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#include <linux/mutex.h>
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2006-03-23 10:59:32 +00:00
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#include <linux/list.h>
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2009-08-19 07:40:48 +00:00
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#include <linux/stringify.h>
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2007-07-22 09:12:31 +00:00
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#include <linux/mm.h>
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#include <linux/vmalloc.h>
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2009-03-06 15:37:22 +00:00
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#include <linux/memory.h>
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2010-02-25 13:34:38 +00:00
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#include <linux/stop_machine.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2013-07-12 09:21:48 +00:00
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#include <linux/kdebug.h>
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2006-03-23 10:59:32 +00:00
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#include <asm/alternative.h>
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#include <asm/sections.h>
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2007-07-22 09:12:31 +00:00
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#include <asm/pgtable.h>
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2007-07-22 09:12:32 +00:00
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#include <asm/mce.h>
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#include <asm/nmi.h>
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2008-03-06 13:48:49 +00:00
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#include <asm/cacheflush.h>
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2009-03-06 15:37:54 +00:00
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#include <asm/tlbflush.h>
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2008-03-06 13:48:49 +00:00
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#include <asm/io.h>
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2009-03-06 15:37:54 +00:00
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#include <asm/fixmap.h>
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2006-03-23 10:59:32 +00:00
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2007-08-10 20:31:03 +00:00
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#define MAX_PATCH_LEN (255-1)
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2009-08-19 07:40:48 +00:00
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static int __initdata_or_module debug_alternative;
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2007-05-02 17:27:13 +00:00
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2006-06-26 11:56:16 +00:00
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static int __init debug_alt(char *str)
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{
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debug_alternative = 1;
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return 1;
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}
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__setup("debug-alternative", debug_alt);
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2007-07-21 15:10:25 +00:00
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static int noreplace_smp;
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2007-05-02 17:27:13 +00:00
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static int __init setup_noreplace_smp(char *str)
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{
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noreplace_smp = 1;
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return 1;
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}
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__setup("noreplace-smp", setup_noreplace_smp);
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2007-05-02 17:27:16 +00:00
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#ifdef CONFIG_PARAVIRT
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2009-08-19 07:40:48 +00:00
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static int __initdata_or_module noreplace_paravirt = 0;
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2007-05-02 17:27:16 +00:00
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static int __init setup_noreplace_paravirt(char *str)
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{
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noreplace_paravirt = 1;
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return 1;
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}
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__setup("noreplace-paravirt", setup_noreplace_paravirt);
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#endif
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2007-05-02 17:27:13 +00:00
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2014-12-30 19:27:09 +00:00
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#define DPRINTK(fmt, args...) \
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do { \
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if (debug_alternative) \
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printk(KERN_DEBUG "%s: " fmt "\n", __func__, ##args); \
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2012-05-22 02:50:07 +00:00
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} while (0)
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2006-06-26 11:56:16 +00:00
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x86/alternatives: Make JMPs more robust
Up until now we had to pay attention to relative JMPs in alternatives
about how their relative offset gets computed so that the jump target
is still correct. Or, as it is the case for near CALLs (opcode e8), we
still have to go and readjust the offset at patching time.
What is more, the static_cpu_has_safe() facility had to forcefully
generate 5-byte JMPs since we couldn't rely on the compiler to generate
properly sized ones so we had to force the longest ones. Worse than
that, sometimes it would generate a replacement JMP which is longer than
the original one, thus overwriting the beginning of the next instruction
at patching time.
So, in order to alleviate all that and make using JMPs more
straight-forward we go and pad the original instruction in an
alternative block with NOPs at build time, should the replacement(s) be
longer. This way, alternatives users shouldn't pay special attention
so that original and replacement instruction sizes are fine but the
assembler would simply add padding where needed and not do anything
otherwise.
As a second aspect, we go and recompute JMPs at patching time so that we
can try to make 5-byte JMPs into two-byte ones if possible. If not, we
still have to recompute the offsets as the replacement JMP gets put far
away in the .altinstr_replacement section leading to a wrong offset if
copied verbatim.
For example, on a locally generated kernel image
old insn VA: 0xffffffff810014bd, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff810014bd: eb 21 jmp ffffffff810014e0
repl insn: size: 5
ffffffff81d0b23c: e9 b1 62 2f ff jmpq ffffffff810014f2
gets corrected to a 2-byte JMP:
apply_alternatives: feat: 3*32+21, old: (ffffffff810014bd, len: 2), repl: (ffffffff81d0b23c, len: 5)
alt_insn: e9 b1 62 2f ff
recompute_jumps: next_rip: ffffffff81d0b241, tgt_rip: ffffffff810014f2, new_displ: 0x00000033, ret len: 2
converted to: eb 33 90 90 90
and a 5-byte JMP:
old insn VA: 0xffffffff81001516, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff81001516: eb 30 jmp ffffffff81001548
repl insn: size: 5
ffffffff81d0b241: e9 10 63 2f ff jmpq ffffffff81001556
gets shortened into a two-byte one:
apply_alternatives: feat: 3*32+21, old: (ffffffff81001516, len: 2), repl: (ffffffff81d0b241, len: 5)
alt_insn: e9 10 63 2f ff
recompute_jumps: next_rip: ffffffff81d0b246, tgt_rip: ffffffff81001556, new_displ: 0x0000003e, ret len: 2
converted to: eb 3e 90 90 90
... and so on.
This leads to a net win of around
40ish replacements * 3 bytes savings =~ 120 bytes of I$
on an AMD guest which means some savings of precious instruction cache
bandwidth. The padding to the shorter 2-byte JMPs are single-byte NOPs
which on smart microarchitectures means discarding NOPs at decode time
and thus freeing up execution bandwidth.
Signed-off-by: Borislav Petkov <bp@suse.de>
2015-01-05 12:48:41 +00:00
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#define DUMP_BYTES(buf, len, fmt, args...) \
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do { \
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if (unlikely(debug_alternative)) { \
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int j; \
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\
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if (!(len)) \
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break; \
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\
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printk(KERN_DEBUG fmt, ##args); \
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for (j = 0; j < (len) - 1; j++) \
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printk(KERN_CONT "%02hhx ", buf[j]); \
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printk(KERN_CONT "%02hhx\n", buf[j]); \
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} \
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} while (0)
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2011-04-18 22:19:51 +00:00
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/*
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* Each GENERIC_NOPX is of X bytes, and defined as an array of bytes
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* that correspond to that nop. Getting from one nop to the next, we
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* add to the array the offset that is equal to the sum of all sizes of
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* nops preceding the one we are after.
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*
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* Note: The GENERIC_NOP5_ATOMIC is at the end, as it breaks the
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* nice symmetry of sizes of the previous nops.
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*/
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2009-08-19 07:40:48 +00:00
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#if defined(GENERIC_NOP1) && !defined(CONFIG_X86_64)
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2011-04-18 22:19:51 +00:00
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static const unsigned char intelnops[] =
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{
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GENERIC_NOP1,
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GENERIC_NOP2,
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GENERIC_NOP3,
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GENERIC_NOP4,
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GENERIC_NOP5,
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GENERIC_NOP6,
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GENERIC_NOP7,
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GENERIC_NOP8,
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GENERIC_NOP5_ATOMIC
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};
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static const unsigned char * const intel_nops[ASM_NOP_MAX+2] =
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{
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2006-03-23 10:59:32 +00:00
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NULL,
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intelnops,
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intelnops + 1,
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intelnops + 1 + 2,
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intelnops + 1 + 2 + 3,
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intelnops + 1 + 2 + 3 + 4,
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intelnops + 1 + 2 + 3 + 4 + 5,
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intelnops + 1 + 2 + 3 + 4 + 5 + 6,
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intelnops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
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2011-04-18 22:19:51 +00:00
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intelnops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
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2006-03-23 10:59:32 +00:00
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};
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2006-06-26 11:56:16 +00:00
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#endif
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#ifdef K8_NOP1
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2011-04-18 22:19:51 +00:00
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static const unsigned char k8nops[] =
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{
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K8_NOP1,
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K8_NOP2,
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K8_NOP3,
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K8_NOP4,
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K8_NOP5,
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K8_NOP6,
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K8_NOP7,
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K8_NOP8,
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K8_NOP5_ATOMIC
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};
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static const unsigned char * const k8_nops[ASM_NOP_MAX+2] =
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{
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2006-03-23 10:59:32 +00:00
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NULL,
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k8nops,
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k8nops + 1,
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k8nops + 1 + 2,
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k8nops + 1 + 2 + 3,
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k8nops + 1 + 2 + 3 + 4,
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k8nops + 1 + 2 + 3 + 4 + 5,
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k8nops + 1 + 2 + 3 + 4 + 5 + 6,
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k8nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
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2011-04-18 22:19:51 +00:00
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k8nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
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2006-03-23 10:59:32 +00:00
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};
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2006-06-26 11:56:16 +00:00
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#endif
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2009-08-19 07:40:48 +00:00
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#if defined(K7_NOP1) && !defined(CONFIG_X86_64)
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2011-04-18 22:19:51 +00:00
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static const unsigned char k7nops[] =
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{
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K7_NOP1,
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K7_NOP2,
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K7_NOP3,
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K7_NOP4,
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K7_NOP5,
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K7_NOP6,
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K7_NOP7,
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K7_NOP8,
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K7_NOP5_ATOMIC
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};
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static const unsigned char * const k7_nops[ASM_NOP_MAX+2] =
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{
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2006-03-23 10:59:32 +00:00
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NULL,
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k7nops,
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k7nops + 1,
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k7nops + 1 + 2,
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k7nops + 1 + 2 + 3,
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k7nops + 1 + 2 + 3 + 4,
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k7nops + 1 + 2 + 3 + 4 + 5,
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k7nops + 1 + 2 + 3 + 4 + 5 + 6,
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k7nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
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2011-04-18 22:19:51 +00:00
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k7nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
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2006-03-23 10:59:32 +00:00
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};
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2006-06-26 11:56:16 +00:00
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#endif
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2007-10-17 16:04:41 +00:00
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#ifdef P6_NOP1
|
2012-08-22 10:03:48 +00:00
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static const unsigned char p6nops[] =
|
2011-04-18 22:19:51 +00:00
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{
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P6_NOP1,
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P6_NOP2,
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P6_NOP3,
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P6_NOP4,
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P6_NOP5,
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P6_NOP6,
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P6_NOP7,
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P6_NOP8,
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P6_NOP5_ATOMIC
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};
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static const unsigned char * const p6_nops[ASM_NOP_MAX+2] =
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{
|
2007-10-17 16:04:41 +00:00
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NULL,
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p6nops,
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p6nops + 1,
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p6nops + 1 + 2,
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p6nops + 1 + 2 + 3,
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p6nops + 1 + 2 + 3 + 4,
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p6nops + 1 + 2 + 3 + 4 + 5,
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p6nops + 1 + 2 + 3 + 4 + 5 + 6,
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p6nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
|
2011-04-18 22:19:51 +00:00
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p6nops + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8,
|
2007-10-17 16:04:41 +00:00
|
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};
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#endif
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|
2011-04-18 22:19:51 +00:00
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/* Initialize these to a safe default */
|
2006-06-26 11:56:16 +00:00
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#ifdef CONFIG_X86_64
|
2011-04-18 22:19:51 +00:00
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const unsigned char * const *ideal_nops = p6_nops;
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#else
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const unsigned char * const *ideal_nops = intel_nops;
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#endif
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2006-06-26 11:56:16 +00:00
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2011-04-18 22:19:51 +00:00
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|
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void __init arch_init_ideal_nops(void)
|
2006-06-26 11:56:16 +00:00
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{
|
2011-04-18 22:19:51 +00:00
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_INTEL:
|
2011-04-18 22:31:57 +00:00
|
|
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/*
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|
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* Due to a decoder implementation quirk, some
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* specific Intel CPUs actually perform better with
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* the "k8_nops" than with the SDM-recommended NOPs.
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*/
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if (boot_cpu_data.x86 == 6 &&
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boot_cpu_data.x86_model >= 0x0f &&
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boot_cpu_data.x86_model != 0x1c &&
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boot_cpu_data.x86_model != 0x26 &&
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boot_cpu_data.x86_model != 0x27 &&
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boot_cpu_data.x86_model < 0x30) {
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ideal_nops = k8_nops;
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|
} else if (boot_cpu_has(X86_FEATURE_NOPL)) {
|
2011-04-18 22:19:51 +00:00
|
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ideal_nops = p6_nops;
|
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|
} else {
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|
#ifdef CONFIG_X86_64
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ideal_nops = k8_nops;
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|
#else
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|
ideal_nops = intel_nops;
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|
#endif
|
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|
}
|
2012-07-25 15:28:19 +00:00
|
|
|
break;
|
2011-04-18 22:19:51 +00:00
|
|
|
default:
|
|
|
|
#ifdef CONFIG_X86_64
|
|
|
|
ideal_nops = k8_nops;
|
|
|
|
#else
|
|
|
|
if (boot_cpu_has(X86_FEATURE_K8))
|
|
|
|
ideal_nops = k8_nops;
|
|
|
|
else if (boot_cpu_has(X86_FEATURE_K7))
|
|
|
|
ideal_nops = k7_nops;
|
|
|
|
else
|
|
|
|
ideal_nops = intel_nops;
|
|
|
|
#endif
|
|
|
|
}
|
2006-03-23 10:59:32 +00:00
|
|
|
}
|
|
|
|
|
2007-08-10 20:31:03 +00:00
|
|
|
/* Use this to add nops to a buffer, then text_poke the whole buffer. */
|
2009-08-19 07:40:48 +00:00
|
|
|
static void __init_or_module add_nops(void *insns, unsigned int len)
|
2006-12-07 01:14:08 +00:00
|
|
|
{
|
|
|
|
while (len > 0) {
|
|
|
|
unsigned int noplen = len;
|
|
|
|
if (noplen > ASM_NOP_MAX)
|
|
|
|
noplen = ASM_NOP_MAX;
|
2011-04-18 22:19:51 +00:00
|
|
|
memcpy(insns, ideal_nops[noplen], noplen);
|
2006-12-07 01:14:08 +00:00
|
|
|
insns += noplen;
|
|
|
|
len -= noplen;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-06-26 11:56:16 +00:00
|
|
|
extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
|
2010-04-21 15:08:14 +00:00
|
|
|
extern s32 __smp_locks[], __smp_locks_end[];
|
2010-09-17 15:08:56 +00:00
|
|
|
void *text_poke_early(void *addr, const void *opcode, size_t len);
|
2006-06-26 11:56:16 +00:00
|
|
|
|
x86/alternatives: Make JMPs more robust
Up until now we had to pay attention to relative JMPs in alternatives
about how their relative offset gets computed so that the jump target
is still correct. Or, as it is the case for near CALLs (opcode e8), we
still have to go and readjust the offset at patching time.
What is more, the static_cpu_has_safe() facility had to forcefully
generate 5-byte JMPs since we couldn't rely on the compiler to generate
properly sized ones so we had to force the longest ones. Worse than
that, sometimes it would generate a replacement JMP which is longer than
the original one, thus overwriting the beginning of the next instruction
at patching time.
So, in order to alleviate all that and make using JMPs more
straight-forward we go and pad the original instruction in an
alternative block with NOPs at build time, should the replacement(s) be
longer. This way, alternatives users shouldn't pay special attention
so that original and replacement instruction sizes are fine but the
assembler would simply add padding where needed and not do anything
otherwise.
As a second aspect, we go and recompute JMPs at patching time so that we
can try to make 5-byte JMPs into two-byte ones if possible. If not, we
still have to recompute the offsets as the replacement JMP gets put far
away in the .altinstr_replacement section leading to a wrong offset if
copied verbatim.
For example, on a locally generated kernel image
old insn VA: 0xffffffff810014bd, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff810014bd: eb 21 jmp ffffffff810014e0
repl insn: size: 5
ffffffff81d0b23c: e9 b1 62 2f ff jmpq ffffffff810014f2
gets corrected to a 2-byte JMP:
apply_alternatives: feat: 3*32+21, old: (ffffffff810014bd, len: 2), repl: (ffffffff81d0b23c, len: 5)
alt_insn: e9 b1 62 2f ff
recompute_jumps: next_rip: ffffffff81d0b241, tgt_rip: ffffffff810014f2, new_displ: 0x00000033, ret len: 2
converted to: eb 33 90 90 90
and a 5-byte JMP:
old insn VA: 0xffffffff81001516, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff81001516: eb 30 jmp ffffffff81001548
repl insn: size: 5
ffffffff81d0b241: e9 10 63 2f ff jmpq ffffffff81001556
gets shortened into a two-byte one:
apply_alternatives: feat: 3*32+21, old: (ffffffff81001516, len: 2), repl: (ffffffff81d0b241, len: 5)
alt_insn: e9 10 63 2f ff
recompute_jumps: next_rip: ffffffff81d0b246, tgt_rip: ffffffff81001556, new_displ: 0x0000003e, ret len: 2
converted to: eb 3e 90 90 90
... and so on.
This leads to a net win of around
40ish replacements * 3 bytes savings =~ 120 bytes of I$
on an AMD guest which means some savings of precious instruction cache
bandwidth. The padding to the shorter 2-byte JMPs are single-byte NOPs
which on smart microarchitectures means discarding NOPs at decode time
and thus freeing up execution bandwidth.
Signed-off-by: Borislav Petkov <bp@suse.de>
2015-01-05 12:48:41 +00:00
|
|
|
/*
|
|
|
|
* Are we looking at a near JMP with a 1 or 4-byte displacement.
|
|
|
|
*/
|
|
|
|
static inline bool is_jmp(const u8 opcode)
|
|
|
|
{
|
|
|
|
return opcode == 0xeb || opcode == 0xe9;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __init_or_module
|
|
|
|
recompute_jump(struct alt_instr *a, u8 *orig_insn, u8 *repl_insn, u8 *insnbuf)
|
|
|
|
{
|
|
|
|
u8 *next_rip, *tgt_rip;
|
|
|
|
s32 n_dspl, o_dspl;
|
|
|
|
int repl_len;
|
|
|
|
|
|
|
|
if (a->replacementlen != 5)
|
|
|
|
return;
|
|
|
|
|
|
|
|
o_dspl = *(s32 *)(insnbuf + 1);
|
|
|
|
|
|
|
|
/* next_rip of the replacement JMP */
|
|
|
|
next_rip = repl_insn + a->replacementlen;
|
|
|
|
/* target rip of the replacement JMP */
|
|
|
|
tgt_rip = next_rip + o_dspl;
|
|
|
|
n_dspl = tgt_rip - orig_insn;
|
|
|
|
|
|
|
|
DPRINTK("target RIP: %p, new_displ: 0x%x", tgt_rip, n_dspl);
|
|
|
|
|
|
|
|
if (tgt_rip - orig_insn >= 0) {
|
|
|
|
if (n_dspl - 2 <= 127)
|
|
|
|
goto two_byte_jmp;
|
|
|
|
else
|
|
|
|
goto five_byte_jmp;
|
|
|
|
/* negative offset */
|
|
|
|
} else {
|
|
|
|
if (((n_dspl - 2) & 0xff) == (n_dspl - 2))
|
|
|
|
goto two_byte_jmp;
|
|
|
|
else
|
|
|
|
goto five_byte_jmp;
|
|
|
|
}
|
|
|
|
|
|
|
|
two_byte_jmp:
|
|
|
|
n_dspl -= 2;
|
|
|
|
|
|
|
|
insnbuf[0] = 0xeb;
|
|
|
|
insnbuf[1] = (s8)n_dspl;
|
|
|
|
add_nops(insnbuf + 2, 3);
|
|
|
|
|
|
|
|
repl_len = 2;
|
|
|
|
goto done;
|
|
|
|
|
|
|
|
five_byte_jmp:
|
|
|
|
n_dspl -= 5;
|
|
|
|
|
|
|
|
insnbuf[0] = 0xe9;
|
|
|
|
*(s32 *)&insnbuf[1] = n_dspl;
|
|
|
|
|
|
|
|
repl_len = 5;
|
|
|
|
|
|
|
|
done:
|
|
|
|
|
|
|
|
DPRINTK("final displ: 0x%08x, JMP 0x%lx",
|
|
|
|
n_dspl, (unsigned long)orig_insn + n_dspl + repl_len);
|
|
|
|
}
|
|
|
|
|
2015-01-10 19:34:07 +00:00
|
|
|
static void __init_or_module optimize_nops(struct alt_instr *a, u8 *instr)
|
|
|
|
{
|
2015-04-04 21:07:42 +00:00
|
|
|
if (instr[0] != 0x90)
|
|
|
|
return;
|
|
|
|
|
2015-01-10 19:34:07 +00:00
|
|
|
add_nops(instr + (a->instrlen - a->padlen), a->padlen);
|
|
|
|
|
|
|
|
DUMP_BYTES(instr, a->instrlen, "%p: [%d:%d) optimized NOPs: ",
|
|
|
|
instr, a->instrlen - a->padlen, a->padlen);
|
|
|
|
}
|
|
|
|
|
2014-12-30 19:27:09 +00:00
|
|
|
/*
|
|
|
|
* Replace instructions with better alternatives for this CPU type. This runs
|
|
|
|
* before SMP is initialized to avoid SMP problems with self modifying code.
|
|
|
|
* This implies that asymmetric systems where APs have less capabilities than
|
|
|
|
* the boot processor are not handled. Tough. Make sure you disable such
|
|
|
|
* features by hand.
|
|
|
|
*/
|
2009-08-19 07:40:48 +00:00
|
|
|
void __init_or_module apply_alternatives(struct alt_instr *start,
|
|
|
|
struct alt_instr *end)
|
2006-03-23 10:59:32 +00:00
|
|
|
{
|
|
|
|
struct alt_instr *a;
|
2011-07-13 13:24:10 +00:00
|
|
|
u8 *instr, *replacement;
|
2009-12-18 16:12:56 +00:00
|
|
|
u8 insnbuf[MAX_PATCH_LEN];
|
2006-03-23 10:59:32 +00:00
|
|
|
|
2014-12-30 19:27:09 +00:00
|
|
|
DPRINTK("alt table %p -> %p", start, end);
|
2011-05-17 22:29:12 +00:00
|
|
|
/*
|
|
|
|
* The scan order should be from start to end. A later scanned
|
2014-12-30 19:27:09 +00:00
|
|
|
* alternative code can overwrite previously scanned alternative code.
|
2011-05-17 22:29:12 +00:00
|
|
|
* Some kernel functions (e.g. memcpy, memset, etc) use this order to
|
|
|
|
* patch code.
|
|
|
|
*
|
|
|
|
* So be careful if you want to change the scan order to any other
|
|
|
|
* order.
|
|
|
|
*/
|
2006-03-23 10:59:32 +00:00
|
|
|
for (a = start; a < end; a++) {
|
x86/alternatives: Make JMPs more robust
Up until now we had to pay attention to relative JMPs in alternatives
about how their relative offset gets computed so that the jump target
is still correct. Or, as it is the case for near CALLs (opcode e8), we
still have to go and readjust the offset at patching time.
What is more, the static_cpu_has_safe() facility had to forcefully
generate 5-byte JMPs since we couldn't rely on the compiler to generate
properly sized ones so we had to force the longest ones. Worse than
that, sometimes it would generate a replacement JMP which is longer than
the original one, thus overwriting the beginning of the next instruction
at patching time.
So, in order to alleviate all that and make using JMPs more
straight-forward we go and pad the original instruction in an
alternative block with NOPs at build time, should the replacement(s) be
longer. This way, alternatives users shouldn't pay special attention
so that original and replacement instruction sizes are fine but the
assembler would simply add padding where needed and not do anything
otherwise.
As a second aspect, we go and recompute JMPs at patching time so that we
can try to make 5-byte JMPs into two-byte ones if possible. If not, we
still have to recompute the offsets as the replacement JMP gets put far
away in the .altinstr_replacement section leading to a wrong offset if
copied verbatim.
For example, on a locally generated kernel image
old insn VA: 0xffffffff810014bd, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff810014bd: eb 21 jmp ffffffff810014e0
repl insn: size: 5
ffffffff81d0b23c: e9 b1 62 2f ff jmpq ffffffff810014f2
gets corrected to a 2-byte JMP:
apply_alternatives: feat: 3*32+21, old: (ffffffff810014bd, len: 2), repl: (ffffffff81d0b23c, len: 5)
alt_insn: e9 b1 62 2f ff
recompute_jumps: next_rip: ffffffff81d0b241, tgt_rip: ffffffff810014f2, new_displ: 0x00000033, ret len: 2
converted to: eb 33 90 90 90
and a 5-byte JMP:
old insn VA: 0xffffffff81001516, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff81001516: eb 30 jmp ffffffff81001548
repl insn: size: 5
ffffffff81d0b241: e9 10 63 2f ff jmpq ffffffff81001556
gets shortened into a two-byte one:
apply_alternatives: feat: 3*32+21, old: (ffffffff81001516, len: 2), repl: (ffffffff81d0b241, len: 5)
alt_insn: e9 10 63 2f ff
recompute_jumps: next_rip: ffffffff81d0b246, tgt_rip: ffffffff81001556, new_displ: 0x0000003e, ret len: 2
converted to: eb 3e 90 90 90
... and so on.
This leads to a net win of around
40ish replacements * 3 bytes savings =~ 120 bytes of I$
on an AMD guest which means some savings of precious instruction cache
bandwidth. The padding to the shorter 2-byte JMPs are single-byte NOPs
which on smart microarchitectures means discarding NOPs at decode time
and thus freeing up execution bandwidth.
Signed-off-by: Borislav Petkov <bp@suse.de>
2015-01-05 12:48:41 +00:00
|
|
|
int insnbuf_sz = 0;
|
|
|
|
|
2011-07-13 13:24:10 +00:00
|
|
|
instr = (u8 *)&a->instr_offset + a->instr_offset;
|
|
|
|
replacement = (u8 *)&a->repl_offset + a->repl_offset;
|
2007-08-10 20:31:03 +00:00
|
|
|
BUG_ON(a->instrlen > sizeof(insnbuf));
|
2013-03-20 14:07:23 +00:00
|
|
|
BUG_ON(a->cpuid >= (NCAPINTS + NBUGINTS) * 32);
|
2015-01-10 19:34:07 +00:00
|
|
|
if (!boot_cpu_has(a->cpuid)) {
|
|
|
|
if (a->padlen > 1)
|
|
|
|
optimize_nops(a, instr);
|
|
|
|
|
2006-03-23 10:59:32 +00:00
|
|
|
continue;
|
2015-01-10 19:34:07 +00:00
|
|
|
}
|
2011-07-13 13:24:10 +00:00
|
|
|
|
x86/alternatives: Fix ALTERNATIVE_2 padding generation properly
Quentin caught a corner case with the generation of instruction
padding in the ALTERNATIVE_2 macro: if len(orig_insn) <
len(alt1) < len(alt2), then not enough padding gets added and
that is not good(tm) as we could overwrite the beginning of the
next instruction.
Luckily, at the time of this writing, we don't have
ALTERNATIVE_2() invocations which have that problem and even if
we did, a simple fix would be to prepend the instructions with
enough prefixes so that that corner case doesn't happen.
However, best it would be if we fixed it properly. See below for
a simple, abstracted example of what we're doing.
So what we ended up doing is, we compute the
max(len(alt1), len(alt2)) - len(orig_insn)
and feed that value to the .skip gas directive. The max() cannot
have conditionals due to gas limitations, thus the fancy integer
math.
With this patch, all ALTERNATIVE_2 sites get padded correctly;
generating obscure test cases pass too:
#define alt_max_short(a, b) ((a) ^ (((a) ^ (b)) & -(-((a) < (b)))))
#define gen_skip(orig, alt1, alt2, marker) \
.skip -((alt_max_short(alt1, alt2) - (orig)) > 0) * \
(alt_max_short(alt1, alt2) - (orig)),marker
.pushsection .text, "ax"
.globl main
main:
gen_skip(1, 2, 4, 0x09)
gen_skip(4, 1, 2, 0x10)
...
.popsection
Thanks to Quentin for catching it and double-checking the fix!
Reported-by: Quentin Casasnovas <quentin.casasnovas@oracle.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20150404133443.GE21152@pd.tnic
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-04-04 13:34:43 +00:00
|
|
|
DPRINTK("feat: %d*32+%d, old: (%p, len: %d), repl: (%p, len: %d), pad: %d",
|
2014-12-30 19:27:09 +00:00
|
|
|
a->cpuid >> 5,
|
|
|
|
a->cpuid & 0x1f,
|
|
|
|
instr, a->instrlen,
|
x86/alternatives: Fix ALTERNATIVE_2 padding generation properly
Quentin caught a corner case with the generation of instruction
padding in the ALTERNATIVE_2 macro: if len(orig_insn) <
len(alt1) < len(alt2), then not enough padding gets added and
that is not good(tm) as we could overwrite the beginning of the
next instruction.
Luckily, at the time of this writing, we don't have
ALTERNATIVE_2() invocations which have that problem and even if
we did, a simple fix would be to prepend the instructions with
enough prefixes so that that corner case doesn't happen.
However, best it would be if we fixed it properly. See below for
a simple, abstracted example of what we're doing.
So what we ended up doing is, we compute the
max(len(alt1), len(alt2)) - len(orig_insn)
and feed that value to the .skip gas directive. The max() cannot
have conditionals due to gas limitations, thus the fancy integer
math.
With this patch, all ALTERNATIVE_2 sites get padded correctly;
generating obscure test cases pass too:
#define alt_max_short(a, b) ((a) ^ (((a) ^ (b)) & -(-((a) < (b)))))
#define gen_skip(orig, alt1, alt2, marker) \
.skip -((alt_max_short(alt1, alt2) - (orig)) > 0) * \
(alt_max_short(alt1, alt2) - (orig)),marker
.pushsection .text, "ax"
.globl main
main:
gen_skip(1, 2, 4, 0x09)
gen_skip(4, 1, 2, 0x10)
...
.popsection
Thanks to Quentin for catching it and double-checking the fix!
Reported-by: Quentin Casasnovas <quentin.casasnovas@oracle.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/20150404133443.GE21152@pd.tnic
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-04-04 13:34:43 +00:00
|
|
|
replacement, a->replacementlen, a->padlen);
|
2014-12-30 19:27:09 +00:00
|
|
|
|
x86/alternatives: Make JMPs more robust
Up until now we had to pay attention to relative JMPs in alternatives
about how their relative offset gets computed so that the jump target
is still correct. Or, as it is the case for near CALLs (opcode e8), we
still have to go and readjust the offset at patching time.
What is more, the static_cpu_has_safe() facility had to forcefully
generate 5-byte JMPs since we couldn't rely on the compiler to generate
properly sized ones so we had to force the longest ones. Worse than
that, sometimes it would generate a replacement JMP which is longer than
the original one, thus overwriting the beginning of the next instruction
at patching time.
So, in order to alleviate all that and make using JMPs more
straight-forward we go and pad the original instruction in an
alternative block with NOPs at build time, should the replacement(s) be
longer. This way, alternatives users shouldn't pay special attention
so that original and replacement instruction sizes are fine but the
assembler would simply add padding where needed and not do anything
otherwise.
As a second aspect, we go and recompute JMPs at patching time so that we
can try to make 5-byte JMPs into two-byte ones if possible. If not, we
still have to recompute the offsets as the replacement JMP gets put far
away in the .altinstr_replacement section leading to a wrong offset if
copied verbatim.
For example, on a locally generated kernel image
old insn VA: 0xffffffff810014bd, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff810014bd: eb 21 jmp ffffffff810014e0
repl insn: size: 5
ffffffff81d0b23c: e9 b1 62 2f ff jmpq ffffffff810014f2
gets corrected to a 2-byte JMP:
apply_alternatives: feat: 3*32+21, old: (ffffffff810014bd, len: 2), repl: (ffffffff81d0b23c, len: 5)
alt_insn: e9 b1 62 2f ff
recompute_jumps: next_rip: ffffffff81d0b241, tgt_rip: ffffffff810014f2, new_displ: 0x00000033, ret len: 2
converted to: eb 33 90 90 90
and a 5-byte JMP:
old insn VA: 0xffffffff81001516, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff81001516: eb 30 jmp ffffffff81001548
repl insn: size: 5
ffffffff81d0b241: e9 10 63 2f ff jmpq ffffffff81001556
gets shortened into a two-byte one:
apply_alternatives: feat: 3*32+21, old: (ffffffff81001516, len: 2), repl: (ffffffff81d0b241, len: 5)
alt_insn: e9 10 63 2f ff
recompute_jumps: next_rip: ffffffff81d0b246, tgt_rip: ffffffff81001556, new_displ: 0x0000003e, ret len: 2
converted to: eb 3e 90 90 90
... and so on.
This leads to a net win of around
40ish replacements * 3 bytes savings =~ 120 bytes of I$
on an AMD guest which means some savings of precious instruction cache
bandwidth. The padding to the shorter 2-byte JMPs are single-byte NOPs
which on smart microarchitectures means discarding NOPs at decode time
and thus freeing up execution bandwidth.
Signed-off-by: Borislav Petkov <bp@suse.de>
2015-01-05 12:48:41 +00:00
|
|
|
DUMP_BYTES(instr, a->instrlen, "%p: old_insn: ", instr);
|
|
|
|
DUMP_BYTES(replacement, a->replacementlen, "%p: rpl_insn: ", replacement);
|
|
|
|
|
2011-07-13 13:24:10 +00:00
|
|
|
memcpy(insnbuf, replacement, a->replacementlen);
|
x86/alternatives: Make JMPs more robust
Up until now we had to pay attention to relative JMPs in alternatives
about how their relative offset gets computed so that the jump target
is still correct. Or, as it is the case for near CALLs (opcode e8), we
still have to go and readjust the offset at patching time.
What is more, the static_cpu_has_safe() facility had to forcefully
generate 5-byte JMPs since we couldn't rely on the compiler to generate
properly sized ones so we had to force the longest ones. Worse than
that, sometimes it would generate a replacement JMP which is longer than
the original one, thus overwriting the beginning of the next instruction
at patching time.
So, in order to alleviate all that and make using JMPs more
straight-forward we go and pad the original instruction in an
alternative block with NOPs at build time, should the replacement(s) be
longer. This way, alternatives users shouldn't pay special attention
so that original and replacement instruction sizes are fine but the
assembler would simply add padding where needed and not do anything
otherwise.
As a second aspect, we go and recompute JMPs at patching time so that we
can try to make 5-byte JMPs into two-byte ones if possible. If not, we
still have to recompute the offsets as the replacement JMP gets put far
away in the .altinstr_replacement section leading to a wrong offset if
copied verbatim.
For example, on a locally generated kernel image
old insn VA: 0xffffffff810014bd, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff810014bd: eb 21 jmp ffffffff810014e0
repl insn: size: 5
ffffffff81d0b23c: e9 b1 62 2f ff jmpq ffffffff810014f2
gets corrected to a 2-byte JMP:
apply_alternatives: feat: 3*32+21, old: (ffffffff810014bd, len: 2), repl: (ffffffff81d0b23c, len: 5)
alt_insn: e9 b1 62 2f ff
recompute_jumps: next_rip: ffffffff81d0b241, tgt_rip: ffffffff810014f2, new_displ: 0x00000033, ret len: 2
converted to: eb 33 90 90 90
and a 5-byte JMP:
old insn VA: 0xffffffff81001516, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff81001516: eb 30 jmp ffffffff81001548
repl insn: size: 5
ffffffff81d0b241: e9 10 63 2f ff jmpq ffffffff81001556
gets shortened into a two-byte one:
apply_alternatives: feat: 3*32+21, old: (ffffffff81001516, len: 2), repl: (ffffffff81d0b241, len: 5)
alt_insn: e9 10 63 2f ff
recompute_jumps: next_rip: ffffffff81d0b246, tgt_rip: ffffffff81001556, new_displ: 0x0000003e, ret len: 2
converted to: eb 3e 90 90 90
... and so on.
This leads to a net win of around
40ish replacements * 3 bytes savings =~ 120 bytes of I$
on an AMD guest which means some savings of precious instruction cache
bandwidth. The padding to the shorter 2-byte JMPs are single-byte NOPs
which on smart microarchitectures means discarding NOPs at decode time
and thus freeing up execution bandwidth.
Signed-off-by: Borislav Petkov <bp@suse.de>
2015-01-05 12:48:41 +00:00
|
|
|
insnbuf_sz = a->replacementlen;
|
2011-07-13 13:24:10 +00:00
|
|
|
|
|
|
|
/* 0xe8 is a relative jump; fix the offset. */
|
2014-12-30 19:27:09 +00:00
|
|
|
if (*insnbuf == 0xe8 && a->replacementlen == 5) {
|
|
|
|
*(s32 *)(insnbuf + 1) += replacement - instr;
|
x86/alternatives: Make JMPs more robust
Up until now we had to pay attention to relative JMPs in alternatives
about how their relative offset gets computed so that the jump target
is still correct. Or, as it is the case for near CALLs (opcode e8), we
still have to go and readjust the offset at patching time.
What is more, the static_cpu_has_safe() facility had to forcefully
generate 5-byte JMPs since we couldn't rely on the compiler to generate
properly sized ones so we had to force the longest ones. Worse than
that, sometimes it would generate a replacement JMP which is longer than
the original one, thus overwriting the beginning of the next instruction
at patching time.
So, in order to alleviate all that and make using JMPs more
straight-forward we go and pad the original instruction in an
alternative block with NOPs at build time, should the replacement(s) be
longer. This way, alternatives users shouldn't pay special attention
so that original and replacement instruction sizes are fine but the
assembler would simply add padding where needed and not do anything
otherwise.
As a second aspect, we go and recompute JMPs at patching time so that we
can try to make 5-byte JMPs into two-byte ones if possible. If not, we
still have to recompute the offsets as the replacement JMP gets put far
away in the .altinstr_replacement section leading to a wrong offset if
copied verbatim.
For example, on a locally generated kernel image
old insn VA: 0xffffffff810014bd, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff810014bd: eb 21 jmp ffffffff810014e0
repl insn: size: 5
ffffffff81d0b23c: e9 b1 62 2f ff jmpq ffffffff810014f2
gets corrected to a 2-byte JMP:
apply_alternatives: feat: 3*32+21, old: (ffffffff810014bd, len: 2), repl: (ffffffff81d0b23c, len: 5)
alt_insn: e9 b1 62 2f ff
recompute_jumps: next_rip: ffffffff81d0b241, tgt_rip: ffffffff810014f2, new_displ: 0x00000033, ret len: 2
converted to: eb 33 90 90 90
and a 5-byte JMP:
old insn VA: 0xffffffff81001516, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff81001516: eb 30 jmp ffffffff81001548
repl insn: size: 5
ffffffff81d0b241: e9 10 63 2f ff jmpq ffffffff81001556
gets shortened into a two-byte one:
apply_alternatives: feat: 3*32+21, old: (ffffffff81001516, len: 2), repl: (ffffffff81d0b241, len: 5)
alt_insn: e9 10 63 2f ff
recompute_jumps: next_rip: ffffffff81d0b246, tgt_rip: ffffffff81001556, new_displ: 0x0000003e, ret len: 2
converted to: eb 3e 90 90 90
... and so on.
This leads to a net win of around
40ish replacements * 3 bytes savings =~ 120 bytes of I$
on an AMD guest which means some savings of precious instruction cache
bandwidth. The padding to the shorter 2-byte JMPs are single-byte NOPs
which on smart microarchitectures means discarding NOPs at decode time
and thus freeing up execution bandwidth.
Signed-off-by: Borislav Petkov <bp@suse.de>
2015-01-05 12:48:41 +00:00
|
|
|
DPRINTK("Fix CALL offset: 0x%x, CALL 0x%lx",
|
|
|
|
*(s32 *)(insnbuf + 1),
|
|
|
|
(unsigned long)instr + *(s32 *)(insnbuf + 1) + 5);
|
2014-12-30 19:27:09 +00:00
|
|
|
}
|
2011-07-13 13:24:10 +00:00
|
|
|
|
x86/alternatives: Make JMPs more robust
Up until now we had to pay attention to relative JMPs in alternatives
about how their relative offset gets computed so that the jump target
is still correct. Or, as it is the case for near CALLs (opcode e8), we
still have to go and readjust the offset at patching time.
What is more, the static_cpu_has_safe() facility had to forcefully
generate 5-byte JMPs since we couldn't rely on the compiler to generate
properly sized ones so we had to force the longest ones. Worse than
that, sometimes it would generate a replacement JMP which is longer than
the original one, thus overwriting the beginning of the next instruction
at patching time.
So, in order to alleviate all that and make using JMPs more
straight-forward we go and pad the original instruction in an
alternative block with NOPs at build time, should the replacement(s) be
longer. This way, alternatives users shouldn't pay special attention
so that original and replacement instruction sizes are fine but the
assembler would simply add padding where needed and not do anything
otherwise.
As a second aspect, we go and recompute JMPs at patching time so that we
can try to make 5-byte JMPs into two-byte ones if possible. If not, we
still have to recompute the offsets as the replacement JMP gets put far
away in the .altinstr_replacement section leading to a wrong offset if
copied verbatim.
For example, on a locally generated kernel image
old insn VA: 0xffffffff810014bd, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff810014bd: eb 21 jmp ffffffff810014e0
repl insn: size: 5
ffffffff81d0b23c: e9 b1 62 2f ff jmpq ffffffff810014f2
gets corrected to a 2-byte JMP:
apply_alternatives: feat: 3*32+21, old: (ffffffff810014bd, len: 2), repl: (ffffffff81d0b23c, len: 5)
alt_insn: e9 b1 62 2f ff
recompute_jumps: next_rip: ffffffff81d0b241, tgt_rip: ffffffff810014f2, new_displ: 0x00000033, ret len: 2
converted to: eb 33 90 90 90
and a 5-byte JMP:
old insn VA: 0xffffffff81001516, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff81001516: eb 30 jmp ffffffff81001548
repl insn: size: 5
ffffffff81d0b241: e9 10 63 2f ff jmpq ffffffff81001556
gets shortened into a two-byte one:
apply_alternatives: feat: 3*32+21, old: (ffffffff81001516, len: 2), repl: (ffffffff81d0b241, len: 5)
alt_insn: e9 10 63 2f ff
recompute_jumps: next_rip: ffffffff81d0b246, tgt_rip: ffffffff81001556, new_displ: 0x0000003e, ret len: 2
converted to: eb 3e 90 90 90
... and so on.
This leads to a net win of around
40ish replacements * 3 bytes savings =~ 120 bytes of I$
on an AMD guest which means some savings of precious instruction cache
bandwidth. The padding to the shorter 2-byte JMPs are single-byte NOPs
which on smart microarchitectures means discarding NOPs at decode time
and thus freeing up execution bandwidth.
Signed-off-by: Borislav Petkov <bp@suse.de>
2015-01-05 12:48:41 +00:00
|
|
|
if (a->replacementlen && is_jmp(replacement[0]))
|
|
|
|
recompute_jump(a, instr, replacement, insnbuf);
|
|
|
|
|
|
|
|
if (a->instrlen > a->replacementlen) {
|
2014-12-27 09:41:52 +00:00
|
|
|
add_nops(insnbuf + a->replacementlen,
|
|
|
|
a->instrlen - a->replacementlen);
|
x86/alternatives: Make JMPs more robust
Up until now we had to pay attention to relative JMPs in alternatives
about how their relative offset gets computed so that the jump target
is still correct. Or, as it is the case for near CALLs (opcode e8), we
still have to go and readjust the offset at patching time.
What is more, the static_cpu_has_safe() facility had to forcefully
generate 5-byte JMPs since we couldn't rely on the compiler to generate
properly sized ones so we had to force the longest ones. Worse than
that, sometimes it would generate a replacement JMP which is longer than
the original one, thus overwriting the beginning of the next instruction
at patching time.
So, in order to alleviate all that and make using JMPs more
straight-forward we go and pad the original instruction in an
alternative block with NOPs at build time, should the replacement(s) be
longer. This way, alternatives users shouldn't pay special attention
so that original and replacement instruction sizes are fine but the
assembler would simply add padding where needed and not do anything
otherwise.
As a second aspect, we go and recompute JMPs at patching time so that we
can try to make 5-byte JMPs into two-byte ones if possible. If not, we
still have to recompute the offsets as the replacement JMP gets put far
away in the .altinstr_replacement section leading to a wrong offset if
copied verbatim.
For example, on a locally generated kernel image
old insn VA: 0xffffffff810014bd, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff810014bd: eb 21 jmp ffffffff810014e0
repl insn: size: 5
ffffffff81d0b23c: e9 b1 62 2f ff jmpq ffffffff810014f2
gets corrected to a 2-byte JMP:
apply_alternatives: feat: 3*32+21, old: (ffffffff810014bd, len: 2), repl: (ffffffff81d0b23c, len: 5)
alt_insn: e9 b1 62 2f ff
recompute_jumps: next_rip: ffffffff81d0b241, tgt_rip: ffffffff810014f2, new_displ: 0x00000033, ret len: 2
converted to: eb 33 90 90 90
and a 5-byte JMP:
old insn VA: 0xffffffff81001516, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff81001516: eb 30 jmp ffffffff81001548
repl insn: size: 5
ffffffff81d0b241: e9 10 63 2f ff jmpq ffffffff81001556
gets shortened into a two-byte one:
apply_alternatives: feat: 3*32+21, old: (ffffffff81001516, len: 2), repl: (ffffffff81d0b241, len: 5)
alt_insn: e9 10 63 2f ff
recompute_jumps: next_rip: ffffffff81d0b246, tgt_rip: ffffffff81001556, new_displ: 0x0000003e, ret len: 2
converted to: eb 3e 90 90 90
... and so on.
This leads to a net win of around
40ish replacements * 3 bytes savings =~ 120 bytes of I$
on an AMD guest which means some savings of precious instruction cache
bandwidth. The padding to the shorter 2-byte JMPs are single-byte NOPs
which on smart microarchitectures means discarding NOPs at decode time
and thus freeing up execution bandwidth.
Signed-off-by: Borislav Petkov <bp@suse.de>
2015-01-05 12:48:41 +00:00
|
|
|
insnbuf_sz += a->instrlen - a->replacementlen;
|
|
|
|
}
|
|
|
|
DUMP_BYTES(insnbuf, insnbuf_sz, "%p: final_insn: ", instr);
|
2011-07-13 13:24:10 +00:00
|
|
|
|
x86/alternatives: Make JMPs more robust
Up until now we had to pay attention to relative JMPs in alternatives
about how their relative offset gets computed so that the jump target
is still correct. Or, as it is the case for near CALLs (opcode e8), we
still have to go and readjust the offset at patching time.
What is more, the static_cpu_has_safe() facility had to forcefully
generate 5-byte JMPs since we couldn't rely on the compiler to generate
properly sized ones so we had to force the longest ones. Worse than
that, sometimes it would generate a replacement JMP which is longer than
the original one, thus overwriting the beginning of the next instruction
at patching time.
So, in order to alleviate all that and make using JMPs more
straight-forward we go and pad the original instruction in an
alternative block with NOPs at build time, should the replacement(s) be
longer. This way, alternatives users shouldn't pay special attention
so that original and replacement instruction sizes are fine but the
assembler would simply add padding where needed and not do anything
otherwise.
As a second aspect, we go and recompute JMPs at patching time so that we
can try to make 5-byte JMPs into two-byte ones if possible. If not, we
still have to recompute the offsets as the replacement JMP gets put far
away in the .altinstr_replacement section leading to a wrong offset if
copied verbatim.
For example, on a locally generated kernel image
old insn VA: 0xffffffff810014bd, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff810014bd: eb 21 jmp ffffffff810014e0
repl insn: size: 5
ffffffff81d0b23c: e9 b1 62 2f ff jmpq ffffffff810014f2
gets corrected to a 2-byte JMP:
apply_alternatives: feat: 3*32+21, old: (ffffffff810014bd, len: 2), repl: (ffffffff81d0b23c, len: 5)
alt_insn: e9 b1 62 2f ff
recompute_jumps: next_rip: ffffffff81d0b241, tgt_rip: ffffffff810014f2, new_displ: 0x00000033, ret len: 2
converted to: eb 33 90 90 90
and a 5-byte JMP:
old insn VA: 0xffffffff81001516, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff81001516: eb 30 jmp ffffffff81001548
repl insn: size: 5
ffffffff81d0b241: e9 10 63 2f ff jmpq ffffffff81001556
gets shortened into a two-byte one:
apply_alternatives: feat: 3*32+21, old: (ffffffff81001516, len: 2), repl: (ffffffff81d0b241, len: 5)
alt_insn: e9 10 63 2f ff
recompute_jumps: next_rip: ffffffff81d0b246, tgt_rip: ffffffff81001556, new_displ: 0x0000003e, ret len: 2
converted to: eb 3e 90 90 90
... and so on.
This leads to a net win of around
40ish replacements * 3 bytes savings =~ 120 bytes of I$
on an AMD guest which means some savings of precious instruction cache
bandwidth. The padding to the shorter 2-byte JMPs are single-byte NOPs
which on smart microarchitectures means discarding NOPs at decode time
and thus freeing up execution bandwidth.
Signed-off-by: Borislav Petkov <bp@suse.de>
2015-01-05 12:48:41 +00:00
|
|
|
text_poke_early(instr, insnbuf, insnbuf_sz);
|
2006-03-23 10:59:32 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-07-01 11:36:18 +00:00
|
|
|
#ifdef CONFIG_SMP
|
2010-04-21 15:08:14 +00:00
|
|
|
static void alternatives_smp_lock(const s32 *start, const s32 *end,
|
|
|
|
u8 *text, u8 *text_end)
|
2006-03-23 10:59:32 +00:00
|
|
|
{
|
2010-04-21 15:08:14 +00:00
|
|
|
const s32 *poff;
|
2006-03-23 10:59:32 +00:00
|
|
|
|
2009-03-06 15:37:22 +00:00
|
|
|
mutex_lock(&text_mutex);
|
2010-04-21 15:08:14 +00:00
|
|
|
for (poff = start; poff < end; poff++) {
|
|
|
|
u8 *ptr = (u8 *)poff + *poff;
|
|
|
|
|
|
|
|
if (!*poff || ptr < text || ptr >= text_end)
|
2006-03-23 10:59:32 +00:00
|
|
|
continue;
|
x86: alternatives : fix LOCK_PREFIX race with preemptible kernel and CPU hotplug
If a kernel thread is preempted in single-cpu mode right after the NOP (nop
about to be turned into a lock prefix), then we CPU hotplug a CPU, and then the
thread is scheduled back again, a SMP-unsafe atomic operation will be used on
shared SMP variables, leading to corruption. No corruption would happen in the
reverse case : going from SMP to UP is ok because we split a bit instruction
into tiny pieces, which does not present this condition.
Changing the 0x90 (single-byte nop) currently used into a 0x3E DS segment
override prefix should fix this issue. Since the default of the atomic
instructions is to use the DS segment anyway, it should not affect the
behavior.
The exception to this are references that use ESP/RSP and EBP/RBP as
the base register (they will use the SS segment), however, in Linux
(a) DS == SS at all times, and (b) we do not distinguish between
segment violations reported as #SS as opposed to #GP, so there is no
need to disassemble the instruction to figure out the suitable segment.
This patch assumes that the 0x3E prefix will leave atomic operations as-is (thus
assuming they normally touch data in the DS segment). Since there seem to be no
obvious ill-use of other segment override prefixes for atomic operations, it
should be safe. It can be verified with a quick
grep -r LOCK_PREFIX include/asm-x86/
grep -A 1 -r LOCK_PREFIX arch/x86/
Taken from
This source :
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System
Instructions
States
"Instructions that Reference a Non-Stack Segment—If an instruction encoding
references any base register other than rBP or rSP, or if an instruction
contains an immediate offset, the default segment is the data segment (DS).
These instructions can use the segment-override prefix to select one of the
non-default segments, as shown in Table 1-5."
Therefore, forcing the DS segment on the atomic operations, which already use
the DS segment, should not change.
This source :
http://wiki.osdev.org/X86_Instruction_Encoding
States
"In 64-bit the CS, SS, DS and ES segment overrides are ignored."
Confirmed by "AMD 64-Bit Technology" A.7
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/x86-64_overview.pdf
"In 64-bit mode, the DS, ES, SS and CS segment-override prefixes have no effect.
These four prefixes are no longer treated as segment-override prefixes in the
context of multipleprefix rules. Instead, they are treated as null prefixes."
This patch applies to 2.6.27-rc2, but would also have to be applied to earlier
kernels (2.6.26, 2.6.25, ...).
Performance impact of the fix : tests done on "xaddq" and "xaddl" shows it
actually improves performances on Intel Xeon, AMD64, Pentium M. It does not
change the performance on Pentium II, Pentium 3 and Pentium 4.
Xeon E5405 2.0GHz :
NR_TESTS 10000000
test empty cycles : 162207948
test test 1-byte nop xadd cycles : 170755422
test test DS override prefix xadd cycles : 170000118 *
test test LOCK xadd cycles : 472012134
AMD64 2.0GHz :
NR_TESTS 10000000
test empty cycles : 146674549
test test 1-byte nop xadd cycles : 150273860
test test DS override prefix xadd cycles : 149982382 *
test test LOCK xadd cycles : 270000690
Pentium 4 3.0GHz
NR_TESTS 10000000
test empty cycles : 290001195
test test 1-byte nop xadd cycles : 310000560
test test DS override prefix xadd cycles : 310000575 *
test test LOCK xadd cycles : 1050103740
Pentium M 2.0GHz
NR_TESTS 10000000
test empty cycles : 180000523
test test 1-byte nop xadd cycles : 320000345
test test DS override prefix xadd cycles : 310000374 *
test test LOCK xadd cycles : 480000357
Pentium 3 550MHz
NR_TESTS 10000000
test empty cycles : 510000231
test test 1-byte nop xadd cycles : 620000128
test test DS override prefix xadd cycles : 620000110 *
test test LOCK xadd cycles : 800000088
Pentium II 350MHz
NR_TESTS 10000000
test empty cycles : 200833494
test test 1-byte nop xadd cycles : 340000130
test test DS override prefix xadd cycles : 340000126 *
test test LOCK xadd cycles : 530000078
Speed test modules can be found at
http://ltt.polymtl.ca/svn/trunk/tests/kernel/test-prefix-speed-32.c
http://ltt.polymtl.ca/svn/trunk/tests/kernel/test-prefix-speed.c
Macro-benchmarks
2.0GHz E5405 Core 2 dual Quad-Core Xeon
Summary
* replace smp lock prefixes with DS segment selector prefixes
no lock prefix (s) with lock prefix (s) Speedup
make -j1 kernel/ 33.94 +/- 0.07 34.91 +/- 0.27 2.8 %
hackbench 50 2.99 +/- 0.01 3.74 +/- 0.01 25.1 %
* replace smp lock prefixes with 0x90 nops
no lock prefix (s) with lock prefix (s) Speedup
make -j1 kernel/ 34.16 +/- 0.32 34.91 +/- 0.27 2.2 %
hackbench 50 3.00 +/- 0.01 3.74 +/- 0.01 24.7 %
Detail :
1 CPU, replace smp lock prefixes with DS segment selector prefixes
make -j1 kernel/
real 0m34.067s
user 0m30.630s
sys 0m2.980s
real 0m33.867s
user 0m30.582s
sys 0m3.024s
real 0m33.939s
user 0m30.738s
sys 0m2.876s
real 0m33.913s
user 0m30.806s
sys 0m2.808s
avg : 33.94s
std. dev. : 0.07s
hackbench 50
Time: 2.978
Time: 2.982
Time: 3.010
Time: 2.984
Time: 2.982
avg : 2.99
std. dev. : 0.01
1 CPU, noreplace-smp
make -j1 kernel/
real 0m35.326s
user 0m30.630s
sys 0m3.260s
real 0m34.325s
user 0m30.802s
sys 0m3.084s
real 0m35.568s
user 0m30.722s
sys 0m3.168s
real 0m34.435s
user 0m30.886s
sys 0m2.996s
avg.: 34.91s
std. dev. : 0.27s
hackbench 50
Time: 3.733
Time: 3.750
Time: 3.761
Time: 3.737
Time: 3.741
avg : 3.74
std. dev. : 0.01
1 CPU, replace smp lock prefixes with 0x90 nops
make -j1 kernel/
real 0m34.139s
user 0m30.782s
sys 0m2.820s
real 0m34.010s
user 0m30.630s
sys 0m2.976s
real 0m34.777s
user 0m30.658s
sys 0m2.916s
real 0m33.924s
user 0m30.634s
sys 0m2.924s
real 0m33.962s
user 0m30.774s
sys 0m2.800s
real 0m34.141s
user 0m30.770s
sys 0m2.828s
avg : 34.16
std. dev. : 0.32
hackbench 50
Time: 2.999
Time: 2.994
Time: 3.004
Time: 2.991
Time: 2.988
avg : 3.00
std. dev. : 0.01
I did more runs (20 runs of each) to compare the nop case to the DS
prefix case. Results in seconds. They actually does not seems to show a
significant difference.
NOP
34.155
33.955
34.012
35.299
35.679
34.141
33.995
35.016
34.254
33.957
33.957
34.008
35.013
34.494
33.893
34.295
34.314
34.854
33.991
34.132
DS
34.080
34.304
34.374
35.095
34.291
34.135
33.940
34.208
35.276
34.288
33.861
33.898
34.610
34.709
33.851
34.256
35.161
34.283
33.865
35.078
Used http://www.graphpad.com/quickcalcs/ttest1.cfm?Format=C to do the
T-test (yeah, I'm lazy) :
Group Group One (DS prefix) Group Two (nops)
Mean 34.37815 34.37070
SD 0.46108 0.51905
SEM 0.10310 0.11606
N 20 20
P value and statistical significance:
The two-tailed P value equals 0.9620
By conventional criteria, this difference is considered to be not statistically significant.
Confidence interval:
The mean of Group One minus Group Two equals 0.00745
95% confidence interval of this difference: From -0.30682 to 0.32172
Intermediate values used in calculations:
t = 0.0480
df = 38
standard error of difference = 0.155
So, unless these calculus are completely bogus, the difference between the nop
and the DS case seems not to be statistically significant.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Acked-by: H. Peter Anvin <hpa@zytor.com>
CC: Linus Torvalds <torvalds@linux-foundation.org>
CC: Jeremy Fitzhardinge <jeremy@goop.org>
CC: Roland McGrath <roland@redhat.com>
CC: Ingo Molnar <mingo@elte.hu>
Cc: Steven Rostedt <rostedt@goodmis.org>
CC: Steven Rostedt <srostedt@redhat.com>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: Peter Zijlstra <peterz@infradead.org>
CC: Andrew Morton <akpm@linux-foundation.org>
CC: David Miller <davem@davemloft.net>
CC: Ulrich Drepper <drepper@redhat.com>
CC: Rusty Russell <rusty@rustcorp.com.au>
CC: Gregory Haskins <ghaskins@novell.com>
CC: Arnaldo Carvalho de Melo <acme@redhat.com>
CC: "Luis Claudio R. Goncalves" <lclaudio@uudg.org>
CC: Clark Williams <williams@redhat.com>
CC: Christoph Lameter <cl@linux-foundation.org>
CC: Andi Kleen <andi@firstfloor.org>
CC: Harvey Harrison <harvey.harrison@gmail.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2008-08-14 20:58:15 +00:00
|
|
|
/* turn DS segment override prefix into lock prefix */
|
2010-04-29 23:53:17 +00:00
|
|
|
if (*ptr == 0x3e)
|
|
|
|
text_poke(ptr, ((unsigned char []){0xf0}), 1);
|
2012-09-18 16:36:14 +00:00
|
|
|
}
|
2009-03-06 15:37:22 +00:00
|
|
|
mutex_unlock(&text_mutex);
|
2006-03-23 10:59:32 +00:00
|
|
|
}
|
|
|
|
|
2010-04-21 15:08:14 +00:00
|
|
|
static void alternatives_smp_unlock(const s32 *start, const s32 *end,
|
|
|
|
u8 *text, u8 *text_end)
|
2006-03-23 10:59:32 +00:00
|
|
|
{
|
2010-04-21 15:08:14 +00:00
|
|
|
const s32 *poff;
|
2006-03-23 10:59:32 +00:00
|
|
|
|
2009-03-06 15:37:22 +00:00
|
|
|
mutex_lock(&text_mutex);
|
2010-04-21 15:08:14 +00:00
|
|
|
for (poff = start; poff < end; poff++) {
|
|
|
|
u8 *ptr = (u8 *)poff + *poff;
|
|
|
|
|
|
|
|
if (!*poff || ptr < text || ptr >= text_end)
|
2006-03-23 10:59:32 +00:00
|
|
|
continue;
|
x86: alternatives : fix LOCK_PREFIX race with preemptible kernel and CPU hotplug
If a kernel thread is preempted in single-cpu mode right after the NOP (nop
about to be turned into a lock prefix), then we CPU hotplug a CPU, and then the
thread is scheduled back again, a SMP-unsafe atomic operation will be used on
shared SMP variables, leading to corruption. No corruption would happen in the
reverse case : going from SMP to UP is ok because we split a bit instruction
into tiny pieces, which does not present this condition.
Changing the 0x90 (single-byte nop) currently used into a 0x3E DS segment
override prefix should fix this issue. Since the default of the atomic
instructions is to use the DS segment anyway, it should not affect the
behavior.
The exception to this are references that use ESP/RSP and EBP/RBP as
the base register (they will use the SS segment), however, in Linux
(a) DS == SS at all times, and (b) we do not distinguish between
segment violations reported as #SS as opposed to #GP, so there is no
need to disassemble the instruction to figure out the suitable segment.
This patch assumes that the 0x3E prefix will leave atomic operations as-is (thus
assuming they normally touch data in the DS segment). Since there seem to be no
obvious ill-use of other segment override prefixes for atomic operations, it
should be safe. It can be verified with a quick
grep -r LOCK_PREFIX include/asm-x86/
grep -A 1 -r LOCK_PREFIX arch/x86/
Taken from
This source :
AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System
Instructions
States
"Instructions that Reference a Non-Stack Segment—If an instruction encoding
references any base register other than rBP or rSP, or if an instruction
contains an immediate offset, the default segment is the data segment (DS).
These instructions can use the segment-override prefix to select one of the
non-default segments, as shown in Table 1-5."
Therefore, forcing the DS segment on the atomic operations, which already use
the DS segment, should not change.
This source :
http://wiki.osdev.org/X86_Instruction_Encoding
States
"In 64-bit the CS, SS, DS and ES segment overrides are ignored."
Confirmed by "AMD 64-Bit Technology" A.7
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/x86-64_overview.pdf
"In 64-bit mode, the DS, ES, SS and CS segment-override prefixes have no effect.
These four prefixes are no longer treated as segment-override prefixes in the
context of multipleprefix rules. Instead, they are treated as null prefixes."
This patch applies to 2.6.27-rc2, but would also have to be applied to earlier
kernels (2.6.26, 2.6.25, ...).
Performance impact of the fix : tests done on "xaddq" and "xaddl" shows it
actually improves performances on Intel Xeon, AMD64, Pentium M. It does not
change the performance on Pentium II, Pentium 3 and Pentium 4.
Xeon E5405 2.0GHz :
NR_TESTS 10000000
test empty cycles : 162207948
test test 1-byte nop xadd cycles : 170755422
test test DS override prefix xadd cycles : 170000118 *
test test LOCK xadd cycles : 472012134
AMD64 2.0GHz :
NR_TESTS 10000000
test empty cycles : 146674549
test test 1-byte nop xadd cycles : 150273860
test test DS override prefix xadd cycles : 149982382 *
test test LOCK xadd cycles : 270000690
Pentium 4 3.0GHz
NR_TESTS 10000000
test empty cycles : 290001195
test test 1-byte nop xadd cycles : 310000560
test test DS override prefix xadd cycles : 310000575 *
test test LOCK xadd cycles : 1050103740
Pentium M 2.0GHz
NR_TESTS 10000000
test empty cycles : 180000523
test test 1-byte nop xadd cycles : 320000345
test test DS override prefix xadd cycles : 310000374 *
test test LOCK xadd cycles : 480000357
Pentium 3 550MHz
NR_TESTS 10000000
test empty cycles : 510000231
test test 1-byte nop xadd cycles : 620000128
test test DS override prefix xadd cycles : 620000110 *
test test LOCK xadd cycles : 800000088
Pentium II 350MHz
NR_TESTS 10000000
test empty cycles : 200833494
test test 1-byte nop xadd cycles : 340000130
test test DS override prefix xadd cycles : 340000126 *
test test LOCK xadd cycles : 530000078
Speed test modules can be found at
http://ltt.polymtl.ca/svn/trunk/tests/kernel/test-prefix-speed-32.c
http://ltt.polymtl.ca/svn/trunk/tests/kernel/test-prefix-speed.c
Macro-benchmarks
2.0GHz E5405 Core 2 dual Quad-Core Xeon
Summary
* replace smp lock prefixes with DS segment selector prefixes
no lock prefix (s) with lock prefix (s) Speedup
make -j1 kernel/ 33.94 +/- 0.07 34.91 +/- 0.27 2.8 %
hackbench 50 2.99 +/- 0.01 3.74 +/- 0.01 25.1 %
* replace smp lock prefixes with 0x90 nops
no lock prefix (s) with lock prefix (s) Speedup
make -j1 kernel/ 34.16 +/- 0.32 34.91 +/- 0.27 2.2 %
hackbench 50 3.00 +/- 0.01 3.74 +/- 0.01 24.7 %
Detail :
1 CPU, replace smp lock prefixes with DS segment selector prefixes
make -j1 kernel/
real 0m34.067s
user 0m30.630s
sys 0m2.980s
real 0m33.867s
user 0m30.582s
sys 0m3.024s
real 0m33.939s
user 0m30.738s
sys 0m2.876s
real 0m33.913s
user 0m30.806s
sys 0m2.808s
avg : 33.94s
std. dev. : 0.07s
hackbench 50
Time: 2.978
Time: 2.982
Time: 3.010
Time: 2.984
Time: 2.982
avg : 2.99
std. dev. : 0.01
1 CPU, noreplace-smp
make -j1 kernel/
real 0m35.326s
user 0m30.630s
sys 0m3.260s
real 0m34.325s
user 0m30.802s
sys 0m3.084s
real 0m35.568s
user 0m30.722s
sys 0m3.168s
real 0m34.435s
user 0m30.886s
sys 0m2.996s
avg.: 34.91s
std. dev. : 0.27s
hackbench 50
Time: 3.733
Time: 3.750
Time: 3.761
Time: 3.737
Time: 3.741
avg : 3.74
std. dev. : 0.01
1 CPU, replace smp lock prefixes with 0x90 nops
make -j1 kernel/
real 0m34.139s
user 0m30.782s
sys 0m2.820s
real 0m34.010s
user 0m30.630s
sys 0m2.976s
real 0m34.777s
user 0m30.658s
sys 0m2.916s
real 0m33.924s
user 0m30.634s
sys 0m2.924s
real 0m33.962s
user 0m30.774s
sys 0m2.800s
real 0m34.141s
user 0m30.770s
sys 0m2.828s
avg : 34.16
std. dev. : 0.32
hackbench 50
Time: 2.999
Time: 2.994
Time: 3.004
Time: 2.991
Time: 2.988
avg : 3.00
std. dev. : 0.01
I did more runs (20 runs of each) to compare the nop case to the DS
prefix case. Results in seconds. They actually does not seems to show a
significant difference.
NOP
34.155
33.955
34.012
35.299
35.679
34.141
33.995
35.016
34.254
33.957
33.957
34.008
35.013
34.494
33.893
34.295
34.314
34.854
33.991
34.132
DS
34.080
34.304
34.374
35.095
34.291
34.135
33.940
34.208
35.276
34.288
33.861
33.898
34.610
34.709
33.851
34.256
35.161
34.283
33.865
35.078
Used http://www.graphpad.com/quickcalcs/ttest1.cfm?Format=C to do the
T-test (yeah, I'm lazy) :
Group Group One (DS prefix) Group Two (nops)
Mean 34.37815 34.37070
SD 0.46108 0.51905
SEM 0.10310 0.11606
N 20 20
P value and statistical significance:
The two-tailed P value equals 0.9620
By conventional criteria, this difference is considered to be not statistically significant.
Confidence interval:
The mean of Group One minus Group Two equals 0.00745
95% confidence interval of this difference: From -0.30682 to 0.32172
Intermediate values used in calculations:
t = 0.0480
df = 38
standard error of difference = 0.155
So, unless these calculus are completely bogus, the difference between the nop
and the DS case seems not to be statistically significant.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Acked-by: H. Peter Anvin <hpa@zytor.com>
CC: Linus Torvalds <torvalds@linux-foundation.org>
CC: Jeremy Fitzhardinge <jeremy@goop.org>
CC: Roland McGrath <roland@redhat.com>
CC: Ingo Molnar <mingo@elte.hu>
Cc: Steven Rostedt <rostedt@goodmis.org>
CC: Steven Rostedt <srostedt@redhat.com>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: Peter Zijlstra <peterz@infradead.org>
CC: Andrew Morton <akpm@linux-foundation.org>
CC: David Miller <davem@davemloft.net>
CC: Ulrich Drepper <drepper@redhat.com>
CC: Rusty Russell <rusty@rustcorp.com.au>
CC: Gregory Haskins <ghaskins@novell.com>
CC: Arnaldo Carvalho de Melo <acme@redhat.com>
CC: "Luis Claudio R. Goncalves" <lclaudio@uudg.org>
CC: Clark Williams <williams@redhat.com>
CC: Christoph Lameter <cl@linux-foundation.org>
CC: Andi Kleen <andi@firstfloor.org>
CC: Harvey Harrison <harvey.harrison@gmail.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
2008-08-14 20:58:15 +00:00
|
|
|
/* turn lock prefix into DS segment override prefix */
|
2010-04-29 23:53:17 +00:00
|
|
|
if (*ptr == 0xf0)
|
|
|
|
text_poke(ptr, ((unsigned char []){0x3E}), 1);
|
2012-09-18 16:36:14 +00:00
|
|
|
}
|
2009-03-06 15:37:22 +00:00
|
|
|
mutex_unlock(&text_mutex);
|
2006-03-23 10:59:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
struct smp_alt_module {
|
|
|
|
/* what is this ??? */
|
|
|
|
struct module *mod;
|
|
|
|
char *name;
|
|
|
|
|
|
|
|
/* ptrs to lock prefixes */
|
2010-04-21 15:08:14 +00:00
|
|
|
const s32 *locks;
|
|
|
|
const s32 *locks_end;
|
2006-03-23 10:59:32 +00:00
|
|
|
|
|
|
|
/* .text segment, needed to avoid patching init code ;) */
|
|
|
|
u8 *text;
|
|
|
|
u8 *text_end;
|
|
|
|
|
|
|
|
struct list_head next;
|
|
|
|
};
|
|
|
|
static LIST_HEAD(smp_alt_modules);
|
2008-05-12 19:21:01 +00:00
|
|
|
static DEFINE_MUTEX(smp_alt);
|
2012-08-06 07:59:49 +00:00
|
|
|
static bool uniproc_patched = false; /* protected by smp_alt */
|
2006-03-23 10:59:32 +00:00
|
|
|
|
2009-08-19 07:40:48 +00:00
|
|
|
void __init_or_module alternatives_smp_module_add(struct module *mod,
|
|
|
|
char *name,
|
|
|
|
void *locks, void *locks_end,
|
|
|
|
void *text, void *text_end)
|
2006-03-23 10:59:32 +00:00
|
|
|
{
|
|
|
|
struct smp_alt_module *smp;
|
|
|
|
|
2012-08-06 07:59:49 +00:00
|
|
|
mutex_lock(&smp_alt);
|
|
|
|
if (!uniproc_patched)
|
|
|
|
goto unlock;
|
2007-05-02 17:27:13 +00:00
|
|
|
|
2012-08-06 07:59:49 +00:00
|
|
|
if (num_possible_cpus() == 1)
|
|
|
|
/* Don't bother remembering, we'll never have to undo it. */
|
|
|
|
goto smp_unlock;
|
2006-03-23 10:59:32 +00:00
|
|
|
|
|
|
|
smp = kzalloc(sizeof(*smp), GFP_KERNEL);
|
|
|
|
if (NULL == smp)
|
2012-08-06 07:59:49 +00:00
|
|
|
/* we'll run the (safe but slow) SMP code then ... */
|
|
|
|
goto unlock;
|
2006-03-23 10:59:32 +00:00
|
|
|
|
|
|
|
smp->mod = mod;
|
|
|
|
smp->name = name;
|
|
|
|
smp->locks = locks;
|
|
|
|
smp->locks_end = locks_end;
|
|
|
|
smp->text = text;
|
|
|
|
smp->text_end = text_end;
|
2014-12-30 19:27:09 +00:00
|
|
|
DPRINTK("locks %p -> %p, text %p -> %p, name %s\n",
|
|
|
|
smp->locks, smp->locks_end,
|
2006-03-23 10:59:32 +00:00
|
|
|
smp->text, smp->text_end, smp->name);
|
|
|
|
|
|
|
|
list_add_tail(&smp->next, &smp_alt_modules);
|
2012-08-06 07:59:49 +00:00
|
|
|
smp_unlock:
|
|
|
|
alternatives_smp_unlock(locks, locks_end, text, text_end);
|
|
|
|
unlock:
|
2008-05-12 19:21:01 +00:00
|
|
|
mutex_unlock(&smp_alt);
|
2006-03-23 10:59:32 +00:00
|
|
|
}
|
|
|
|
|
2009-08-19 07:40:48 +00:00
|
|
|
void __init_or_module alternatives_smp_module_del(struct module *mod)
|
2006-03-23 10:59:32 +00:00
|
|
|
{
|
|
|
|
struct smp_alt_module *item;
|
|
|
|
|
2008-05-12 19:21:01 +00:00
|
|
|
mutex_lock(&smp_alt);
|
2006-03-23 10:59:32 +00:00
|
|
|
list_for_each_entry(item, &smp_alt_modules, next) {
|
|
|
|
if (mod != item->mod)
|
|
|
|
continue;
|
|
|
|
list_del(&item->next);
|
|
|
|
kfree(item);
|
2012-08-06 07:59:49 +00:00
|
|
|
break;
|
2006-03-23 10:59:32 +00:00
|
|
|
}
|
2008-05-12 19:21:01 +00:00
|
|
|
mutex_unlock(&smp_alt);
|
2006-03-23 10:59:32 +00:00
|
|
|
}
|
|
|
|
|
2012-08-06 07:59:49 +00:00
|
|
|
void alternatives_enable_smp(void)
|
2006-03-23 10:59:32 +00:00
|
|
|
{
|
|
|
|
struct smp_alt_module *mod;
|
|
|
|
|
2012-08-06 07:59:49 +00:00
|
|
|
/* Why bother if there are no other CPUs? */
|
|
|
|
BUG_ON(num_possible_cpus() == 1);
|
2006-03-23 10:59:32 +00:00
|
|
|
|
2008-05-12 19:21:01 +00:00
|
|
|
mutex_lock(&smp_alt);
|
2008-01-30 12:33:17 +00:00
|
|
|
|
2012-08-06 07:59:49 +00:00
|
|
|
if (uniproc_patched) {
|
2012-05-22 02:50:07 +00:00
|
|
|
pr_info("switching to SMP code\n");
|
2012-08-06 07:59:49 +00:00
|
|
|
BUG_ON(num_online_cpus() != 1);
|
2008-01-30 12:30:55 +00:00
|
|
|
clear_cpu_cap(&boot_cpu_data, X86_FEATURE_UP);
|
|
|
|
clear_cpu_cap(&cpu_data(0), X86_FEATURE_UP);
|
2006-03-23 10:59:32 +00:00
|
|
|
list_for_each_entry(mod, &smp_alt_modules, next)
|
|
|
|
alternatives_smp_lock(mod->locks, mod->locks_end,
|
|
|
|
mod->text, mod->text_end);
|
2012-08-06 07:59:49 +00:00
|
|
|
uniproc_patched = false;
|
2006-03-23 10:59:32 +00:00
|
|
|
}
|
2008-05-12 19:21:01 +00:00
|
|
|
mutex_unlock(&smp_alt);
|
2006-03-23 10:59:32 +00:00
|
|
|
}
|
|
|
|
|
2010-02-02 21:49:11 +00:00
|
|
|
/* Return 1 if the address range is reserved for smp-alternatives */
|
|
|
|
int alternatives_text_reserved(void *start, void *end)
|
|
|
|
{
|
|
|
|
struct smp_alt_module *mod;
|
2010-04-21 15:08:14 +00:00
|
|
|
const s32 *poff;
|
2010-02-05 17:16:47 +00:00
|
|
|
u8 *text_start = start;
|
|
|
|
u8 *text_end = end;
|
2010-02-02 21:49:11 +00:00
|
|
|
|
|
|
|
list_for_each_entry(mod, &smp_alt_modules, next) {
|
2010-02-05 17:16:47 +00:00
|
|
|
if (mod->text > text_end || mod->text_end < text_start)
|
2010-02-02 21:49:11 +00:00
|
|
|
continue;
|
2010-04-21 15:08:14 +00:00
|
|
|
for (poff = mod->locks; poff < mod->locks_end; poff++) {
|
|
|
|
const u8 *ptr = (const u8 *)poff + *poff;
|
|
|
|
|
|
|
|
if (text_start <= ptr && text_end > ptr)
|
2010-02-02 21:49:11 +00:00
|
|
|
return 1;
|
2010-04-21 15:08:14 +00:00
|
|
|
}
|
2010-02-02 21:49:11 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
x86/alternatives: Make JMPs more robust
Up until now we had to pay attention to relative JMPs in alternatives
about how their relative offset gets computed so that the jump target
is still correct. Or, as it is the case for near CALLs (opcode e8), we
still have to go and readjust the offset at patching time.
What is more, the static_cpu_has_safe() facility had to forcefully
generate 5-byte JMPs since we couldn't rely on the compiler to generate
properly sized ones so we had to force the longest ones. Worse than
that, sometimes it would generate a replacement JMP which is longer than
the original one, thus overwriting the beginning of the next instruction
at patching time.
So, in order to alleviate all that and make using JMPs more
straight-forward we go and pad the original instruction in an
alternative block with NOPs at build time, should the replacement(s) be
longer. This way, alternatives users shouldn't pay special attention
so that original and replacement instruction sizes are fine but the
assembler would simply add padding where needed and not do anything
otherwise.
As a second aspect, we go and recompute JMPs at patching time so that we
can try to make 5-byte JMPs into two-byte ones if possible. If not, we
still have to recompute the offsets as the replacement JMP gets put far
away in the .altinstr_replacement section leading to a wrong offset if
copied verbatim.
For example, on a locally generated kernel image
old insn VA: 0xffffffff810014bd, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff810014bd: eb 21 jmp ffffffff810014e0
repl insn: size: 5
ffffffff81d0b23c: e9 b1 62 2f ff jmpq ffffffff810014f2
gets corrected to a 2-byte JMP:
apply_alternatives: feat: 3*32+21, old: (ffffffff810014bd, len: 2), repl: (ffffffff81d0b23c, len: 5)
alt_insn: e9 b1 62 2f ff
recompute_jumps: next_rip: ffffffff81d0b241, tgt_rip: ffffffff810014f2, new_displ: 0x00000033, ret len: 2
converted to: eb 33 90 90 90
and a 5-byte JMP:
old insn VA: 0xffffffff81001516, CPU feat: X86_FEATURE_ALWAYS, size: 2
__switch_to:
ffffffff81001516: eb 30 jmp ffffffff81001548
repl insn: size: 5
ffffffff81d0b241: e9 10 63 2f ff jmpq ffffffff81001556
gets shortened into a two-byte one:
apply_alternatives: feat: 3*32+21, old: (ffffffff81001516, len: 2), repl: (ffffffff81d0b241, len: 5)
alt_insn: e9 10 63 2f ff
recompute_jumps: next_rip: ffffffff81d0b246, tgt_rip: ffffffff81001556, new_displ: 0x0000003e, ret len: 2
converted to: eb 3e 90 90 90
... and so on.
This leads to a net win of around
40ish replacements * 3 bytes savings =~ 120 bytes of I$
on an AMD guest which means some savings of precious instruction cache
bandwidth. The padding to the shorter 2-byte JMPs are single-byte NOPs
which on smart microarchitectures means discarding NOPs at decode time
and thus freeing up execution bandwidth.
Signed-off-by: Borislav Petkov <bp@suse.de>
2015-01-05 12:48:41 +00:00
|
|
|
#endif /* CONFIG_SMP */
|
2006-07-01 11:36:18 +00:00
|
|
|
|
2006-12-07 01:14:08 +00:00
|
|
|
#ifdef CONFIG_PARAVIRT
|
2009-08-19 07:40:48 +00:00
|
|
|
void __init_or_module apply_paravirt(struct paravirt_patch_site *start,
|
|
|
|
struct paravirt_patch_site *end)
|
2006-12-07 01:14:08 +00:00
|
|
|
{
|
2007-05-02 17:27:14 +00:00
|
|
|
struct paravirt_patch_site *p;
|
2007-08-10 20:31:03 +00:00
|
|
|
char insnbuf[MAX_PATCH_LEN];
|
2006-12-07 01:14:08 +00:00
|
|
|
|
2007-05-02 17:27:16 +00:00
|
|
|
if (noreplace_paravirt)
|
|
|
|
return;
|
|
|
|
|
2006-12-07 01:14:08 +00:00
|
|
|
for (p = start; p < end; p++) {
|
|
|
|
unsigned int used;
|
|
|
|
|
2007-08-10 20:31:03 +00:00
|
|
|
BUG_ON(p->len > MAX_PATCH_LEN);
|
2007-08-18 21:31:41 +00:00
|
|
|
/* prep the buffer with the original instructions */
|
|
|
|
memcpy(insnbuf, p->instr, p->len);
|
2007-10-16 18:51:29 +00:00
|
|
|
used = pv_init_ops.patch(p->instrtype, p->clobbers, insnbuf,
|
|
|
|
(unsigned long)p->instr, p->len);
|
2007-05-02 17:27:13 +00:00
|
|
|
|
2007-05-02 17:27:14 +00:00
|
|
|
BUG_ON(used > p->len);
|
|
|
|
|
2006-12-07 01:14:08 +00:00
|
|
|
/* Pad the rest with nops */
|
2007-08-10 20:31:03 +00:00
|
|
|
add_nops(insnbuf + used, p->len - used);
|
2008-03-06 13:48:49 +00:00
|
|
|
text_poke_early(p->instr, insnbuf, p->len);
|
2006-12-07 01:14:08 +00:00
|
|
|
}
|
|
|
|
}
|
2007-05-02 17:27:14 +00:00
|
|
|
extern struct paravirt_patch_site __start_parainstructions[],
|
2006-12-07 01:14:08 +00:00
|
|
|
__stop_parainstructions[];
|
|
|
|
#endif /* CONFIG_PARAVIRT */
|
|
|
|
|
2006-03-23 10:59:32 +00:00
|
|
|
void __init alternative_instructions(void)
|
|
|
|
{
|
2007-07-22 09:12:32 +00:00
|
|
|
/* The patching is not fully atomic, so try to avoid local interruptions
|
|
|
|
that might execute the to be patched code.
|
|
|
|
Other CPUs are not running. */
|
|
|
|
stop_nmi();
|
2009-02-12 12:39:27 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Don't stop machine check exceptions while patching.
|
|
|
|
* MCEs only happen when something got corrupted and in this
|
|
|
|
* case we must do something about the corruption.
|
|
|
|
* Ignoring it is worse than a unlikely patching race.
|
|
|
|
* Also machine checks tend to be broadcast and if one CPU
|
|
|
|
* goes into machine check the others follow quickly, so we don't
|
|
|
|
* expect a machine check to cause undue problems during to code
|
|
|
|
* patching.
|
|
|
|
*/
|
2007-07-22 09:12:32 +00:00
|
|
|
|
2006-03-23 10:59:32 +00:00
|
|
|
apply_alternatives(__alt_instructions, __alt_instructions_end);
|
|
|
|
|
2006-07-01 11:36:18 +00:00
|
|
|
#ifdef CONFIG_SMP
|
2012-08-06 07:59:49 +00:00
|
|
|
/* Patch to UP if other cpus not imminent. */
|
|
|
|
if (!noreplace_smp && (num_present_cpus() == 1 || setup_max_cpus <= 1)) {
|
|
|
|
uniproc_patched = true;
|
2006-03-23 10:59:32 +00:00
|
|
|
alternatives_smp_module_add(NULL, "core kernel",
|
|
|
|
__smp_locks, __smp_locks_end,
|
|
|
|
_text, _etext);
|
|
|
|
}
|
2007-07-22 09:12:32 +00:00
|
|
|
|
2012-08-06 07:59:49 +00:00
|
|
|
if (!uniproc_patched || num_possible_cpus() == 1)
|
2007-10-17 16:04:34 +00:00
|
|
|
free_init_pages("SMP alternatives",
|
|
|
|
(unsigned long)__smp_locks,
|
|
|
|
(unsigned long)__smp_locks_end);
|
2012-08-06 07:59:49 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
apply_paravirt(__parainstructions, __parainstructions_end);
|
2007-10-17 16:04:34 +00:00
|
|
|
|
2007-07-22 09:12:32 +00:00
|
|
|
restart_nmi();
|
2006-03-23 10:59:32 +00:00
|
|
|
}
|
2007-07-22 09:12:31 +00:00
|
|
|
|
2008-03-06 13:48:49 +00:00
|
|
|
/**
|
|
|
|
* text_poke_early - Update instructions on a live kernel at boot time
|
|
|
|
* @addr: address to modify
|
|
|
|
* @opcode: source of the copy
|
|
|
|
* @len: length to copy
|
|
|
|
*
|
2007-07-22 09:12:31 +00:00
|
|
|
* When you use this code to patch more than one byte of an instruction
|
|
|
|
* you need to make sure that other CPUs cannot execute this code in parallel.
|
2008-03-06 13:48:49 +00:00
|
|
|
* Also no thread must be currently preempted in the middle of these
|
|
|
|
* instructions. And on the local CPU you need to be protected again NMI or MCE
|
|
|
|
* handlers seeing an inconsistent instruction while you patch.
|
2007-07-22 09:12:31 +00:00
|
|
|
*/
|
2010-09-17 15:08:56 +00:00
|
|
|
void *__init_or_module text_poke_early(void *addr, const void *opcode,
|
2009-08-19 07:40:48 +00:00
|
|
|
size_t len)
|
2007-07-22 09:12:31 +00:00
|
|
|
{
|
2008-03-06 13:48:49 +00:00
|
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
2007-07-22 09:12:31 +00:00
|
|
|
memcpy(addr, opcode, len);
|
2008-03-06 13:48:49 +00:00
|
|
|
sync_core();
|
2009-09-10 01:53:50 +00:00
|
|
|
local_irq_restore(flags);
|
2008-03-06 13:48:49 +00:00
|
|
|
/* Could also do a CLFLUSH here to speed up CPU recovery; but
|
|
|
|
that causes hangs on some VIA CPUs. */
|
|
|
|
return addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* text_poke - Update instructions on a live kernel
|
|
|
|
* @addr: address to modify
|
|
|
|
* @opcode: source of the copy
|
|
|
|
* @len: length to copy
|
|
|
|
*
|
|
|
|
* Only atomic text poke/set should be allowed when not doing early patching.
|
|
|
|
* It means the size must be writable atomically and the address must be aligned
|
|
|
|
* in a way that permits an atomic write. It also makes sure we fit on a single
|
|
|
|
* page.
|
2009-03-06 15:37:54 +00:00
|
|
|
*
|
|
|
|
* Note: Must be called under text_mutex.
|
2008-03-06 13:48:49 +00:00
|
|
|
*/
|
2014-04-17 08:18:07 +00:00
|
|
|
void *text_poke(void *addr, const void *opcode, size_t len)
|
2008-03-06 13:48:49 +00:00
|
|
|
{
|
2009-03-06 15:37:54 +00:00
|
|
|
unsigned long flags;
|
2008-03-06 13:48:49 +00:00
|
|
|
char *vaddr;
|
2008-04-24 15:03:33 +00:00
|
|
|
struct page *pages[2];
|
|
|
|
int i;
|
2008-03-06 13:48:49 +00:00
|
|
|
|
2008-04-24 15:03:33 +00:00
|
|
|
if (!core_kernel_text((unsigned long)addr)) {
|
|
|
|
pages[0] = vmalloc_to_page(addr);
|
|
|
|
pages[1] = vmalloc_to_page(addr + PAGE_SIZE);
|
x86: fix test_poke for vmalloced pages
* Ingo Molnar (mingo@elte.hu) wrote:
>
> * Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> wrote:
>
> > The shadow vmap for DEBUG_RODATA kernel text modification uses
> > virt_to_page to get the pages from the pointer address.
> >
> > However, I think vmalloc_to_page would be required in case the page is
> > used for modules.
> >
> > Since only the core kernel text is marked read-only, use
> > kernel_text_address() to make sure we only shadow map the core kernel
> > text, not modules.
>
> actually, i think we should mark module text readonly too.
>
Yes, but in the meantime, the x86 tree would need this patch to make
kprobes work correctly on modules.
I suspect that without this fix, with the enhanced hotplug and kprobes
patch, kprobes will use text_poke to insert breakpoints in modules
(vmalloced pages used), which will map the wrong pages and corrupt
random kernel locations instead of updating the correct page.
Work that would write protect the module pages should clearly be done,
but it can come in a later time. We have to make sure we interact
correctly with the page allocation debugging, as an example.
Here is the patch against x86.git 2.6.25-rc5 :
The shadow vmap for DEBUG_RODATA kernel text modification uses virt_to_page to
get the pages from the pointer address.
However, I think vmalloc_to_page would be required in case the page is used for
modules.
Since only the core kernel text is marked read-only, use kernel_text_address()
to make sure we only shadow map the core kernel text, not modules.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
CC: akpm@linux-foundation.org
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2008-03-12 15:54:16 +00:00
|
|
|
} else {
|
2008-04-24 15:03:33 +00:00
|
|
|
pages[0] = virt_to_page(addr);
|
2008-04-25 15:07:03 +00:00
|
|
|
WARN_ON(!PageReserved(pages[0]));
|
2008-04-24 15:03:33 +00:00
|
|
|
pages[1] = virt_to_page(addr + PAGE_SIZE);
|
2008-03-06 13:48:49 +00:00
|
|
|
}
|
2008-04-24 15:03:33 +00:00
|
|
|
BUG_ON(!pages[0]);
|
2009-03-09 16:40:40 +00:00
|
|
|
local_irq_save(flags);
|
2009-03-06 15:37:54 +00:00
|
|
|
set_fixmap(FIX_TEXT_POKE0, page_to_phys(pages[0]));
|
|
|
|
if (pages[1])
|
|
|
|
set_fixmap(FIX_TEXT_POKE1, page_to_phys(pages[1]));
|
|
|
|
vaddr = (char *)fix_to_virt(FIX_TEXT_POKE0);
|
2008-04-24 15:03:33 +00:00
|
|
|
memcpy(&vaddr[(unsigned long)addr & ~PAGE_MASK], opcode, len);
|
2009-03-06 15:37:54 +00:00
|
|
|
clear_fixmap(FIX_TEXT_POKE0);
|
|
|
|
if (pages[1])
|
|
|
|
clear_fixmap(FIX_TEXT_POKE1);
|
|
|
|
local_flush_tlb();
|
2007-07-22 09:12:31 +00:00
|
|
|
sync_core();
|
2007-09-06 14:59:52 +00:00
|
|
|
/* Could also do a CLFLUSH here to speed up CPU recovery; but
|
|
|
|
that causes hangs on some VIA CPUs. */
|
2008-04-24 15:03:33 +00:00
|
|
|
for (i = 0; i < len; i++)
|
|
|
|
BUG_ON(((char *)addr)[i] != ((char *)opcode)[i]);
|
2009-03-09 16:40:40 +00:00
|
|
|
local_irq_restore(flags);
|
2008-03-06 13:48:49 +00:00
|
|
|
return addr;
|
2007-07-22 09:12:31 +00:00
|
|
|
}
|
2010-02-25 13:34:38 +00:00
|
|
|
|
2013-07-12 09:21:48 +00:00
|
|
|
static void do_sync_core(void *info)
|
|
|
|
{
|
|
|
|
sync_core();
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool bp_patching_in_progress;
|
|
|
|
static void *bp_int3_handler, *bp_int3_addr;
|
|
|
|
|
2013-07-23 08:09:28 +00:00
|
|
|
int poke_int3_handler(struct pt_regs *regs)
|
2013-07-12 09:21:48 +00:00
|
|
|
{
|
|
|
|
/* bp_patching_in_progress */
|
|
|
|
smp_rmb();
|
|
|
|
|
|
|
|
if (likely(!bp_patching_in_progress))
|
2013-07-23 08:09:28 +00:00
|
|
|
return 0;
|
2013-07-12 09:21:48 +00:00
|
|
|
|
2015-03-19 01:33:33 +00:00
|
|
|
if (user_mode(regs) || regs->ip != (unsigned long)bp_int3_addr)
|
2013-07-23 08:09:28 +00:00
|
|
|
return 0;
|
2013-07-12 09:21:48 +00:00
|
|
|
|
|
|
|
/* set up the specified breakpoint handler */
|
2013-07-23 08:09:28 +00:00
|
|
|
regs->ip = (unsigned long) bp_int3_handler;
|
|
|
|
|
|
|
|
return 1;
|
2013-07-12 09:21:48 +00:00
|
|
|
|
|
|
|
}
|
2013-07-23 08:09:28 +00:00
|
|
|
|
2013-07-12 09:21:48 +00:00
|
|
|
/**
|
|
|
|
* text_poke_bp() -- update instructions on live kernel on SMP
|
|
|
|
* @addr: address to patch
|
|
|
|
* @opcode: opcode of new instruction
|
|
|
|
* @len: length to copy
|
|
|
|
* @handler: address to jump to when the temporary breakpoint is hit
|
|
|
|
*
|
|
|
|
* Modify multi-byte instruction by using int3 breakpoint on SMP.
|
2013-07-18 11:47:53 +00:00
|
|
|
* We completely avoid stop_machine() here, and achieve the
|
|
|
|
* synchronization using int3 breakpoint.
|
2013-07-12 09:21:48 +00:00
|
|
|
*
|
|
|
|
* The way it is done:
|
|
|
|
* - add a int3 trap to the address that will be patched
|
|
|
|
* - sync cores
|
|
|
|
* - update all but the first byte of the patched range
|
|
|
|
* - sync cores
|
|
|
|
* - replace the first byte (int3) by the first byte of
|
|
|
|
* replacing opcode
|
|
|
|
* - sync cores
|
|
|
|
*
|
|
|
|
* Note: must be called under text_mutex.
|
|
|
|
*/
|
|
|
|
void *text_poke_bp(void *addr, const void *opcode, size_t len, void *handler)
|
|
|
|
{
|
|
|
|
unsigned char int3 = 0xcc;
|
|
|
|
|
|
|
|
bp_int3_handler = handler;
|
|
|
|
bp_int3_addr = (u8 *)addr + sizeof(int3);
|
|
|
|
bp_patching_in_progress = true;
|
|
|
|
/*
|
|
|
|
* Corresponding read barrier in int3 notifier for
|
|
|
|
* making sure the in_progress flags is correctly ordered wrt.
|
|
|
|
* patching
|
|
|
|
*/
|
|
|
|
smp_wmb();
|
|
|
|
|
|
|
|
text_poke(addr, &int3, sizeof(int3));
|
|
|
|
|
|
|
|
on_each_cpu(do_sync_core, NULL, 1);
|
|
|
|
|
|
|
|
if (len - sizeof(int3) > 0) {
|
|
|
|
/* patch all but the first byte */
|
|
|
|
text_poke((char *)addr + sizeof(int3),
|
|
|
|
(const char *) opcode + sizeof(int3),
|
|
|
|
len - sizeof(int3));
|
|
|
|
/*
|
|
|
|
* According to Intel, this core syncing is very likely
|
|
|
|
* not necessary and we'd be safe even without it. But
|
|
|
|
* better safe than sorry (plus there's not only Intel).
|
|
|
|
*/
|
|
|
|
on_each_cpu(do_sync_core, NULL, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* patch the first byte */
|
|
|
|
text_poke(addr, opcode, sizeof(int3));
|
|
|
|
|
|
|
|
on_each_cpu(do_sync_core, NULL, 1);
|
|
|
|
|
|
|
|
bp_patching_in_progress = false;
|
|
|
|
smp_wmb();
|
|
|
|
|
|
|
|
return addr;
|
|
|
|
}
|
|
|
|
|