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linux/arch/arm/mach-tegra/Makefile

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ARM: tegra: build assembly files with -march=armv7-a The tegra assembly files are written for ARMv7 and are not compatible with ARMv6, which leads to build warnings when compiling a dual ARMv6/v7 kernel. Since this code is only ever run on Tegra ARMv7 hardware, we can tell the assembler which architecture level to use. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-09 19:58:38 +00:00
asflags-y += -march=armv7-a
[ARM] tegra: initial tegra support v2: Fixes from Mike Rapoport - remove unused header files (mach/dma.h and mach/nand.h) - remove tegra 1 references from Makefile.boot v2: fixes from Russell King - remove mach/io.h include from mach/iomap.h - fix whitespace in Kconfig v2: from Colin Cross - fix invalid immediate in debug-macro.S v3: - allow selection of multiple boards Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com>
2010-01-22 00:53:02 +00:00
obj-y += io.o
ARM: tegra: irq: Move legacy_irq.c into irq.c Now that irq.c is just an interface layer between the gic and legacy_irq.c, move the contents of legacy_irq.c into irq.c. Signed-off-by: Colin Cross <ccross@android.com>
2011-05-01 22:26:51 +00:00
obj-y += irq.o
[ARM] tegra: Add support for reading fuses The Tegra SOC contains fuses to identify the CPU type and bin, and a unique id. The CPU info is required to determine the correct voltages for each cpu and core frequency. Signed-off-by: Colin Cross <ccross@android.com>
2010-06-23 22:49:17 +00:00
obj-y += fuse.o
ARM: tegra: Add a simple PMC driver This PMC driver is enough to parse the nvidia,invert-interrupt property from device tree, and configure the PMC's to honor that. In the future, this file could expand to centralize all other PMC accesses within the mach-tegra code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-01-25 21:43:28 +00:00
obj-y += pmc.o
ARM: tegra: functions to access the flowcontroller Introduce some functions to write to the flowcontroller registers. The flowcontroller controls CPU sleepstates and wakeup. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-02-09 23:47:44 +00:00
obj-y += flowctrl.o
ARM: tegra: build powergate unconditionally powergate functions are needed for tegra30 as well (see common.c), so build it always. Fixes: arch/arm/mach-tegra/built-in.o: In function `tegra30_init_early': apbio.c:(.init.text+0x78): undefined reference to `tegra_powergate_init' (using "allnoconfig" with tegra30 enabled) Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-13 13:55:47 +00:00
obj-y += powergate.o
ARM: tegra: apbio access using dma for tegra20 only The Tegra20 HW issue with accessing APBIO registers (such as fuse registers) directly from the CPU concurrently with APB DMA accesses has been fixed in Tegra30 and later chips. Access these registers directly from the CPU on Tegra30 and later, and apply the workaround only for Tegra20. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Chaitanya Bandi <bandik@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-20 12:36:34 +00:00
obj-y += apbio.o
ARM: tegra30: cpuidle: add powered-down state for secondary CPUs This supports power-gated idle on secondary CPUs for Tegra30. The secondary CPUs can go into powered-down state independently. When CPU goes into this state, it saves it's contexts and puts itself to flow controlled WFI state. After that, it will been power gated. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-31 09:41:17 +00:00
obj-y += pm.o
ARM: tegra: make device can run on UP The reset handler code is used for either UP or SMP. To make Tegra device can compile for UP. It needs to be moved to another file that is not SMP only. This is because the reset handler also be needed by CPU idle "powered-down" mode. So we also need to put the reset handler init function in non-SMP only and init them always. And currently the implementation of the reset handler to know which CPU is OK to bring up was identital with "cpu_present_mask". But the "cpu_present_mask" did not initialize yet when the reset handler init function was moved to init early function. We use the "cpu_possible_mask" to replace "cpu_present_mask". Then it can work on both UP and SMP case. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren: dropped the move of v7_invalidate_l1() from one file to another, to avoid conflicts with Pavel's cleanup of this function, adjust Makefile so each line only contains 1 file.] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-04 09:32:22 +00:00
obj-y += reset.o
obj-y += reset-handler.o
ARM: tegra: fix compile error when disable CPU_IDLE The "sleep.S" file has many functions that be shared by different module currently. Not just for CPU idle driver. Make it build as default now. Reported-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren: add sleep.o to separate line so each line only contains 1 file] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-25 06:38:32 +00:00
obj-y += sleep.o
ARM: tegra: Unify Device tree board files Unify board-dt-tegra{30,114} to the Tegra20 DT board file, "tegra.c". Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-02-13 17:15:50 +00:00
obj-y += tegra.o
ARM: tegra: Avoid compiling cpuidle code when not configured No need to compile cpuidle.c and sleep.S if cpuidle isn't configured in the kernel. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-02-23 16:21:52 +00:00
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
ARM: tegra: Add speedo-based process identification Detect CPU and core process ID by checking speedo corner tables. This can provide a more accurate process ID. Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren s/Tegra2/Tegra20/ in log print] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-15 07:42:33 +00:00
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o
ARM: tegra: Add external memory controller driver The frequency memory bus on Tegra can be adjusted without disabling accesses to memory by updating the memory configuration registers from a per-board table, and then changing the clock frequency. The clock controller and memory controller have an interlock that prevents the new memory registers from taking effect until the clock frequency change. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
2011-02-13 02:22:49 +00:00
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
ARM: tegra: rename the file of "sleep-tXX" to "sleep-tegraXX" For the naming consistency under the mach-tegra, we re-name the file of "sleep-tXX" to "sleep-tegraXX" (e.g., sleep-t30 to sleep-tegra30). Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-08 00:23:57 +00:00
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o
ARM: tegra: add LP1 suspend support for Tegra20 The LP1 suspend mode will power off the CPU, clock gated the PLLs and put SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The sequence when LP1 suspending: * tunning off L1 data cache and the MMU * putting SDRAM into self-refresh * storing some EMC registers and SCLK burst policy * switching CPU to CLK_M (12MHz OSC) * switching SCLK to CLK_S (32KHz OSC) * tunning off PLLM, PLLP and PLLC * shutting off the CPU rail The sequence of LP1 resuming: * re-enabling PLLM, PLLP, and PLLC * restoring some EMC registers and SCLK burst policy * setting up CCLK burst policy to PLLP * resuming SDRAM to normal mode * jumping to the "tegra_resume" from PMC_SCRATCH41 Due to the SDRAM will be put into self-refresh mode, the low level procedures of LP1 suspending and resuming should be copied to TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before restoring the CPU context when resuming, the SDRAM needs to be switched back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy be restored, CCLK burst policy be set in PLLP. Then jumping to "tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore CPU context and back to kernel. Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12 09:40:05 +00:00
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o
ARM: tegra: cpuidle: separate cpuidle driver for different chips The different Tegra chips may have different CPU idle states and data. Individual CPU idle driver make it more easy to maintain. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-31 09:41:15 +00:00
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o
endif
ARM: tegra: Tegra30 speedo-based process identification This patch adds speedo-based process identification support for Tegra30. Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren s/Tegra3/Tegra30/ in log print, s/T30/Tegra30/ in commit description] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-15 07:42:34 +00:00
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o
ARM: tegra: cpuidle: separate cpuidle driver for different chips The different Tegra chips may have different CPU idle states and data. Individual CPU idle driver make it more easy to maintain. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-31 09:41:15 +00:00
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o
ARM: tegra: add LP1 suspend support for Tegra30 The LP1 suspend mode will power off the CPU, clock gated the PLLs and put SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The sequence when LP1 suspending: * tunning off L1 data cache and the MMU * storing some EMC registers, DPD (deep power down) status, clk source of mselect and SCLK burst policy * putting SDRAM into self-refresh * switching CPU to CLK_M (12MHz OSC) * tunning off PLLM, PLLP, PLLA, PLLC and PLLX * switching SCLK to CLK_S (32KHz OSC) * shutting off the CPU rail The sequence of LP1 resuming: * re-enabling PLLM, PLLP, PLLA, PLLC and PLLX * restoring the clk source of mselect and SCLK burst policy * setting up CCLK burst policy to PLLX * restoring DPD status and some EMC registers * resuming SDRAM to normal mode * jumping to the "tegra_resume" from PMC_SCRATCH41 Due to the SDRAM will be put into self-refresh mode, the low level procedures of LP1 suspending and resuming should be copied to TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before restoring the CPU context when resuming, the SDRAM needs to be switched back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy be restored, CCLK burst policy be set in PLLX. Then jumping to "tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore CPU context and back to kernel. Based on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12 09:40:04 +00:00
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o
ARM: tegra: cpuidle: separate cpuidle driver for different chips The different Tegra chips may have different CPU idle states and data. Individual CPU idle driver make it more easy to maintain. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-31 09:41:15 +00:00
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
endif
ARM: tegra: build localtimer support only when needed It is possible to build a tegra kernel without localtimer support, so the tegra specific parts should only be built when that is indeed enabled. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alan Ott <alan@signal11.us> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-03-02 20:58:32 +00:00
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
[ARM] tegra: SMP support Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com>
2010-02-22 01:46:23 +00:00
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
[ARM] tegra: harmony: Add harmony board file v2: fixes from Russell King - include linux/io.h instead of mach/io.h v3: fixes from Linus Walleij - remove /16 * 16 from UART clock v3: - Fix checkpatch issues - make board init calls explicit - use clock init table to set clocks - remove panel Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Erik Gilling <konkers@android.com>
2010-02-11 01:13:07 +00:00
ARM: tegra: add speedo-based process id for Tegra114 Add speedo-based process identification for Tegra114. Based on the work by: Alex Frid <afrid@nvidia.com> Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren: added include of bug.h] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-18 11:17:34 +00:00
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o
ARM: tegra114: add CPU hotplug support The Tegra114 is a quad cores SoC. Each core can be hotplugged including CPU0. The hotplug sequence can be controlled by setting event trigger in flow controller. Then the flow controller will take care all the power sequence that include CPU up and down. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-05-20 10:39:29 +00:00
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
ARM: tegra: add LP1 suspend support for Tegra114 The LP1 suspend mode will power off the CPU, clock gated the PLLs and put SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The sequence when LP1 suspending: * tunning off L1 data cache and the MMU * storing some EMC registers, DPD (deep power down) status, clk source of mselect and SCLK burst policy * putting SDRAM into self-refresh * switching CPU to CLK_M (12MHz OSC) * tunning off PLLM, PLLP, PLLA, PLLC and PLLX * switching SCLK to CLK_S (32KHz OSC) * shutting off the CPU rail The sequence of LP1 resuming: * re-enabling PLLM, PLLP, PLLA, PLLC and PLLX * restoring the clk source of mselect and SCLK burst policy * setting up CCLK burst policy to PLLX * restoring DPD status and some EMC registers * resuming SDRAM to normal mode * jumping to the "tegra_resume" from PMC_SCRATCH41 Due to the SDRAM will be put into self-refresh mode, the low level procedures of LP1 suspending and resuming should be copied to TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before restoring the CPU context when resuming, the SDRAM needs to be switched back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy be restored. Then jumping to "tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore CPU context and back to kernel. Based on the work by: Bo Yan <byan@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12 09:40:06 +00:00
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o
ARM: tegra: add Tegra114 ARM_CPUIDLE_WFI_STATE support Adding the generic ARM_CPUIDLE_WFI_STATE support for Tegra114. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-21 09:49:06 +00:00
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o
endif
ARM: tegra: CPU hotplug support for Tegra124 The procedure of CPU hotplug for Tegra124 is same with Tegra114. We re-use the same function with it. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-11 09:57:30 +00:00
obj-$(CONFIG_ARCH_TEGRA_124_SOC) += sleep-tegra30.o
ARM: tegra: remove CONFIG_MACH_TEGRA_DT * Make ARCH_TEGRA select USE_OF; DT is the way forward. * Build board-dt-tegra*.c when the relevant Tegra SoC support is enabled, rather than requiring a specific config option for this. * The board-specific config options already build board-*-pinmux.o, and when booting from device tree these files are no longer needed, so we can remove some Makefile commands related to those files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-21 21:07:19 +00:00
ARM: tegra: remove board (but not DT) support for Paz00 Paz00 (Toshiba AC100) can be booted using device tree with equal functionality as when booted using a board file. Remove as much of the board file as is possible, since it's no longer needed. One special-case is still left in board-dt-tegra20.c, since there is no way to create a WiFi rfkill device from device tree yet. This logic is now enabled unconditionally rather than via CONFIG_MACH_PAZ00. The extra cases where it's enabled (.configs which did not enable Paz00 support) shouldn't impact much since the amount of code is tiny. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Marc Dietrich <marvin24@gmx.de>
2012-08-03 21:09:04 +00:00
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o
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