2012-05-10 07:42:30 +00:00
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NVIDIA Tegra20 MC(Memory Controller)
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Required properties:
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2018-12-12 20:38:49 +00:00
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- compatible : "nvidia,tegra20-mc-gart"
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- reg : Should contain 2 register ranges: physical base address and length of
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the controller's registers and the GART aperture respectively.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- mc: the module's clock input
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2012-05-10 07:42:30 +00:00
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- interrupts : Should contain MC General interrupt.
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2018-04-09 19:28:25 +00:00
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- #reset-cells : Should be 1. This cell represents memory client module ID.
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The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>
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or in the TRM documentation.
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2018-12-12 20:38:49 +00:00
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- #iommu-cells: Should be 0. This cell represents the number of cells in an
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IOMMU specifier needed to encode an address. GART supports only a single
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address space that is shared by all devices, therefore no additional
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information needed for the address encoding.
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2012-05-10 07:42:30 +00:00
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Example:
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2018-04-09 19:28:25 +00:00
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mc: memory-controller@7000f000 {
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2018-12-12 20:38:49 +00:00
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compatible = "nvidia,tegra20-mc-gart";
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reg = <0x7000f000 0x400 /* controller registers */
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0x58000000 0x02000000>; /* GART aperture */
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clocks = <&tegra_car TEGRA20_CLK_MC>;
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clock-names = "mc";
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interrupts = <GIC_SPI 77 0x04>;
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2018-04-09 19:28:25 +00:00
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#reset-cells = <1>;
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2018-12-12 20:38:49 +00:00
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#iommu-cells = <0>;
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2018-04-09 19:28:25 +00:00
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};
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video-codec@6001a000 {
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compatible = "nvidia,tegra20-vde";
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...
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resets = <&mc TEGRA20_MC_RESET_VDE>;
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2018-12-12 20:38:49 +00:00
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iommus = <&mc>;
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2012-05-10 07:42:30 +00:00
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};
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