2008-07-05 08:02:59 +00:00
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/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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2009-01-26 15:34:53 +00:00
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* This contains i.MX27-specific hardware definitions. For those
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* hardware pieces that are common between i.MX21 and i.MX27, have a
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* look at mx2x.h.
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*
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2008-07-05 08:02:59 +00:00
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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2010-01-08 15:02:30 +00:00
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#ifndef __MACH_MX27_H__
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#define __MACH_MX27_H__
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2008-07-05 08:02:59 +00:00
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2009-11-13 20:31:31 +00:00
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#define MX27_AIPI_BASE_ADDR 0x10000000
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#define MX27_AIPI_SIZE SZ_1M
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#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
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#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
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#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000)
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#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000)
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#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000)
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#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000)
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#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000)
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#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000)
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#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000)
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#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000)
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#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000)
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#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000)
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#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000)
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#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000)
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#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
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#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
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#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
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2010-06-16 15:25:40 +00:00
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#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
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2009-11-13 20:31:31 +00:00
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#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
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#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
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#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
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2010-11-11 09:52:33 +00:00
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#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000)
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#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100)
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#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200)
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#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300)
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#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400)
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#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500)
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2009-11-13 20:31:31 +00:00
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#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
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#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
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#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
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2011-03-10 19:55:04 +00:00
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#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
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#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
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2009-11-13 20:31:31 +00:00
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#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
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#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
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#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
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#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000)
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#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000)
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#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
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#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
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#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
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2010-11-05 17:52:09 +00:00
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#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
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#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000)
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#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200)
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#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400)
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2009-11-13 20:31:31 +00:00
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#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
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2010-11-02 16:50:55 +00:00
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#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
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#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
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2009-11-13 20:31:31 +00:00
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#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
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#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
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#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
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#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000)
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#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000)
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#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000)
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#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000)
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#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000)
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#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
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#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
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#define MX27_AVIC_BASE_ADDR 0x10040000
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2008-07-05 08:02:59 +00:00
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2009-01-26 15:34:53 +00:00
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/* ROM patch */
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2009-11-10 14:26:21 +00:00
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#define MX27_ROMP_BASE_ADDR 0x10041000
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2008-07-05 08:02:59 +00:00
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2009-11-13 20:31:31 +00:00
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#define MX27_SAHB1_BASE_ADDR 0x80000000
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#define MX27_SAHB1_SIZE SZ_1M
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#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
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#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
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2008-07-05 08:02:59 +00:00
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/* Memory regions and CS */
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2009-11-10 14:26:21 +00:00
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#define MX27_SDRAM_BASE_ADDR 0xa0000000
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#define MX27_CSD1_BASE_ADDR 0xb0000000
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2008-07-05 08:02:59 +00:00
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2009-11-10 14:26:21 +00:00
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#define MX27_CS0_BASE_ADDR 0xc0000000
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#define MX27_CS1_BASE_ADDR 0xc8000000
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#define MX27_CS2_BASE_ADDR 0xd0000000
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#define MX27_CS3_BASE_ADDR 0xd2000000
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#define MX27_CS4_BASE_ADDR 0xd4000000
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#define MX27_CS5_BASE_ADDR 0xd6000000
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2008-07-05 08:02:59 +00:00
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2009-01-26 15:34:53 +00:00
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/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
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2009-11-10 14:26:21 +00:00
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#define MX27_X_MEMC_BASE_ADDR 0xd8000000
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#define MX27_X_MEMC_SIZE SZ_1M
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#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
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#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
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#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
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#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
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#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
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2008-07-05 08:02:59 +00:00
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2010-01-07 10:27:17 +00:00
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#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
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#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
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#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
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#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
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2009-11-10 14:26:21 +00:00
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#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
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2009-11-10 09:18:08 +00:00
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/* IRAM */
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2009-11-10 14:26:21 +00:00
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#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
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2009-11-10 09:18:08 +00:00
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2010-10-25 13:44:25 +00:00
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#define MX27_IO_P2V(x) IMX_IO_P2V(x)
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2010-10-25 09:40:30 +00:00
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#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
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2009-12-16 16:30:27 +00:00
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2009-01-26 15:34:53 +00:00
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/* fixed interrupt numbers */
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2012-06-14 03:16:14 +00:00
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#include <asm/irq.h>
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#define MX27_INT_I2C2 (NR_IRQS_LEGACY + 1)
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#define MX27_INT_GPT6 (NR_IRQS_LEGACY + 2)
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#define MX27_INT_GPT5 (NR_IRQS_LEGACY + 3)
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#define MX27_INT_GPT4 (NR_IRQS_LEGACY + 4)
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#define MX27_INT_RTIC (NR_IRQS_LEGACY + 5)
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#define MX27_INT_CSPI3 (NR_IRQS_LEGACY + 6)
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2013-06-23 13:40:35 +00:00
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#define MX27_INT_MSHC (NR_IRQS_LEGACY + 7)
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2012-06-14 03:16:14 +00:00
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#define MX27_INT_GPIO (NR_IRQS_LEGACY + 8)
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#define MX27_INT_SDHC3 (NR_IRQS_LEGACY + 9)
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#define MX27_INT_SDHC2 (NR_IRQS_LEGACY + 10)
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#define MX27_INT_SDHC1 (NR_IRQS_LEGACY + 11)
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#define MX27_INT_I2C1 (NR_IRQS_LEGACY + 12)
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#define MX27_INT_SSI2 (NR_IRQS_LEGACY + 13)
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#define MX27_INT_SSI1 (NR_IRQS_LEGACY + 14)
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#define MX27_INT_CSPI2 (NR_IRQS_LEGACY + 15)
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#define MX27_INT_CSPI1 (NR_IRQS_LEGACY + 16)
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#define MX27_INT_UART4 (NR_IRQS_LEGACY + 17)
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#define MX27_INT_UART3 (NR_IRQS_LEGACY + 18)
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#define MX27_INT_UART2 (NR_IRQS_LEGACY + 19)
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#define MX27_INT_UART1 (NR_IRQS_LEGACY + 20)
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#define MX27_INT_KPP (NR_IRQS_LEGACY + 21)
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#define MX27_INT_RTC (NR_IRQS_LEGACY + 22)
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#define MX27_INT_PWM (NR_IRQS_LEGACY + 23)
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#define MX27_INT_GPT3 (NR_IRQS_LEGACY + 24)
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#define MX27_INT_GPT2 (NR_IRQS_LEGACY + 25)
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#define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26)
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#define MX27_INT_WDOG (NR_IRQS_LEGACY + 27)
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#define MX27_INT_PCMCIA (NR_IRQS_LEGACY + 28)
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#define MX27_INT_NFC (NR_IRQS_LEGACY + 29)
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#define MX27_INT_ATA (NR_IRQS_LEGACY + 30)
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#define MX27_INT_CSI (NR_IRQS_LEGACY + 31)
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#define MX27_INT_DMACH0 (NR_IRQS_LEGACY + 32)
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#define MX27_INT_DMACH1 (NR_IRQS_LEGACY + 33)
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#define MX27_INT_DMACH2 (NR_IRQS_LEGACY + 34)
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#define MX27_INT_DMACH3 (NR_IRQS_LEGACY + 35)
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#define MX27_INT_DMACH4 (NR_IRQS_LEGACY + 36)
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#define MX27_INT_DMACH5 (NR_IRQS_LEGACY + 37)
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#define MX27_INT_DMACH6 (NR_IRQS_LEGACY + 38)
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#define MX27_INT_DMACH7 (NR_IRQS_LEGACY + 39)
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#define MX27_INT_DMACH8 (NR_IRQS_LEGACY + 40)
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#define MX27_INT_DMACH9 (NR_IRQS_LEGACY + 41)
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#define MX27_INT_DMACH10 (NR_IRQS_LEGACY + 42)
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#define MX27_INT_DMACH11 (NR_IRQS_LEGACY + 43)
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#define MX27_INT_DMACH12 (NR_IRQS_LEGACY + 44)
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#define MX27_INT_DMACH13 (NR_IRQS_LEGACY + 45)
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#define MX27_INT_DMACH14 (NR_IRQS_LEGACY + 46)
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#define MX27_INT_DMACH15 (NR_IRQS_LEGACY + 47)
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#define MX27_INT_UART6 (NR_IRQS_LEGACY + 48)
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#define MX27_INT_UART5 (NR_IRQS_LEGACY + 49)
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#define MX27_INT_FEC (NR_IRQS_LEGACY + 50)
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#define MX27_INT_EMMAPRP (NR_IRQS_LEGACY + 51)
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#define MX27_INT_EMMAPP (NR_IRQS_LEGACY + 52)
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#define MX27_INT_VPU (NR_IRQS_LEGACY + 53)
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#define MX27_INT_USB_HS1 (NR_IRQS_LEGACY + 54)
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#define MX27_INT_USB_HS2 (NR_IRQS_LEGACY + 55)
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#define MX27_INT_USB_OTG (NR_IRQS_LEGACY + 56)
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#define MX27_INT_SCC_SMN (NR_IRQS_LEGACY + 57)
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#define MX27_INT_SCC_SCM (NR_IRQS_LEGACY + 58)
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#define MX27_INT_SAHARA (NR_IRQS_LEGACY + 59)
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#define MX27_INT_SLCDC (NR_IRQS_LEGACY + 60)
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#define MX27_INT_LCDC (NR_IRQS_LEGACY + 61)
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#define MX27_INT_IIM (NR_IRQS_LEGACY + 62)
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#define MX27_INT_CCM (NR_IRQS_LEGACY + 63)
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2008-07-05 08:02:59 +00:00
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/* fixed DMA request numbers */
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2009-11-13 20:31:31 +00:00
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#define MX27_DMA_REQ_CSPI3_RX 1
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#define MX27_DMA_REQ_CSPI3_TX 2
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#define MX27_DMA_REQ_EXT 3
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2009-11-10 14:26:21 +00:00
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#define MX27_DMA_REQ_MSHC 4
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2009-11-13 20:31:31 +00:00
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#define MX27_DMA_REQ_SDHC2 6
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#define MX27_DMA_REQ_SDHC1 7
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#define MX27_DMA_REQ_SSI2_RX0 8
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#define MX27_DMA_REQ_SSI2_TX0 9
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#define MX27_DMA_REQ_SSI2_RX1 10
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#define MX27_DMA_REQ_SSI2_TX1 11
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#define MX27_DMA_REQ_SSI1_RX0 12
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#define MX27_DMA_REQ_SSI1_TX0 13
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#define MX27_DMA_REQ_SSI1_RX1 14
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#define MX27_DMA_REQ_SSI1_TX1 15
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#define MX27_DMA_REQ_CSPI2_RX 16
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#define MX27_DMA_REQ_CSPI2_TX 17
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#define MX27_DMA_REQ_CSPI1_RX 18
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#define MX27_DMA_REQ_CSPI1_TX 19
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#define MX27_DMA_REQ_UART4_RX 20
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#define MX27_DMA_REQ_UART4_TX 21
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#define MX27_DMA_REQ_UART3_RX 22
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#define MX27_DMA_REQ_UART3_TX 23
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#define MX27_DMA_REQ_UART2_RX 24
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#define MX27_DMA_REQ_UART2_TX 25
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#define MX27_DMA_REQ_UART1_RX 26
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#define MX27_DMA_REQ_UART1_TX 27
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2009-11-10 14:26:21 +00:00
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#define MX27_DMA_REQ_ATA_TX 28
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#define MX27_DMA_REQ_ATA_RCV 29
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2009-11-13 20:31:31 +00:00
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#define MX27_DMA_REQ_CSI_STAT 30
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#define MX27_DMA_REQ_CSI_RX 31
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2009-11-10 14:26:21 +00:00
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#define MX27_DMA_REQ_UART5_TX 32
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#define MX27_DMA_REQ_UART5_RX 33
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#define MX27_DMA_REQ_UART6_TX 34
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#define MX27_DMA_REQ_UART6_RX 35
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#define MX27_DMA_REQ_SDHC3 36
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#define MX27_DMA_REQ_NFC 37
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2008-07-05 08:02:59 +00:00
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2010-01-08 15:02:30 +00:00
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#endif /* ifndef __MACH_MX27_H__ */
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