2008-07-05 08:02:59 +00:00
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/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __ASM_ARCH_MXC_MX27_H__
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#define __ASM_ARCH_MXC_MX27_H__
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#ifndef __ASM_ARCH_MXC_HARDWARE_H__
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#error "Do not include directly."
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#endif
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/* IRAM */
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#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */
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/* Register offests */
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#define AIPI_BASE_ADDR 0x10000000
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#define AIPI_BASE_ADDR_VIRT 0xF4000000
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#define AIPI_SIZE SZ_1M
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#define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000)
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#define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000)
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#define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000)
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#define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000)
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#define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000)
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#define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000)
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#define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000)
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#define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000)
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#define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000)
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#define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000)
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#define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000)
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#define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000)
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#define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000)
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#define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000)
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#define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000)
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#define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000)
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#define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000)
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#define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000)
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#define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000)
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#define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000)
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#define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000)
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#define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000)
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#define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000)
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#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000)
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#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000)
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#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000)
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#define UART5_BASE_ADDR (AIPI_BASE_ADDR + 0x1B000)
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#define UART6_BASE_ADDR (AIPI_BASE_ADDR + 0x1C000)
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#define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000)
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#define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000)
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#define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000)
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#define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000)
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#define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000)
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#define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000)
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#define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000)
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/* for mx27*/
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#define OTG_BASE_ADDR USBOTG_BASE_ADDR
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#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000)
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2008-10-07 08:31:07 +00:00
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#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000)
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#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400)
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2008-07-05 08:02:59 +00:00
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#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000)
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#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800)
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#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000)
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#define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000)
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#define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000)
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#define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000)
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#define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000)
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#define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000)
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#define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000)
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#define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000)
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/* ROMP and AVIC */
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#define ROMP_BASE_ADDR 0x10041000
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#define AVIC_BASE_ADDR 0x10040000
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#define SAHB1_BASE_ADDR 0x80000000
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#define SAHB1_BASE_ADDR_VIRT 0xF4100000
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#define SAHB1_SIZE SZ_1M
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#define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000)
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#define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000)
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/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
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#define X_MEMC_BASE_ADDR 0xD8000000
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#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
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#define X_MEMC_SIZE SZ_1M
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#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR)
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#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
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#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
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#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
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#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
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/* Memory regions and CS */
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#define SDRAM_BASE_ADDR 0xA0000000
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#define CSD1_BASE_ADDR 0xB0000000
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#define CS0_BASE_ADDR 0xC0000000
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#define CS1_BASE_ADDR 0xC8000000
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#define CS2_BASE_ADDR 0xD0000000
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#define CS3_BASE_ADDR 0xD2000000
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#define CS4_BASE_ADDR 0xD4000000
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#define CS5_BASE_ADDR 0xD6000000
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#define PCMCIA_MEM_BASE_ADDR 0xDC000000
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/*
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* This macro defines the physical to virtual address mapping for all the
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* peripheral modules. It is used by passing in the physical address as x
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* and returning the virtual address. If the physical address is not mapped,
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* it returns 0xDEADBEEF
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*/
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#define IO_ADDRESS(x) \
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2009-01-26 15:34:51 +00:00
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(void __force __iomem *) \
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2008-07-05 08:02:59 +00:00
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(((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
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AIPI_IO_ADDRESS(x) : \
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((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
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SAHB1_IO_ADDRESS(x) : \
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((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
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X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
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/* define the address mapping macros: in physical address order */
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#define AIPI_IO_ADDRESS(x) \
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(((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
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#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
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#define SAHB1_IO_ADDRESS(x) \
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(((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
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#define CS4_IO_ADDRESS(x) \
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(((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
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#define X_MEMC_IO_ADDRESS(x) \
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(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
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#define PCMCIA_IO_ADDRESS(x) \
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(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
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/* fixed interrput numbers */
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#define MXC_INT_CCM 63
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#define MXC_INT_IIM 62
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#define MXC_INT_LCDC 61
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#define MXC_INT_SLCDC 60
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#define MXC_INT_SAHARA 59
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#define MXC_INT_SCC_SCM 58
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#define MXC_INT_SCC_SMN 57
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#define MXC_INT_USB3 56
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#define MXC_INT_USB2 55
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#define MXC_INT_USB1 54
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#define MXC_INT_VPU 53
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#define MXC_INT_EMMAPP 52
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#define MXC_INT_EMMAPRP 51
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#define MXC_INT_FEC 50
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#define MXC_INT_UART5 49
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#define MXC_INT_UART6 48
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#define MXC_INT_DMACH15 47
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#define MXC_INT_DMACH14 46
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#define MXC_INT_DMACH13 45
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#define MXC_INT_DMACH12 44
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#define MXC_INT_DMACH11 43
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#define MXC_INT_DMACH10 42
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#define MXC_INT_DMACH9 41
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#define MXC_INT_DMACH8 40
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#define MXC_INT_DMACH7 39
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#define MXC_INT_DMACH6 38
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#define MXC_INT_DMACH5 37
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#define MXC_INT_DMACH4 36
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#define MXC_INT_DMACH3 35
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#define MXC_INT_DMACH2 34
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#define MXC_INT_DMACH1 33
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#define MXC_INT_DMACH0 32
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#define MXC_INT_CSI 31
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#define MXC_INT_ATA 30
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#define MXC_INT_NANDFC 29
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#define MXC_INT_PCMCIA 28
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#define MXC_INT_WDOG 27
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#define MXC_INT_GPT1 26
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#define MXC_INT_GPT2 25
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#define MXC_INT_GPT3 24
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#define MXC_INT_GPT INT_GPT1
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#define MXC_INT_PWM 23
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#define MXC_INT_RTC 22
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#define MXC_INT_KPP 21
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#define MXC_INT_UART1 20
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#define MXC_INT_UART2 19
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#define MXC_INT_UART3 18
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#define MXC_INT_UART4 17
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#define MXC_INT_CSPI1 16
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#define MXC_INT_CSPI2 15
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#define MXC_INT_SSI1 14
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#define MXC_INT_SSI2 13
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#define MXC_INT_I2C 12
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#define MXC_INT_SDHC1 11
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#define MXC_INT_SDHC2 10
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#define MXC_INT_SDHC3 9
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#define MXC_INT_GPIO 8
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#define MXC_INT_SDHC 7
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#define MXC_INT_CSPI3 6
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#define MXC_INT_RTIC 5
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#define MXC_INT_GPT4 4
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#define MXC_INT_GPT5 3
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#define MXC_INT_GPT6 2
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#define MXC_INT_I2C2 1
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/* fixed DMA request numbers */
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#define DMA_REQ_NFC 37
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#define DMA_REQ_SDHC3 36
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#define DMA_REQ_UART6_RX 35
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#define DMA_REQ_UART6_TX 34
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#define DMA_REQ_UART5_RX 33
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#define DMA_REQ_UART5_TX 32
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#define DMA_REQ_CSI_RX 31
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#define DMA_REQ_CSI_STAT 30
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#define DMA_REQ_ATA_RCV 29
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#define DMA_REQ_ATA_TX 28
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#define DMA_REQ_UART1_TX 27
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#define DMA_REQ_UART1_RX 26
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#define DMA_REQ_UART2_TX 25
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#define DMA_REQ_UART2_RX 24
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#define DMA_REQ_UART3_TX 23
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#define DMA_REQ_UART3_RX 22
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#define DMA_REQ_UART4_TX 21
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#define DMA_REQ_UART4_RX 20
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#define DMA_REQ_CSPI1_TX 19
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#define DMA_REQ_CSPI1_RX 18
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#define DMA_REQ_CSPI2_TX 17
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#define DMA_REQ_CSPI2_RX 16
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#define DMA_REQ_SSI1_TX1 15
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#define DMA_REQ_SSI1_RX1 14
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#define DMA_REQ_SSI1_TX0 13
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#define DMA_REQ_SSI1_RX0 12
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#define DMA_REQ_SSI2_TX1 11
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#define DMA_REQ_SSI2_RX1 10
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#define DMA_REQ_SSI2_TX0 9
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#define DMA_REQ_SSI2_RX0 8
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#define DMA_REQ_SDHC1 7
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#define DMA_REQ_SDHC2 6
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#define DMA_REQ_MSHC 4
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#define DMA_REQ_EXT 3
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#define DMA_REQ_CSPI3_TX 2
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#define DMA_REQ_CSPI3_RX 1
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/* silicon revisions specific to i.MX27 */
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#define CHIP_REV_1_0 0x00
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#define CHIP_REV_2_0 0x01
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#ifndef __ASSEMBLY__
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extern int mx27_revision(void);
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#endif
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/* gpio and gpio based interrupt handling */
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#define GPIO_DR 0x1C
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#define GPIO_GDIR 0x00
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#define GPIO_PSR 0x24
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#define GPIO_ICR1 0x28
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#define GPIO_ICR2 0x2C
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#define GPIO_IMR 0x30
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#define GPIO_ISR 0x34
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#define GPIO_INT_LOW_LEV 0x3
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#define GPIO_INT_HIGH_LEV 0x2
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#define GPIO_INT_RISE_EDGE 0x0
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#define GPIO_INT_FALL_EDGE 0x1
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#define GPIO_INT_NONE 0x4
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/* Mandatory defines used globally */
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/* this is an i.MX27 CPU */
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#define cpu_is_mx27() (1)
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/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
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#define ARCH_NR_GPIOS (192 + 16)
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#endif /* __ASM_ARCH_MXC_MX27_H__ */
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