2005-04-16 22:20:36 +00:00
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/bitops.h>
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#include <linux/smp.h>
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2009-02-26 19:16:58 +00:00
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#include <linux/sched.h>
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2005-04-16 22:20:36 +00:00
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#include <linux/thread_info.h>
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2005-11-14 00:07:23 +00:00
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#include <linux/module.h>
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2009-07-03 23:35:45 +00:00
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#include <linux/uaccess.h>
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2005-04-16 22:20:36 +00:00
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#include <asm/processor.h>
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2007-10-17 16:04:33 +00:00
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#include <asm/pgtable.h>
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2005-04-16 22:20:36 +00:00
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#include <asm/msr.h>
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2008-02-04 15:48:04 +00:00
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#include <asm/bugs.h>
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2009-03-08 07:46:26 +00:00
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#include <asm/cpu.h>
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2005-04-16 22:20:36 +00:00
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2008-09-09 23:40:35 +00:00
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#ifdef CONFIG_X86_64
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2009-07-03 23:35:45 +00:00
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#include <linux/topology.h>
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2008-09-09 23:40:35 +00:00
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#include <asm/numa_64.h>
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#endif
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2005-04-16 22:20:36 +00:00
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#include "cpu.h"
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#ifdef CONFIG_X86_LOCAL_APIC
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#include <asm/mpspec.h>
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#include <asm/apic.h>
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#endif
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x86: use ELF section to list CPU vendor specific code
Replace the hardcoded list of initialization functions for each CPU
vendor by a list in an ELF section, which is read at initialization in
arch/x86/kernel/cpu/cpu.c to fill the cpu_devs[] array. The ELF
section, named .x86cpuvendor.init, is reclaimed after boot, and
contains entries of type "struct cpu_vendor_dev" which associates a
vendor number with a pointer to a "struct cpu_dev" structure.
This first modification allows to remove all the VENDOR_init_cpu()
functions.
This patch also removes the hardcoded calls to early_init_amd() and
early_init_intel(). Instead, we add a "c_early_init" member to the
cpu_dev structure, which is then called if not NULL by the generic CPU
initialization code. Unfortunately, in early_cpu_detect(), this_cpu is
not yet set, so we have to use the cpu_devs[] array directly.
This patch is part of the Linux Tiny project, and is needed for
further patch that will allow to disable compilation of unused CPU
support code.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-02-15 11:00:23 +00:00
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static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
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2005-04-16 22:20:36 +00:00
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{
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2011-05-17 22:29:11 +00:00
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u64 misc_enable;
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2009-01-26 03:30:41 +00:00
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/* Unmask CPUID levels if masked: */
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2009-01-26 17:40:58 +00:00
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if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
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2009-01-26 03:30:41 +00:00
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rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
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if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
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misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
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wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
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c->cpuid_level = cpuid_eax(0);
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2010-09-28 22:35:01 +00:00
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get_cpu_cap(c);
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2009-01-26 03:30:41 +00:00
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}
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2009-01-21 23:04:32 +00:00
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}
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2008-01-30 12:32:40 +00:00
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if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
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(c->x86 == 0x6 && c->x86_model >= 0x0e))
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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2008-09-09 23:40:35 +00:00
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2011-10-13 00:46:33 +00:00
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if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
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unsigned lower_word;
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wrmsr(MSR_IA32_UCODE_REV, 0, 0);
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/* Required by the SDM */
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sync_core();
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rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
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}
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2010-04-13 21:40:54 +00:00
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/*
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* Atom erratum AAE44/AAF40/AAG38/AAH41:
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*
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* A race condition between speculative fetches and invalidating
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* a large page. This is worked around in microcode, but we
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* need the microcode to have already been loaded... so if it is
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* not, recommend a BIOS update and disable large pages.
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*/
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2011-10-13 00:46:34 +00:00
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if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
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c->microcode < 0x20e) {
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printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
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clear_cpu_cap(c, X86_FEATURE_PSE);
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2010-04-13 21:40:54 +00:00
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}
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2008-09-09 23:40:35 +00:00
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#ifdef CONFIG_X86_64
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set_cpu_cap(c, X86_FEATURE_SYSENTER32);
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#else
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/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
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if (c->x86 == 15 && c->x86_cache_alignment == 64)
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c->x86_cache_alignment = 128;
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#endif
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2008-11-18 00:11:37 +00:00
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2009-03-12 12:37:34 +00:00
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/* CPUID workaround for 0F33/0F34 CPU */
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if (c->x86 == 0xF && c->x86_model == 0x3
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&& (c->x86_mask == 0x3 || c->x86_mask == 0x4))
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c->x86_phys_bits = 36;
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2008-11-18 00:11:37 +00:00
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/*
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* c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
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2009-02-26 19:16:58 +00:00
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* with P/T states and does not stop in deep C-states.
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*
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* It is also reliable across cores and sockets. (but not across
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* cabinets - we turn it off in that case explicitly.)
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2008-11-18 00:11:37 +00:00
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*/
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if (c->x86_power & (1 << 8)) {
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
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2010-03-01 17:48:15 +00:00
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if (!check_tsc_unstable())
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sched_clock_stable = 1;
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2008-11-18 00:11:37 +00:00
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}
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2009-01-23 00:17:05 +00:00
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/*
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* There is a known erratum on Pentium III and Core Solo
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* and Core Duo CPUs.
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* " Page with PAT set to WC while associated MTRR is UC
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* may consolidate to UC "
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* Because of this erratum, it is better to stick with
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* setting WC in MTRR rather than using PAT on these CPUs.
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*
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* Enable PAT WC only on P4, Core 2 or later CPUs.
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*/
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if (c->x86 == 6 && c->x86_model < 15)
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clear_cpu_cap(c, X86_FEATURE_PAT);
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2008-04-03 22:53:23 +00:00
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#ifdef CONFIG_KMEMCHECK
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/*
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* P4s have a "fast strings" feature which causes single-
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* stepping REP instructions to only generate a #DB on
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* cache-line boundaries.
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*
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* Ingo Molnar reported a Pentium D (model 6) and a Xeon
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* (model 2) with the same problem.
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*/
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if (c->x86 == 15) {
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rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
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if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
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printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
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misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
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wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
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}
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}
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#endif
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2011-05-17 22:29:11 +00:00
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/*
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* If fast string is not enabled in IA32_MISC_ENABLE for any reason,
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* clear the fast string and enhanced fast string CPU capabilities.
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*/
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if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
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rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
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if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
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printk(KERN_INFO "Disabled fast string operations\n");
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setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
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setup_clear_cpu_cap(X86_FEATURE_ERMS);
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}
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}
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2005-04-16 22:20:36 +00:00
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}
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2008-09-09 23:40:35 +00:00
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#ifdef CONFIG_X86_32
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2005-04-16 22:20:36 +00:00
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/*
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* Early probe support logic for ppro memory erratum #50
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*
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* This is called before we do cpu ident work
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*/
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2008-02-22 22:09:42 +00:00
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2006-03-23 10:59:33 +00:00
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int __cpuinit ppro_with_ram_bug(void)
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2005-04-16 22:20:36 +00:00
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{
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/* Uses data from early_cpu_detect now */
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if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
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boot_cpu_data.x86 == 6 &&
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boot_cpu_data.x86_model == 1 &&
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boot_cpu_data.x86_mask < 8) {
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printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
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return 1;
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}
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return 0;
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}
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2008-02-22 22:09:42 +00:00
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2008-09-09 23:40:38 +00:00
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#ifdef CONFIG_X86_F00F_BUG
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static void __cpuinit trap_init_f00f_bug(void)
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{
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__set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
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2005-04-16 22:20:36 +00:00
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2008-09-09 23:40:38 +00:00
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/*
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* Update the IDT descriptor and reload the IDT so that
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* it uses the read-only mapped virtual address.
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*/
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idt_descr.address = fix_to_virt(FIX_F00F_IDT);
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load_idt(&idt_descr);
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}
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#endif
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2009-03-08 07:46:26 +00:00
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static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
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{
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/* calling is from identify_secondary_cpu() ? */
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2010-07-21 17:03:58 +00:00
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if (!c->cpu_index)
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2009-03-08 07:46:26 +00:00
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return;
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/*
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* Mask B, Pentium, but not Pentium MMX
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*/
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if (c->x86 == 5 &&
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c->x86_mask >= 1 && c->x86_mask <= 4 &&
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c->x86_model <= 3) {
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/*
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* Remember we have B step Pentia with bugs
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*/
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WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
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"with B stepping processors.\n");
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}
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}
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2008-09-09 23:40:38 +00:00
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static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
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2005-04-16 22:20:36 +00:00
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{
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unsigned long lo, hi;
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2008-09-09 23:40:38 +00:00
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#ifdef CONFIG_X86_F00F_BUG
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/*
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* All current models of Pentium and Pentium with MMX technology CPUs
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2009-07-03 23:35:45 +00:00
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* have the F0 0F bug, which lets nonprivileged users lock up the
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* system.
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2008-09-09 23:40:38 +00:00
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* Note that the workaround only should be initialized once...
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*/
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c->f00f_bug = 0;
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if (!paravirt_enabled() && c->x86 == 5) {
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static int f00f_workaround_enabled;
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c->f00f_bug = 1;
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if (!f00f_workaround_enabled) {
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trap_init_f00f_bug();
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printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
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f00f_workaround_enabled = 1;
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}
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}
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#endif
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/*
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* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
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* model 3 mask 3
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*/
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if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
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clear_cpu_cap(c, X86_FEATURE_SEP);
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/*
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* P4 Xeon errata 037 workaround.
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* Hardware prefetcher may cause stale data to be loaded into the cache.
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*/
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2005-04-16 22:20:36 +00:00
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if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
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2008-02-22 22:09:42 +00:00
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rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
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2009-02-20 10:56:38 +00:00
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if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
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2005-04-16 22:20:36 +00:00
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printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
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printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
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2009-02-20 10:56:38 +00:00
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lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
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2009-07-03 23:35:45 +00:00
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wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
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2005-04-16 22:20:36 +00:00
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}
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}
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2008-09-09 23:40:38 +00:00
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/*
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* See if we have a good local APIC by checking for buggy Pentia,
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* i.e. all B steppings and the C2 stepping of P54C when using their
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* integrated APIC (see 11AP erratum in "Pentium Processor
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* Specification Update").
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*/
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if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
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(c->x86_mask < 0x6 || c->x86_mask == 0xb))
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set_cpu_cap(c, X86_FEATURE_11AP);
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2008-09-09 23:40:35 +00:00
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2008-09-09 23:40:38 +00:00
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#ifdef CONFIG_X86_INTEL_USERCOPY
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2008-09-09 23:40:35 +00:00
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/*
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2008-09-09 23:40:38 +00:00
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* Set up the preferred alignment for movsl bulk memory moves
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2008-09-09 23:40:35 +00:00
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*/
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2008-09-09 23:40:38 +00:00
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switch (c->x86) {
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case 4: /* 486: untested */
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break;
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case 5: /* Old Pentia: untested */
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break;
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case 6: /* PII/PIII only like movsl with 8-byte alignment */
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movsl_mask.mask = 7;
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break;
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case 15: /* P4 is OK down to 8-byte alignment */
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movsl_mask.mask = 7;
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break;
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}
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2008-09-09 23:40:35 +00:00
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#endif
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2008-09-09 23:40:38 +00:00
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#ifdef CONFIG_X86_NUMAQ
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numaq_tsc_disable();
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#endif
|
2009-03-08 07:46:26 +00:00
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intel_smp_check(c);
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2008-09-09 23:40:38 +00:00
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}
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#else
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static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
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{
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}
|
2008-09-09 23:40:35 +00:00
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|
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#endif
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|
|
2009-05-15 20:05:16 +00:00
|
|
|
static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
|
2008-09-09 23:40:35 +00:00
|
|
|
{
|
2011-01-23 13:37:40 +00:00
|
|
|
#ifdef CONFIG_NUMA
|
2008-09-09 23:40:35 +00:00
|
|
|
unsigned node;
|
|
|
|
int cpu = smp_processor_id();
|
|
|
|
|
|
|
|
/* Don't do the funky fallback heuristics the AMD version employs
|
|
|
|
for now. */
|
2011-01-23 13:37:39 +00:00
|
|
|
node = numa_cpu_node(cpu);
|
2010-09-30 12:04:10 +00:00
|
|
|
if (node == NUMA_NO_NODE || !node_online(node)) {
|
2009-11-21 08:23:37 +00:00
|
|
|
/* reuse the value from init_cpu_to_node() */
|
|
|
|
node = cpu_to_node(cpu);
|
|
|
|
}
|
2008-09-09 23:40:35 +00:00
|
|
|
numa_set_node(cpu, node);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2005-04-16 22:25:15 +00:00
|
|
|
/*
|
|
|
|
* find out the number of processor cores on the die
|
|
|
|
*/
|
2008-09-08 00:58:58 +00:00
|
|
|
static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
|
2005-04-16 22:25:15 +00:00
|
|
|
{
|
2005-09-03 22:56:42 +00:00
|
|
|
unsigned int eax, ebx, ecx, edx;
|
2005-04-16 22:25:15 +00:00
|
|
|
|
|
|
|
if (c->cpuid_level < 4)
|
|
|
|
return 1;
|
|
|
|
|
2005-09-03 22:56:42 +00:00
|
|
|
/* Intel has a non-standard dependency on %ecx for this CPUID level. */
|
|
|
|
cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
|
2005-04-16 22:25:15 +00:00
|
|
|
if (eax & 0x1f)
|
2009-07-03 23:35:45 +00:00
|
|
|
return (eax >> 26) + 1;
|
2005-04-16 22:25:15 +00:00
|
|
|
else
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2008-09-10 10:53:34 +00:00
|
|
|
static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
|
|
|
|
{
|
|
|
|
/* Intel VMX MSR indicated features */
|
|
|
|
#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
|
|
|
|
#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
|
|
|
|
#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
|
|
|
|
#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
|
|
|
|
#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
|
|
|
|
#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
|
|
|
|
|
|
|
|
u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
|
|
|
|
|
|
|
|
clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
|
|
|
|
clear_cpu_cap(c, X86_FEATURE_VNMI);
|
|
|
|
clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
|
|
|
|
clear_cpu_cap(c, X86_FEATURE_EPT);
|
|
|
|
clear_cpu_cap(c, X86_FEATURE_VPID);
|
|
|
|
|
|
|
|
rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
|
|
|
|
msr_ctl = vmx_msr_high | vmx_msr_low;
|
|
|
|
if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
|
|
|
|
set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
|
|
|
|
if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
|
|
|
|
set_cpu_cap(c, X86_FEATURE_VNMI);
|
|
|
|
if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
|
|
|
|
rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
|
|
|
|
vmx_msr_low, vmx_msr_high);
|
|
|
|
msr_ctl2 = vmx_msr_high | vmx_msr_low;
|
|
|
|
if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
|
|
|
|
(msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
|
|
|
|
set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
|
|
|
|
if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
|
|
|
|
set_cpu_cap(c, X86_FEATURE_EPT);
|
|
|
|
if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
|
|
|
|
set_cpu_cap(c, X86_FEATURE_VPID);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-03-23 10:59:33 +00:00
|
|
|
static void __cpuinit init_intel(struct cpuinfo_x86 *c)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
unsigned int l2 = 0;
|
|
|
|
|
2008-01-30 12:32:40 +00:00
|
|
|
early_init_intel(c);
|
|
|
|
|
2008-09-09 23:40:38 +00:00
|
|
|
intel_workarounds(c);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2008-12-19 02:09:21 +00:00
|
|
|
/*
|
|
|
|
* Detect the extended topology information if available. This
|
|
|
|
* will reinitialise the initial_apicid which will be used
|
|
|
|
* in init_intel_cacheinfo()
|
|
|
|
*/
|
|
|
|
detect_extended_topology(c);
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
l2 = init_intel_cacheinfo(c);
|
2008-02-22 22:09:42 +00:00
|
|
|
if (c->cpuid_level > 9) {
|
2006-06-26 11:59:59 +00:00
|
|
|
unsigned eax = cpuid_eax(10);
|
|
|
|
/* Check for version and the number of counters */
|
|
|
|
if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
|
2008-02-26 07:52:33 +00:00
|
|
|
set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
|
2006-06-26 11:59:59 +00:00
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2008-09-09 23:40:38 +00:00
|
|
|
if (cpu_has_xmm2)
|
|
|
|
set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
|
|
|
|
if (cpu_has_ds) {
|
|
|
|
unsigned int l1;
|
|
|
|
rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
|
|
|
|
if (!(l1 & (1<<11)))
|
|
|
|
set_cpu_cap(c, X86_FEATURE_BTS);
|
|
|
|
if (!(l1 & (1<<12)))
|
|
|
|
set_cpu_cap(c, X86_FEATURE_PEBS);
|
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2009-02-07 00:52:05 +00:00
|
|
|
if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
|
|
|
|
set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
|
|
|
|
|
2008-09-09 23:40:38 +00:00
|
|
|
#ifdef CONFIG_X86_64
|
|
|
|
if (c->x86 == 15)
|
|
|
|
c->x86_cache_alignment = c->x86_clflush_size * 2;
|
|
|
|
if (c->x86 == 6)
|
|
|
|
set_cpu_cap(c, X86_FEATURE_REP_GOOD);
|
|
|
|
#else
|
2008-02-22 22:09:42 +00:00
|
|
|
/*
|
|
|
|
* Names for the Pentium II/Celeron processors
|
|
|
|
* detectable only by also checking the cache size.
|
|
|
|
* Dixon is NOT a Celeron.
|
|
|
|
*/
|
2005-04-16 22:20:36 +00:00
|
|
|
if (c->x86 == 6) {
|
2008-09-09 23:40:38 +00:00
|
|
|
char *p = NULL;
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
switch (c->x86_model) {
|
|
|
|
case 5:
|
2011-05-16 19:38:08 +00:00
|
|
|
if (l2 == 0)
|
|
|
|
p = "Celeron (Covington)";
|
|
|
|
else if (l2 == 256)
|
|
|
|
p = "Mobile Pentium II (Dixon)";
|
2005-04-16 22:20:36 +00:00
|
|
|
break;
|
2008-02-22 22:09:42 +00:00
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
case 6:
|
|
|
|
if (l2 == 128)
|
|
|
|
p = "Celeron (Mendocino)";
|
|
|
|
else if (c->x86_mask == 0 || c->x86_mask == 5)
|
|
|
|
p = "Celeron-A";
|
|
|
|
break;
|
2008-02-22 22:09:42 +00:00
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
case 8:
|
|
|
|
if (l2 == 128)
|
|
|
|
p = "Celeron (Coppermine)";
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2008-09-09 23:40:38 +00:00
|
|
|
if (p)
|
|
|
|
strcpy(c->x86_model_id, p);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
2008-09-09 23:40:35 +00:00
|
|
|
if (c->x86 == 15)
|
|
|
|
set_cpu_cap(c, X86_FEATURE_P4);
|
|
|
|
if (c->x86 == 6)
|
|
|
|
set_cpu_cap(c, X86_FEATURE_P3);
|
2008-11-09 13:29:21 +00:00
|
|
|
#endif
|
2008-09-09 23:40:35 +00:00
|
|
|
|
|
|
|
if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
|
|
|
|
/*
|
|
|
|
* let's use the legacy cpuid vector 0x1 and 0x4 for topology
|
|
|
|
* detection.
|
|
|
|
*/
|
|
|
|
c->x86_max_cores = intel_num_cpu_cores(c);
|
|
|
|
#ifdef CONFIG_X86_32
|
|
|
|
detect_ht(c);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Work around errata */
|
2009-05-15 20:05:16 +00:00
|
|
|
srat_detect_node(c);
|
2008-09-10 10:53:34 +00:00
|
|
|
|
|
|
|
if (cpu_has(c, X86_FEATURE_VMX))
|
|
|
|
detect_vmx_virtcap(c);
|
x86, intel, power: Initialize MSR_IA32_ENERGY_PERF_BIAS
Since 2.6.36 (23016bf0d25), Linux prints the existence of "epb" in /proc/cpuinfo,
Since 2.6.38 (d5532ee7b40), the x86_energy_perf_policy(8) utility has
been available in-tree to update MSR_IA32_ENERGY_PERF_BIAS.
However, the typical BIOS fails to initialize the MSR, presumably
because this is handled by high-volume shrink-wrap operating systems...
Linux distros, on the other hand, do not yet invoke x86_energy_perf_policy(8).
As a result, WSM-EP, SNB, and later hardware from Intel will run in its
default hardware power-on state (performance), which assumes that users
care for performance at all costs and not for energy efficiency.
While that is fine for performance benchmarks, the hardware's intended default
operating point is "normal" mode...
Initialize the MSR to the "normal" by default during kernel boot.
x86_energy_perf_policy(8) is available to change the default after boot,
should the user have a different preference.
Signed-off-by: Len Brown <len.brown@intel.com>
Link: http://lkml.kernel.org/r/alpine.LFD.2.02.1107140051020.18606@x980
Acked-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Cc: <stable@kernel.org>
2011-07-14 04:53:24 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
|
|
|
|
* x86_energy_perf_policy(8) is available to change it at run-time
|
|
|
|
*/
|
|
|
|
if (cpu_has(c, X86_FEATURE_EPB)) {
|
|
|
|
u64 epb;
|
|
|
|
|
|
|
|
rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
|
2011-07-15 21:37:15 +00:00
|
|
|
if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) {
|
|
|
|
printk_once(KERN_WARNING "ENERGY_PERF_BIAS:"
|
|
|
|
" Set to 'normal', was 'performance'\n"
|
|
|
|
"ENERGY_PERF_BIAS: View and update with"
|
|
|
|
" x86_energy_perf_policy(8)\n");
|
x86, intel, power: Initialize MSR_IA32_ENERGY_PERF_BIAS
Since 2.6.36 (23016bf0d25), Linux prints the existence of "epb" in /proc/cpuinfo,
Since 2.6.38 (d5532ee7b40), the x86_energy_perf_policy(8) utility has
been available in-tree to update MSR_IA32_ENERGY_PERF_BIAS.
However, the typical BIOS fails to initialize the MSR, presumably
because this is handled by high-volume shrink-wrap operating systems...
Linux distros, on the other hand, do not yet invoke x86_energy_perf_policy(8).
As a result, WSM-EP, SNB, and later hardware from Intel will run in its
default hardware power-on state (performance), which assumes that users
care for performance at all costs and not for energy efficiency.
While that is fine for performance benchmarks, the hardware's intended default
operating point is "normal" mode...
Initialize the MSR to the "normal" by default during kernel boot.
x86_energy_perf_policy(8) is available to change the default after boot,
should the user have a different preference.
Signed-off-by: Len Brown <len.brown@intel.com>
Link: http://lkml.kernel.org/r/alpine.LFD.2.02.1107140051020.18606@x980
Acked-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Cc: <stable@kernel.org>
2011-07-14 04:53:24 +00:00
|
|
|
epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
|
|
|
|
wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
|
|
|
|
}
|
|
|
|
}
|
2006-12-07 01:14:01 +00:00
|
|
|
}
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2008-09-09 23:40:35 +00:00
|
|
|
#ifdef CONFIG_X86_32
|
2008-02-22 22:09:42 +00:00
|
|
|
static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2008-02-22 22:09:42 +00:00
|
|
|
/*
|
|
|
|
* Intel PIII Tualatin. This comes in two flavours.
|
2005-04-16 22:20:36 +00:00
|
|
|
* One has 256kb of cache, the other 512. We have no way
|
|
|
|
* to determine which, so we use a boottime override
|
|
|
|
* for the 512kb model, and assume 256 otherwise.
|
|
|
|
*/
|
|
|
|
if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
|
|
|
|
size = 256;
|
|
|
|
return size;
|
|
|
|
}
|
2008-09-09 23:40:35 +00:00
|
|
|
#endif
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2009-03-12 12:08:49 +00:00
|
|
|
static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
|
2005-04-16 22:20:36 +00:00
|
|
|
.c_vendor = "Intel",
|
2008-02-22 22:09:42 +00:00
|
|
|
.c_ident = { "GenuineIntel" },
|
2008-09-09 23:40:35 +00:00
|
|
|
#ifdef CONFIG_X86_32
|
2005-04-16 22:20:36 +00:00
|
|
|
.c_models = {
|
2008-02-22 22:09:42 +00:00
|
|
|
{ .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
|
|
|
|
{
|
|
|
|
[0] = "486 DX-25/33",
|
|
|
|
[1] = "486 DX-50",
|
|
|
|
[2] = "486 SX",
|
|
|
|
[3] = "486 DX/2",
|
|
|
|
[4] = "486 SL",
|
|
|
|
[5] = "486 SX/2",
|
|
|
|
[7] = "486 DX/2-WB",
|
|
|
|
[8] = "486 DX/4",
|
2005-04-16 22:20:36 +00:00
|
|
|
[9] = "486 DX/4-WB"
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{ .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
|
2008-02-22 22:09:42 +00:00
|
|
|
{
|
|
|
|
[0] = "Pentium 60/66 A-step",
|
|
|
|
[1] = "Pentium 60/66",
|
2005-04-16 22:20:36 +00:00
|
|
|
[2] = "Pentium 75 - 200",
|
2008-02-22 22:09:42 +00:00
|
|
|
[3] = "OverDrive PODP5V83",
|
2005-04-16 22:20:36 +00:00
|
|
|
[4] = "Pentium MMX",
|
2008-02-22 22:09:42 +00:00
|
|
|
[7] = "Mobile Pentium 75 - 200",
|
2005-04-16 22:20:36 +00:00
|
|
|
[8] = "Mobile Pentium MMX"
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{ .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
|
2008-02-22 22:09:42 +00:00
|
|
|
{
|
2005-04-16 22:20:36 +00:00
|
|
|
[0] = "Pentium Pro A-step",
|
2008-02-22 22:09:42 +00:00
|
|
|
[1] = "Pentium Pro",
|
|
|
|
[3] = "Pentium II (Klamath)",
|
|
|
|
[4] = "Pentium II (Deschutes)",
|
|
|
|
[5] = "Pentium II (Deschutes)",
|
2005-04-16 22:20:36 +00:00
|
|
|
[6] = "Mobile Pentium II",
|
2008-02-22 22:09:42 +00:00
|
|
|
[7] = "Pentium III (Katmai)",
|
|
|
|
[8] = "Pentium III (Coppermine)",
|
2005-04-16 22:20:36 +00:00
|
|
|
[10] = "Pentium III (Cascades)",
|
|
|
|
[11] = "Pentium III (Tualatin)",
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{ .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
|
|
|
|
{
|
|
|
|
[0] = "Pentium 4 (Unknown)",
|
|
|
|
[1] = "Pentium 4 (Willamette)",
|
|
|
|
[2] = "Pentium 4 (Northwood)",
|
|
|
|
[4] = "Pentium 4 (Foster)",
|
|
|
|
[5] = "Pentium 4 (Foster)",
|
|
|
|
}
|
|
|
|
},
|
|
|
|
},
|
2008-09-09 23:40:35 +00:00
|
|
|
.c_size_cache = intel_size_cache,
|
|
|
|
#endif
|
x86: use ELF section to list CPU vendor specific code
Replace the hardcoded list of initialization functions for each CPU
vendor by a list in an ELF section, which is read at initialization in
arch/x86/kernel/cpu/cpu.c to fill the cpu_devs[] array. The ELF
section, named .x86cpuvendor.init, is reclaimed after boot, and
contains entries of type "struct cpu_vendor_dev" which associates a
vendor number with a pointer to a "struct cpu_dev" structure.
This first modification allows to remove all the VENDOR_init_cpu()
functions.
This patch also removes the hardcoded calls to early_init_amd() and
early_init_intel(). Instead, we add a "c_early_init" member to the
cpu_dev structure, which is then called if not NULL by the generic CPU
initialization code. Unfortunately, in early_cpu_detect(), this_cpu is
not yet set, so we have to use the cpu_devs[] array directly.
This patch is part of the Linux Tiny project, and is needed for
further patch that will allow to disable compilation of unused CPU
support code.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2008-02-15 11:00:23 +00:00
|
|
|
.c_early_init = early_init_intel,
|
2005-04-16 22:20:36 +00:00
|
|
|
.c_init = init_intel,
|
2008-09-04 19:09:45 +00:00
|
|
|
.c_x86_vendor = X86_VENDOR_INTEL,
|
2005-04-16 22:20:36 +00:00
|
|
|
};
|
|
|
|
|
2008-09-04 19:09:45 +00:00
|
|
|
cpu_dev_register(intel_cpu_dev);
|
2005-04-16 22:20:36 +00:00
|
|
|
|