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x86: remove smp_apply_quirks()/smp_checks()
Impact: cleanup and code size reduction on 64-bit This code is only applied to Intel Pentium and AMD K7 32-bit cpus. Move those checks to intel_init()/amd_init() for 32-bit so 64-bit will not build this code. Also change to use cpu_index check to see if we need to emit warning. Signed-off-by: Yinghai Lu <yinghai@kernel.org> LKML-Reference: <49B377D2.8030108@kernel.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Yinghai Lu
Ingo Molnar
parent
31bbed527e
commit
1f442d70c8
@ -5,6 +5,7 @@
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/apic.h>
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#include <asm/cpu.h>
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#ifdef CONFIG_X86_64
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# include <asm/numa_64.h>
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@ -141,6 +142,55 @@ static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
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}
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}
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static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_SMP
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/* calling is from identify_secondary_cpu() ? */
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if (c->cpu_index == boot_cpu_id)
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return;
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/*
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* Certain Athlons might work (for various values of 'work') in SMP
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* but they are not certified as MP capable.
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*/
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/* Athlon 660/661 is valid. */
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if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
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(c->x86_mask == 1)))
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goto valid_k7;
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/* Duron 670 is valid */
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if ((c->x86_model == 7) && (c->x86_mask == 0))
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goto valid_k7;
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/*
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* Athlon 662, Duron 671, and Athlon >model 7 have capability
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* bit. It's worth noting that the A5 stepping (662) of some
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* Athlon XP's have the MP bit set.
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* See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
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* more.
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*/
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if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
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((c->x86_model == 7) && (c->x86_mask >= 1)) ||
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(c->x86_model > 7))
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if (cpu_has_mp)
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goto valid_k7;
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/* If we get here, not a certified SMP capable AMD system. */
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/*
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* Don't taint if we are running SMP kernel on a single non-MP
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* approved Athlon
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*/
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WARN_ONCE(1, "WARNING: This combination of AMD"
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"processors is not suitable for SMP.\n");
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if (!test_taint(TAINT_UNSAFE_SMP))
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add_taint(TAINT_UNSAFE_SMP);
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valid_k7:
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;
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#endif
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}
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static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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@ -175,6 +225,8 @@ static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
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}
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set_cpu_cap(c, X86_FEATURE_K7);
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amd_k7_smp_check(c);
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}
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#endif
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@ -13,6 +13,7 @@
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#include <asm/uaccess.h>
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#include <asm/ds.h>
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#include <asm/bugs.h>
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#include <asm/cpu.h>
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#ifdef CONFIG_X86_64
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#include <asm/topology.h>
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@ -110,6 +111,28 @@ static void __cpuinit trap_init_f00f_bug(void)
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}
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#endif
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static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_SMP
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/* calling is from identify_secondary_cpu() ? */
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if (c->cpu_index == boot_cpu_id)
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return;
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/*
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* Mask B, Pentium, but not Pentium MMX
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*/
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if (c->x86 == 5 &&
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c->x86_mask >= 1 && c->x86_mask <= 4 &&
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c->x86_model <= 3) {
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/*
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* Remember we have B step Pentia with bugs
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*/
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WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
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"with B stepping processors.\n");
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}
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#endif
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}
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static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
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{
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unsigned long lo, hi;
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@ -186,6 +209,8 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
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#ifdef CONFIG_X86_NUMAQ
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numaq_tsc_disable();
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#endif
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intel_smp_check(c);
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}
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#else
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static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
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@ -114,10 +114,6 @@ EXPORT_PER_CPU_SYMBOL(cpu_info);
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atomic_t init_deasserted;
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/* Set if we find a B stepping CPU */
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static int __cpuinitdata smp_b_stepping;
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#if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
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/* which logical CPUs are on which nodes */
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@ -271,8 +267,6 @@ static void __cpuinit smp_callin(void)
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cpumask_set_cpu(cpuid, cpu_callin_mask);
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}
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static int __cpuinitdata unsafe_smp;
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/*
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* Activate a secondary processor.
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*/
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@ -340,76 +334,6 @@ notrace static void __cpuinit start_secondary(void *unused)
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cpu_idle();
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}
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static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
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{
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/*
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* Mask B, Pentium, but not Pentium MMX
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*/
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if (c->x86_vendor == X86_VENDOR_INTEL &&
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c->x86 == 5 &&
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c->x86_mask >= 1 && c->x86_mask <= 4 &&
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c->x86_model <= 3)
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/*
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* Remember we have B step Pentia with bugs
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*/
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smp_b_stepping = 1;
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/*
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* Certain Athlons might work (for various values of 'work') in SMP
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* but they are not certified as MP capable.
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*/
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if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
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if (num_possible_cpus() == 1)
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goto valid_k7;
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/* Athlon 660/661 is valid. */
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if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
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(c->x86_mask == 1)))
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goto valid_k7;
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/* Duron 670 is valid */
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if ((c->x86_model == 7) && (c->x86_mask == 0))
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goto valid_k7;
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/*
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* Athlon 662, Duron 671, and Athlon >model 7 have capability
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* bit. It's worth noting that the A5 stepping (662) of some
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* Athlon XP's have the MP bit set.
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* See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
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* more.
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*/
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if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
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((c->x86_model == 7) && (c->x86_mask >= 1)) ||
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(c->x86_model > 7))
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if (cpu_has_mp)
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goto valid_k7;
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/* If we get here, not a certified SMP capable AMD system. */
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unsafe_smp = 1;
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}
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valid_k7:
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;
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}
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static void __cpuinit smp_checks(void)
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{
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if (smp_b_stepping)
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printk(KERN_WARNING "WARNING: SMP operation may be unreliable"
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"with B stepping processors.\n");
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/*
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* Don't taint if we are running SMP kernel on a single non-MP
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* approved Athlon
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*/
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if (unsafe_smp && num_online_cpus() > 1) {
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printk(KERN_INFO "WARNING: This combination of AMD"
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"processors is not suitable for SMP.\n");
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add_taint(TAINT_UNSAFE_SMP);
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}
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}
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/*
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* The bootstrap kernel entry code has set these up. Save them for
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* a given CPU
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@ -423,7 +347,6 @@ void __cpuinit smp_store_cpu_info(int id)
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c->cpu_index = id;
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if (id != 0)
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identify_secondary_cpu(c);
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smp_apply_quirks(c);
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}
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@ -1193,7 +1116,6 @@ void __init native_smp_cpus_done(unsigned int max_cpus)
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pr_debug("Boot done.\n");
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impress_friends();
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smp_checks();
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#ifdef CONFIG_X86_IO_APIC
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setup_ioapic_dest();
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#endif
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