License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2010-01-08 15:02:30 +00:00
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#ifndef __MACH_MX35_H__
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#define __MACH_MX35_H__
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2010-10-08 14:00:10 +00:00
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2009-02-02 13:11:54 +00:00
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/*
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* IRAM
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*/
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#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
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2009-11-12 20:47:57 +00:00
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#define MX35_IRAM_SIZE SZ_128K
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2009-02-02 13:11:54 +00:00
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2009-11-13 20:25:01 +00:00
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#define MX35_L2CC_BASE_ADDR 0x30000000
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#define MX35_L2CC_SIZE SZ_1M
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#define MX35_AIPS1_BASE_ADDR 0x43f00000
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#define MX35_AIPS1_SIZE SZ_1M
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#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
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#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
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#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000)
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#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
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#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
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#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
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2010-06-16 17:25:34 +00:00
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#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
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2009-11-13 20:25:01 +00:00
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#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
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#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
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#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
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#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000)
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#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000)
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#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000)
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#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000)
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#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000)
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#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000)
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#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000)
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#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
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#define MX35_SPBA0_BASE_ADDR 0x50000000
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#define MX35_SPBA0_SIZE SZ_1M
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#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
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#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
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#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000)
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2011-08-23 20:18:06 +00:00
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#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000)
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2009-11-13 20:25:01 +00:00
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#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000)
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2009-11-12 20:47:57 +00:00
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#define MX35_FEC_BASE_ADDR 0x50038000
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2009-11-13 20:25:01 +00:00
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#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
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#define MX35_AIPS2_BASE_ADDR 0x53f00000
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#define MX35_AIPS2_SIZE SZ_1M
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#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
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#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
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#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000)
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#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000)
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#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
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#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
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#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
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2010-10-11 10:55:22 +00:00
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#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000)
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#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000)
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#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000)
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2009-11-13 20:25:01 +00:00
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#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
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#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
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#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
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#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000)
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#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000)
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#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000)
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#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000)
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#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000)
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2010-07-22 09:41:56 +00:00
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#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000)
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#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
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2009-11-13 20:25:01 +00:00
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#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
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2010-10-08 14:00:10 +00:00
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#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
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2010-11-12 15:40:06 +00:00
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#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000)
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#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000)
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/*
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* The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
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* HS. When host support was implemented only a preliminary document was
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* available, which told 0x400. This works fine.
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*/
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#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400)
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2009-11-13 20:25:01 +00:00
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#define MX35_ROMP_BASE_ADDR 0x60000000
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#define MX35_ROMP_SIZE SZ_1M
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#define MX35_AVIC_BASE_ADDR 0x68000000
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#define MX35_AVIC_SIZE SZ_1M
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/*
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* Memory regions and CS
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*/
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#define MX35_IPU_MEM_BASE_ADDR 0x70000000
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#define MX35_CSD0_BASE_ADDR 0x80000000
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#define MX35_CSD1_BASE_ADDR 0x90000000
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#define MX35_CS0_BASE_ADDR 0xa0000000
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#define MX35_CS1_BASE_ADDR 0xa8000000
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#define MX35_CS2_BASE_ADDR 0xb0000000
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#define MX35_CS3_BASE_ADDR 0xb2000000
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#define MX35_CS4_BASE_ADDR 0xb4000000
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2010-10-25 13:44:25 +00:00
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#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000
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2009-11-13 20:25:01 +00:00
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#define MX35_CS4_SIZE SZ_32M
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#define MX35_CS5_BASE_ADDR 0xb6000000
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2010-10-25 13:44:25 +00:00
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#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000
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2009-11-13 20:25:01 +00:00
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#define MX35_CS5_SIZE SZ_32M
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/*
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* NAND, SDRAM, WEIM, M3IF, EMI controllers
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*/
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#define MX35_X_MEMC_BASE_ADDR 0xb8000000
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#define MX35_X_MEMC_SIZE SZ_64K
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#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
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#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
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#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000)
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#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000)
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#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR
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2009-11-12 20:47:57 +00:00
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#define MX35_NFC_BASE_ADDR 0xbb000000
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2009-11-13 20:25:01 +00:00
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#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
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2009-02-02 13:11:54 +00:00
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2010-10-25 13:44:25 +00:00
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#define MX35_IO_P2V(x) IMX_IO_P2V(x)
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2010-10-25 09:40:30 +00:00
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#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x))
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2009-12-16 18:07:20 +00:00
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2009-02-02 13:11:54 +00:00
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/*
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* Interrupt numbers
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*/
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2012-06-14 03:16:14 +00:00
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#include <asm/irq.h>
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#define MX35_INT_OWIRE (NR_IRQS_LEGACY + 2)
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#define MX35_INT_I2C3 (NR_IRQS_LEGACY + 3)
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#define MX35_INT_I2C2 (NR_IRQS_LEGACY + 4)
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#define MX35_INT_RTIC (NR_IRQS_LEGACY + 6)
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#define MX35_INT_ESDHC1 (NR_IRQS_LEGACY + 7)
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#define MX35_INT_ESDHC2 (NR_IRQS_LEGACY + 8)
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#define MX35_INT_ESDHC3 (NR_IRQS_LEGACY + 9)
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#define MX35_INT_I2C1 (NR_IRQS_LEGACY + 10)
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#define MX35_INT_SSI1 (NR_IRQS_LEGACY + 11)
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#define MX35_INT_SSI2 (NR_IRQS_LEGACY + 12)
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#define MX35_INT_CSPI2 (NR_IRQS_LEGACY + 13)
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#define MX35_INT_CSPI1 (NR_IRQS_LEGACY + 14)
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#define MX35_INT_ATA (NR_IRQS_LEGACY + 15)
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#define MX35_INT_GPU2D (NR_IRQS_LEGACY + 16)
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#define MX35_INT_ASRC (NR_IRQS_LEGACY + 17)
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#define MX35_INT_UART3 (NR_IRQS_LEGACY + 18)
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#define MX35_INT_IIM (NR_IRQS_LEGACY + 19)
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#define MX35_INT_RNGA (NR_IRQS_LEGACY + 22)
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#define MX35_INT_EVTMON (NR_IRQS_LEGACY + 23)
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#define MX35_INT_KPP (NR_IRQS_LEGACY + 24)
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#define MX35_INT_RTC (NR_IRQS_LEGACY + 25)
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#define MX35_INT_PWM (NR_IRQS_LEGACY + 26)
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#define MX35_INT_EPIT2 (NR_IRQS_LEGACY + 27)
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#define MX35_INT_EPIT1 (NR_IRQS_LEGACY + 28)
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#define MX35_INT_GPT (NR_IRQS_LEGACY + 29)
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#define MX35_INT_POWER_FAIL (NR_IRQS_LEGACY + 30)
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#define MX35_INT_UART2 (NR_IRQS_LEGACY + 32)
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#define MX35_INT_NFC (NR_IRQS_LEGACY + 33)
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#define MX35_INT_SDMA (NR_IRQS_LEGACY + 34)
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#define MX35_INT_USB_HS (NR_IRQS_LEGACY + 35)
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#define MX35_INT_USB_OTG (NR_IRQS_LEGACY + 37)
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#define MX35_INT_MSHC1 (NR_IRQS_LEGACY + 39)
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#define MX35_INT_ESAI (NR_IRQS_LEGACY + 40)
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#define MX35_INT_IPU_ERR (NR_IRQS_LEGACY + 41)
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#define MX35_INT_IPU_SYN (NR_IRQS_LEGACY + 42)
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#define MX35_INT_CAN1 (NR_IRQS_LEGACY + 43)
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#define MX35_INT_CAN2 (NR_IRQS_LEGACY + 44)
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#define MX35_INT_UART1 (NR_IRQS_LEGACY + 45)
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#define MX35_INT_MLB (NR_IRQS_LEGACY + 46)
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#define MX35_INT_SPDIF (NR_IRQS_LEGACY + 47)
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#define MX35_INT_ECT (NR_IRQS_LEGACY + 48)
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#define MX35_INT_SCC_SCM (NR_IRQS_LEGACY + 49)
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#define MX35_INT_SCC_SMN (NR_IRQS_LEGACY + 50)
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#define MX35_INT_GPIO2 (NR_IRQS_LEGACY + 51)
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#define MX35_INT_GPIO1 (NR_IRQS_LEGACY + 52)
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#define MX35_INT_WDOG (NR_IRQS_LEGACY + 55)
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#define MX35_INT_GPIO3 (NR_IRQS_LEGACY + 56)
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#define MX35_INT_FEC (NR_IRQS_LEGACY + 57)
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#define MX35_INT_EXT_POWER (NR_IRQS_LEGACY + 58)
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#define MX35_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59)
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#define MX35_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60)
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#define MX35_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61)
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#define MX35_INT_EXT_WDOG (NR_IRQS_LEGACY + 62)
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#define MX35_INT_EXT_TV (NR_IRQS_LEGACY + 63)
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2009-11-13 20:25:01 +00:00
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2010-08-25 15:37:45 +00:00
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#define MX35_DMA_REQ_SSI2_RX1 22
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#define MX35_DMA_REQ_SSI2_TX1 23
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#define MX35_DMA_REQ_SSI2_RX0 24
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#define MX35_DMA_REQ_SSI2_TX0 25
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#define MX35_DMA_REQ_SSI1_RX1 26
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#define MX35_DMA_REQ_SSI1_TX1 27
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#define MX35_DMA_REQ_SSI1_RX0 28
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#define MX35_DMA_REQ_SSI1_TX0 29
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2009-11-13 20:25:01 +00:00
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#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
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2010-01-08 15:02:30 +00:00
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#endif /* ifndef __MACH_MX35_H__ */
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