2009-02-02 13:11:54 +00:00
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/*
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* IRAM
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*/
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#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
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2009-11-12 20:47:57 +00:00
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#define MX35_IRAM_SIZE SZ_128K
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2009-02-02 13:11:54 +00:00
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2009-11-12 20:47:57 +00:00
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#define MX35_FEC_BASE_ADDR 0x50038000
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#define MX35_OTG_BASE_ADDR 0x53ff4000
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#define MX35_NFC_BASE_ADDR 0xbb000000
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2009-02-02 13:11:54 +00:00
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/*
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* Interrupt numbers
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*/
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2009-11-12 20:47:57 +00:00
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#define MX35_INT_OWIRE 2
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2009-02-02 13:11:54 +00:00
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#define MX35_INT_MMC_SDHC1 7
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2009-11-12 20:47:57 +00:00
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#define MX35_INT_MMC_SDHC2 8
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#define MX35_INT_MMC_SDHC3 9
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2009-02-02 13:11:54 +00:00
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#define MX35_INT_SSI1 11
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#define MX35_INT_SSI2 12
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2009-11-12 20:47:57 +00:00
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#define MX35_INT_GPU2D 16
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#define MX35_INT_ASRC 17
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#define MX35_INT_USBHS 35
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#define MX35_INT_USBOTG 37
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#define MX35_INT_ESAI 40
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#define MX35_INT_CAN1 43
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#define MX35_INT_CAN2 44
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#define MX35_INT_MLB 46
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#define MX35_INT_SPDIF 47
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#define MX35_INT_FEC 57
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2009-02-02 13:11:54 +00:00
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2009-11-12 20:47:57 +00:00
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/* these should go away */
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#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
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#define MXC_INT_OWIRE MX35_INT_OWIRE
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#define MXC_INT_MMC_SDHC2 MX35_INT_MMC_SDHC2
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#define MXC_INT_MMC_SDHC3 MX35_INT_MMC_SDHC3
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#define MXC_INT_GPU2D MX35_INT_GPU2D
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#define MXC_INT_ASRC MX35_INT_ASRC
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#define MXC_INT_USBHS MX35_INT_USBHS
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#define MXC_INT_USBOTG MX35_INT_USBOTG
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#define MXC_INT_ESAI MX35_INT_ESAI
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#define MXC_INT_CAN1 MX35_INT_CAN1
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#define MXC_INT_CAN2 MX35_INT_CAN2
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#define MXC_INT_MLB MX35_INT_MLB
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#define MXC_INT_SPDIF MX35_INT_SPDIF
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#define MXC_INT_FEC MX35_INT_FEC
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