2021-02-03 15:04:34 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Irqdomain for Linux to run as the root partition on Microsoft Hypervisor.
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*
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* Authors:
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* Sunil Muthuswamy <sunilmut@microsoft.com>
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* Wei Liu <wei.liu@kernel.org>
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*/
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <asm/mshyperv.h>
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static int hv_map_interrupt(union hv_device_id device_id, bool level,
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int cpu, int vector, struct hv_interrupt_entry *entry)
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{
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struct hv_input_map_device_interrupt *input;
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struct hv_output_map_device_interrupt *output;
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struct hv_device_interrupt_descriptor *intr_desc;
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unsigned long flags;
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u64 status;
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int nr_bank, var_size;
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local_irq_save(flags);
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input = *this_cpu_ptr(hyperv_pcpu_input_arg);
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output = *this_cpu_ptr(hyperv_pcpu_output_arg);
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intr_desc = &input->interrupt_descriptor;
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memset(input, 0, sizeof(*input));
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input->partition_id = hv_current_partition_id;
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input->device_id = device_id.as_uint64;
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intr_desc->interrupt_type = HV_X64_INTERRUPT_TYPE_FIXED;
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intr_desc->vector_count = 1;
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intr_desc->target.vector = vector;
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if (level)
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intr_desc->trigger_mode = HV_INTERRUPT_TRIGGER_MODE_LEVEL;
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else
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intr_desc->trigger_mode = HV_INTERRUPT_TRIGGER_MODE_EDGE;
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intr_desc->target.vp_set.valid_bank_mask = 0;
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intr_desc->target.vp_set.format = HV_GENERIC_SET_SPARSE_4K;
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nr_bank = cpumask_to_vpset(&(intr_desc->target.vp_set), cpumask_of(cpu));
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if (nr_bank < 0) {
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local_irq_restore(flags);
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pr_err("%s: unable to generate VP set\n", __func__);
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return EINVAL;
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}
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intr_desc->target.flags = HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET;
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/*
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* var-sized hypercall, var-size starts after vp_mask (thus
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* vp_set.format does not count, but vp_set.valid_bank_mask
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* does).
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*/
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var_size = nr_bank + 1;
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status = hv_do_rep_hypercall(HVCALL_MAP_DEVICE_INTERRUPT, 0, var_size,
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input, output);
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*entry = output->interrupt_entry;
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local_irq_restore(flags);
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2021-04-17 00:43:03 +00:00
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if (!hv_result_success(status))
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2021-02-03 15:04:34 +00:00
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pr_err("%s: hypercall failed, status %lld\n", __func__, status);
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2021-04-17 00:43:03 +00:00
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return hv_result(status);
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2021-02-03 15:04:34 +00:00
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}
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static int hv_unmap_interrupt(u64 id, struct hv_interrupt_entry *old_entry)
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{
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unsigned long flags;
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struct hv_input_unmap_device_interrupt *input;
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struct hv_interrupt_entry *intr_entry;
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u64 status;
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local_irq_save(flags);
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input = *this_cpu_ptr(hyperv_pcpu_input_arg);
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memset(input, 0, sizeof(*input));
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intr_entry = &input->interrupt_entry;
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input->partition_id = hv_current_partition_id;
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input->device_id = id;
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*intr_entry = *old_entry;
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status = hv_do_hypercall(HVCALL_UNMAP_DEVICE_INTERRUPT, input, NULL);
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local_irq_restore(flags);
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2021-04-17 00:43:03 +00:00
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return hv_result(status);
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2021-02-03 15:04:34 +00:00
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}
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#ifdef CONFIG_PCI_MSI
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struct rid_data {
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struct pci_dev *bridge;
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u32 rid;
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};
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static int get_rid_cb(struct pci_dev *pdev, u16 alias, void *data)
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{
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struct rid_data *rd = data;
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u8 bus = PCI_BUS_NUM(rd->rid);
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if (pdev->bus->number != bus || PCI_BUS_NUM(alias) != bus) {
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rd->bridge = pdev;
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rd->rid = alias;
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}
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return 0;
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}
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static union hv_device_id hv_build_pci_dev_id(struct pci_dev *dev)
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{
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union hv_device_id dev_id;
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struct rid_data data = {
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.bridge = NULL,
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.rid = PCI_DEVID(dev->bus->number, dev->devfn)
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};
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pci_for_each_dma_alias(dev, get_rid_cb, &data);
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dev_id.as_uint64 = 0;
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dev_id.device_type = HV_DEVICE_TYPE_PCI;
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dev_id.pci.segment = pci_domain_nr(dev->bus);
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dev_id.pci.bdf.bus = PCI_BUS_NUM(data.rid);
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dev_id.pci.bdf.device = PCI_SLOT(data.rid);
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dev_id.pci.bdf.function = PCI_FUNC(data.rid);
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dev_id.pci.source_shadow = HV_SOURCE_SHADOW_NONE;
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if (data.bridge) {
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int pos;
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/*
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* Microsoft Hypervisor requires a bus range when the bridge is
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* running in PCI-X mode.
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*
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* To distinguish conventional vs PCI-X bridge, we can check
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* the bridge's PCI-X Secondary Status Register, Secondary Bus
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* Mode and Frequency bits. See PCI Express to PCI/PCI-X Bridge
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* Specification Revision 1.0 5.2.2.1.3.
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*
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* Value zero means it is in conventional mode, otherwise it is
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* in PCI-X mode.
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*/
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pos = pci_find_capability(data.bridge, PCI_CAP_ID_PCIX);
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if (pos) {
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u16 status;
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pci_read_config_word(data.bridge, pos +
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PCI_X_BRIDGE_SSTATUS, &status);
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if (status & PCI_X_SSTATUS_FREQ) {
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/* Non-zero, PCI-X mode */
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u8 sec_bus, sub_bus;
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dev_id.pci.source_shadow = HV_SOURCE_SHADOW_BRIDGE_BUS_RANGE;
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pci_read_config_byte(data.bridge, PCI_SECONDARY_BUS, &sec_bus);
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dev_id.pci.shadow_bus_range.secondary_bus = sec_bus;
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pci_read_config_byte(data.bridge, PCI_SUBORDINATE_BUS, &sub_bus);
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dev_id.pci.shadow_bus_range.subordinate_bus = sub_bus;
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}
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}
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}
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return dev_id;
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}
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static int hv_map_msi_interrupt(struct pci_dev *dev, int cpu, int vector,
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struct hv_interrupt_entry *entry)
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{
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union hv_device_id device_id = hv_build_pci_dev_id(dev);
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return hv_map_interrupt(device_id, false, cpu, vector, entry);
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}
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static inline void entry_to_msi_msg(struct hv_interrupt_entry *entry, struct msi_msg *msg)
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{
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/* High address is always 0 */
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msg->address_hi = 0;
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msg->address_lo = entry->msi_entry.address.as_uint32;
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msg->data = entry->msi_entry.data.as_uint32;
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}
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static int hv_unmap_msi_interrupt(struct pci_dev *dev, struct hv_interrupt_entry *old_entry);
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static void hv_irq_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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struct msi_desc *msidesc;
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struct pci_dev *dev;
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struct hv_interrupt_entry out_entry, *stored_entry;
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struct irq_cfg *cfg = irqd_cfg(data);
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2022-07-01 20:00:55 +00:00
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const cpumask_t *affinity;
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2021-02-03 15:04:34 +00:00
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int cpu;
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u64 status;
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msidesc = irq_data_get_msi_desc(data);
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dev = msi_desc_to_pci_dev(msidesc);
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if (!cfg) {
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pr_debug("%s: cfg is NULL", __func__);
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return;
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}
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affinity = irq_data_get_effective_affinity_mask(data);
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cpu = cpumask_first_and(affinity, cpu_online_mask);
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if (data->chip_data) {
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/*
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* This interrupt is already mapped. Let's unmap first.
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*
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* We don't use retarget interrupt hypercalls here because
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* Microsoft Hypervisor doens't allow root to change the vector
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* or specify VPs outside of the set that is initially used
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* during mapping.
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*/
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stored_entry = data->chip_data;
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data->chip_data = NULL;
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status = hv_unmap_msi_interrupt(dev, stored_entry);
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kfree(stored_entry);
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if (status != HV_STATUS_SUCCESS) {
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pr_debug("%s: failed to unmap, status %lld", __func__, status);
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return;
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}
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}
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stored_entry = kzalloc(sizeof(*stored_entry), GFP_ATOMIC);
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if (!stored_entry) {
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pr_debug("%s: failed to allocate chip data\n", __func__);
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return;
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}
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status = hv_map_msi_interrupt(dev, cpu, cfg->vector, &out_entry);
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if (status != HV_STATUS_SUCCESS) {
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kfree(stored_entry);
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return;
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}
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*stored_entry = out_entry;
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data->chip_data = stored_entry;
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entry_to_msi_msg(&out_entry, msg);
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return;
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}
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static int hv_unmap_msi_interrupt(struct pci_dev *dev, struct hv_interrupt_entry *old_entry)
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{
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return hv_unmap_interrupt(hv_build_pci_dev_id(dev).as_uint64, old_entry);
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}
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2021-12-06 22:27:41 +00:00
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static void hv_teardown_msi_irq(struct pci_dev *dev, struct irq_data *irqd)
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2021-02-03 15:04:34 +00:00
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{
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struct hv_interrupt_entry old_entry;
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struct msi_msg msg;
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2021-12-06 22:27:41 +00:00
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u64 status;
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2021-02-03 15:04:34 +00:00
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2021-12-06 22:27:41 +00:00
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if (!irqd->chip_data) {
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2021-02-03 15:04:34 +00:00
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pr_debug("%s: no chip data\n!", __func__);
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return;
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}
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2021-12-06 22:27:41 +00:00
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old_entry = *(struct hv_interrupt_entry *)irqd->chip_data;
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2021-02-03 15:04:34 +00:00
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entry_to_msi_msg(&old_entry, &msg);
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2021-12-06 22:27:41 +00:00
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kfree(irqd->chip_data);
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irqd->chip_data = NULL;
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2021-02-03 15:04:34 +00:00
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status = hv_unmap_msi_interrupt(dev, &old_entry);
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2021-12-06 22:27:41 +00:00
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if (status != HV_STATUS_SUCCESS)
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2021-02-03 15:04:34 +00:00
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pr_err("%s: hypercall failed, status %lld\n", __func__, status);
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}
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2021-12-06 22:27:41 +00:00
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static void hv_msi_free_irq(struct irq_domain *domain,
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struct msi_domain_info *info, unsigned int virq)
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2021-02-03 15:04:34 +00:00
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{
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2021-12-06 22:27:41 +00:00
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struct irq_data *irqd = irq_get_irq_data(virq);
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struct msi_desc *desc;
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2021-02-03 15:04:34 +00:00
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2021-12-06 22:27:41 +00:00
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if (!irqd)
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2021-02-03 15:04:34 +00:00
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return;
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2021-12-06 22:27:41 +00:00
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desc = irq_data_get_msi_desc(irqd);
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if (!desc || !desc->irq || WARN_ON_ONCE(!dev_is_pci(desc->dev)))
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return;
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2021-02-03 15:04:34 +00:00
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2021-12-06 22:27:41 +00:00
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hv_teardown_msi_irq(to_pci_dev(desc->dev), irqd);
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2021-02-03 15:04:34 +00:00
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}
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/*
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* IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
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* which implement the MSI or MSI-X Capability Structure.
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*/
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static struct irq_chip hv_pci_msi_controller = {
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.name = "HV-PCI-MSI",
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.irq_unmask = pci_msi_unmask_irq,
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.irq_mask = pci_msi_mask_irq,
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.irq_ack = irq_chip_ack_parent,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_compose_msi_msg = hv_irq_compose_msi_msg,
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.irq_set_affinity = msi_domain_set_affinity,
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.flags = IRQCHIP_SKIP_SET_WAKE,
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};
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static struct msi_domain_ops pci_msi_domain_ops = {
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2021-12-06 22:27:41 +00:00
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.msi_free = hv_msi_free_irq,
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2021-02-03 15:04:34 +00:00
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.msi_prepare = pci_msi_prepare,
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};
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static struct msi_domain_info hv_pci_msi_domain_info = {
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.flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_PCI_MSIX,
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.ops = &pci_msi_domain_ops,
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.chip = &hv_pci_msi_controller,
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.handler = handle_edge_irq,
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.handler_name = "edge",
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};
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struct irq_domain * __init hv_create_pci_msi_domain(void)
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{
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struct irq_domain *d = NULL;
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struct fwnode_handle *fn;
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fn = irq_domain_alloc_named_fwnode("HV-PCI-MSI");
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if (fn)
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d = pci_msi_create_irq_domain(fn, &hv_pci_msi_domain_info, x86_vector_domain);
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/* No point in going further if we can't get an irq domain */
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BUG_ON(!d);
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return d;
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}
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#endif /* CONFIG_PCI_MSI */
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2021-02-03 15:04:35 +00:00
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int hv_unmap_ioapic_interrupt(int ioapic_id, struct hv_interrupt_entry *entry)
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{
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union hv_device_id device_id;
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device_id.as_uint64 = 0;
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device_id.device_type = HV_DEVICE_TYPE_IOAPIC;
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device_id.ioapic.ioapic_id = (u8)ioapic_id;
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return hv_unmap_interrupt(device_id.as_uint64, entry);
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}
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EXPORT_SYMBOL_GPL(hv_unmap_ioapic_interrupt);
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int hv_map_ioapic_interrupt(int ioapic_id, bool level, int cpu, int vector,
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struct hv_interrupt_entry *entry)
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{
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union hv_device_id device_id;
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device_id.as_uint64 = 0;
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device_id.device_type = HV_DEVICE_TYPE_IOAPIC;
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device_id.ioapic.ioapic_id = (u8)ioapic_id;
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return hv_map_interrupt(device_id, level, cpu, vector, entry);
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}
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EXPORT_SYMBOL_GPL(hv_map_ioapic_interrupt);
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