Commit Graph

106767 Commits

Author SHA1 Message Date
Vineet Gupta
4fbf81ca53 ARC: kgdb: generic kgdb_arch_pc() suffices
The ARC version of kgdb_arch_pc() is identical to the generic version in
kernel/debug/debug_core.c.  Drop the ARC version so we use the generic one.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-10-22 16:14:04 -06:00
Bjorn Helgaas
754f0da0dc x86, intel-mid: Remove "weak" from function declarations
For the following interfaces:

  get_penwell_ops()
  get_cloverview_ops()
  get_tangier_ops()

there is only one implementation, so they do not need to be marked "weak".

Remove the "weak" attribute from their declarations.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Ingo Molnar <mingo@kernel.org>
CC: David Cohen <david.a.cohen@linux.intel.com>
CC: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
CC: x86@kernel.org
2014-10-22 16:14:03 -06:00
Stefan Hengelein
44da7623e3 MIPS: ath79: Fix compilation error when CONFIG_PCI is disabled
When CONFIG_PCI is disabled, 'db120_pci_init()' had a different
signature than when was enabled. Therefore, compilation failed when
CONFIG_PCI was not present.

arch/mips/ath79/mach-db120.c:132: error: too many arguments to function 'db120_pci_init'

This error was found with vampyr.

Signed-off-by: Stefan Hengelein <stefan.hengelein@fau.de>
Reviewed-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: geert@linux-m68k.org
Patchwork: https://patchwork.linux-mips.org/patch/8119/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-22 23:16:59 +02:00
Stefan Hengelein
cd3d6438b4 MIPS: MSP71xx: Remove compilation error when CONFIG_MIPS_MT is present
When CONFIG_MIPS_MT is defined, code is enabled that tries to call
'set_vi_handler()'. This function is declared in <asm/setup.h> but the
header is never included. Therefore, the compilation breaks.

arch/mips/pmcs-msp71xx/msp_irq.c:133: error: implicit declaration of function 'set_vi_handler'

This error was found with vampyr.

Signed-off-by: Stefan Hengelein <stefan.hengelein@fau.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: ryazanov.s.a@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/8122/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-22 23:16:55 +02:00
Andy Lutomirski
b47dcbdc51 x86, apic: Handle a bad TSC more gracefully
If the TSC is unusable or disabled, then this patch fixes:

 - Confusion while trying to clear old APIC interrupts.
 - Division by zero and incorrect programming of the TSC deadline
   timer.

This fixes boot if the CPU has a TSC deadline timer but a missing or
broken TSC.  The failure to boot can be observed with qemu using
-cpu qemu64,-tsc,+tsc-deadline

This also happens to me in nested KVM for unknown reasons.
With this patch, I can boot cleanly (although without a TSC).

Signed-off-by: Andy Lutomirski <luto@amacapital.net>
Cc: Bandan Das <bsd@redhat.com>
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/e2fa274e498c33988efac0ba8b7e3120f7f92d78.1413393027.git.luto@amacapital.net
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-10-22 21:31:46 +02:00
David Daney
b61cd31ee6 MIPS: Octeon: Remove special case for simulator command line.
There is no reason to have the kernel to append commands when running
under the simulator, the simulator is perfectly capable of supplying
the necessary command line arguments.  Furthermore, if the simulator
needs something different than what is hard coded in the kernel, it
cannot get it if the kernel overrides it.

Fix/Simplify the whole thing by removing this bit.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8152/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-22 19:37:03 +02:00
David Daney
9e0f162a36 MIPS: tlbex: Properly fix HUGE TLB Refill exception handler
In commit 8393c524a2 (MIPS: tlbex: Fix a missing statement for
HUGETLB), the TLB Refill handler was fixed so that non-OCTEON targets
would work properly with huge pages.  The change was incorrect in that
it broke the OCTEON case.

The problem is shown here:

    xxx0:	df7a0000 	ld	k0,0(k1)
    .
    .
    .
    xxxc0:	df610000 	ld	at,0(k1)
    xxxc4:	335a0ff0 	andi	k0,k0,0xff0
    xxxc8:	e825ffcd 	bbit1	at,0x5,0x0
    xxxcc:	003ad82d 	daddu	k1,at,k0
    .
    .
    .

In the non-octeon case there is a destructive test for the huge PTE
bit, and then at 0, $k0 is reloaded (that is what the 8393c524a2
patch added).

In the octeon case, we modify k1 in the branch delay slot, but we
never need k0 again, so the new load is not needed, but since k1 is
modified, if we do the load, we load from a garbage location and then
get a nested TLB Refill, which is seen in userspace as either SIGBUS
or SIGSEGV (depending on the garbage).

The real fix is to only do this reloading if it is needed, and never
where it is harmful.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: stable@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8151/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-22 19:29:08 +02:00
Aaro Koskinen
aa08ed5544 MIPS: loongson2_cpufreq: Fix CPU clock rate setting mismerge
During 3.16 merge window, parts of the commit 8e8acb3296
(MIPS/loongson2_cpufreq: Fix CPU clock rate setting) seem to have
been deleted probably due to a mismerge, and as a result cpufreq
is broken again on Loongson2 boards in 3.16 and newer kernels.
Fix by repeating the fix.

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: stable@vger.kernel.org # 3.16
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7835/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-22 19:10:42 +02:00
Varka Bhadram
5a1e73ffe5 pci: pci-lantiq: remove duplicate check on resource
Sanity check on resource happening with devm_ioremap_resource()

Signed-off-by: Varka Bhadram <varkab@cdac.in>
Acked-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: Varka Bhadram <varkab@cdac.in>
Patchwork: https://patchwork.linux-mips.org/patch/8199/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-22 18:14:04 +02:00
Catalin Marinas
e2b6b35ee7 arm64: vexpress: Add CLCD support to the ARMv8 model platform
This patch enables CLCD support for the VE platform emulated by the
ARMv8 software model (DT bindings are based on Pawel's vexpress
patches) together with defconfig entries for SERIO_AMBAKMI and
FB_ARMCLCD.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Pawel Moll <pawel.moll@arm.com>
2014-10-22 15:33:16 +01:00
Linus Walleij
10d8ddee10 ARM: realview: add MMCI to the PB1176 DTS
This adds the MMC/SD card reader (MMCI) block to the
RealView PB1176 DTS file. Add a special MCLK derived clock
and a fixed regulator to represent the 3.3V rail hardwired
to the MMC reader on the board.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-22 13:49:13 +02:00
Linus Walleij
7406c3957f ARM: realview: add KMIs to the PB1176 DTS
This adds the Keyboard Mouse Interface (KMI) blocks to the
PB1176 DTS file, and defines the special KMI clock derived
from the 24 MHz chrystal.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-22 13:49:13 +02:00
Linus Walleij
7f9ac7dafe ARM: realview: add FPGA UART4 to PB1176 DTS
This adds the UART4 found on the FPGA to the PB1176 DTS
file.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-22 13:49:12 +02:00
Linus Walleij
24ec3ff329 ARM: realview: add PL022 SSP/SPI block to PB1176 DTS
Add the PL022 SSP/SPI block to the PL1176 DTS file, also
define the separate SSPCLK clock derived from the 24MHz
chrystal.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-22 13:49:11 +02:00
Linus Walleij
383caed2e5 ARM: realview: add RTC clocks to device tree
The PB1176 has two PL031 RTC clocks, one in the devchip and one
in the FPGA. Add them to the device tree.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-22 13:49:10 +02:00
Linus Walleij
ad38a34dc6 ARM: realview: add charlcd to PB1176 device tree
Extend the PB1176 device tree with the character LCD device.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-22 13:49:09 +02:00
Linus Walleij
75fd1324f9 ARM: realview: add PL061 GPIO to the PB1176 DTS
This adds the PL061 GPIO instances found on the PB1176 devchip
and the FPGA to the DTS file.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-22 13:49:08 +02:00
Linus Walleij
c7eb3f4a1b ARM: realview: move DT GIC to FPGA node
This creates a node in the device tree to hold the FPGA devices
as a "simple-bus" and moves the GIC found on the FPGA to this
node, so it reflects the actual topology of the system.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-22 13:49:07 +02:00
Linus Walleij
f123a66cbd ARM: realview: add device tree and bindings for PB1176
As a first example, add device tree and bindings for the
RealView PB1176.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-22 13:49:04 +02:00
Linus Walleij
fa6e2eec15 ARM: realview: basic device tree implementation
This implements basic device tree boot support for the RealView
platforms, with a basic device tree for ARM PB1176 as an example.

The implementation is done with a new DT-specific board file
using only pre-existing bindings for the basic IRQ, timer and
serial port drivers. A new compatible type is added to the GIC
for the ARM1176.

This implementation uses the MFD syscon handle from day one to
access the system controller registers, and register the devices
using the SoC bus.

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh@kernel.org>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-22 13:48:20 +02:00
Boris Brezillon
106c67af2f ARM: at91/dt: sam9263: fix PLLB frequencies
PLLB input and output ranges were wrongly copied from at91sam9261 as the
datasheet didn't mention explicitly PLLB. Correct their values.

This fixes USB.

Reported-by: Andreas Henriksson <andreas.henriksson@endian.se>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Tested-by: Andreas Henriksson <andreas.henriksson@endian.se>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2014-10-22 10:08:22 +02:00
Linus Walleij
9713497b6c ARM: integrator: set V4T and V5 as default multitargets
When switching the Integrator machines to multiplatform, the
V7 target becomes default, but most Integrators are V4T or V5,
so set these two as default in the defconfig and deselect V7.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-22 09:49:26 +02:00
Linus Walleij
68f3b875f7 ARM: integrator: make the Integrator multiplatform
This converts the ARM Integrator reference designs to be fully
multiplatform. V4T, V5 and V6 multiplatform builds become
possible after this patch.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-22 09:49:26 +02:00
Pranith Kumar
fcbb539f27 powerpc: Wire up sys_bpf() syscall
This patch wires up the new syscall sys_bpf() on powerpc.

Passes the tests in samples/bpf:

    #0 add+sub+mul OK
    #1 unreachable OK
    #2 unreachable2 OK
    #3 out of range jump OK
    #4 out of range jump2 OK
    #5 test1 ld_imm64 OK
    #6 test2 ld_imm64 OK
    #7 test3 ld_imm64 OK
    #8 test4 ld_imm64 OK
    #9 test5 ld_imm64 OK
    #10 no bpf_exit OK
    #11 loop (back-edge) OK
    #12 loop2 (back-edge) OK
    #13 conditional loop OK
    #14 read uninitialized register OK
    #15 read invalid register OK
    #16 program doesn't init R0 before exit OK
    #17 stack out of bounds OK
    #18 invalid call insn1 OK
    #19 invalid call insn2 OK
    #20 invalid function call OK
    #21 uninitialized stack1 OK
    #22 uninitialized stack2 OK
    #23 check valid spill/fill OK
    #24 check corrupted spill/fill OK
    #25 invalid src register in STX OK
    #26 invalid dst register in STX OK
    #27 invalid dst register in ST OK
    #28 invalid src register in LDX OK
    #29 invalid dst register in LDX OK
    #30 junk insn OK
    #31 junk insn2 OK
    #32 junk insn3 OK
    #33 junk insn4 OK
    #34 junk insn5 OK
    #35 misaligned read from stack OK
    #36 invalid map_fd for function call OK
    #37 don't check return value before access OK
    #38 access memory with incorrect alignment OK
    #39 sometimes access memory with incorrect alignment OK
    #40 jump test 1 OK
    #41 jump test 2 OK
    #42 jump test 3 OK
    #43 jump test 4 OK

Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
[mpe: test using samples/bpf]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2014-10-22 14:03:06 +11:00
Aneesh Kumar K.V
ca5f1d16a5 powerpc/mm: Remove redundant #if case
Remove the check of CONFIG_PPC_SUBPAGE_PROT when deciding if
is_hugepage_only_range() is extern or inline. The extern version is in
slice.c and is built if CONFIG_PPC_MM_SLICES=y.

There was no build break possible because CONFIG_PPC_SUBPAGE_PROT is
only selectable under conditions which also mean CONFIG_PPC_MM_SLICES
will be selected.

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2014-10-22 14:03:06 +11:00
Aneesh Kumar K.V
6643773ce1 powerpc/mm: Fix build error with hugetlfs disabled
arch/powerpc/mm/slice.c:704:5: error: expected identifier or ‘(’ before numeric constant
 int is_hugepage_only_range(struct mm_struct *mm, unsigned long addr,
     ^
make[1]: *** [arch/powerpc/mm/slice.o] Error 1
make: *** [arch/powerpc/mm/slice.o] Error 2

This got introduced via 1217d34b53
"powerpc: Ensure global functions include their prototype". We
started including linux/hugetlb.h with that patch and now we have

 #define is_hugepage_only_range(mm, addr, len)	0

with hugetlbfs disabled.

Fixes: 1217d34b53 ("powerpc: Ensure global functions include their prototype")
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2014-10-22 14:03:06 +11:00
Borislav Petkov
a3a529d104 x86, MCE, AMD: Drop software-defined bank in error thresholding
Aravind had the good question about why we're assigning a
software-defined bank when reporting error thresholding errors instead
of simply using the bank which reports the last error causing the
overflow.

Digging through git history, it pointed to

9526866439 ("[PATCH] x86_64: mce_amd support for family 0x10 processors")

which added that functionality. The problem with this, however, is that
tools don't know about software-defined banks and get puzzled. So drop
that K8_MCE_THRESHOLD_BASE and simply use the hw bank reporting the
thresholding interrupt.

Save us a couple of MSR reads while at it.

Reported-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
Link: https://lkml.kernel.org/r/5435B206.60402@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2014-10-21 22:28:48 +02:00
Chen Yucong
69b9575835 x86, MCE, AMD: Move invariant code out from loop body
Assigning to mce_threshold_vector is loop-invariant code in
mce_amd_feature_init(). So do it only once, out of loop body.

Signed-off-by: Chen Yucong <slaoub@gmail.com>
Link: http://lkml.kernel.org/r/1412263212.8085.6.camel@debian
[ Boris: commit message corrections. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
2014-10-21 22:12:56 +02:00
Chen Yucong
44612a3ac6 x86, MCE, AMD: Correct thresholding error logging
mce_setup() does not gather the content of IA32_MCG_STATUS, so it
should be read explicitly. Moreover, we need to clear IA32_MCx_STATUS
to avoid that mce_log() logs the processed threshold event again
at next time.

But we do the logging ourselves and machine_check_poll() is completely
useless there. So kill it.

Signed-off-by: Chen Yucong <slaoub@gmail.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
2014-10-21 22:12:22 +02:00
Chen Yucong
4b737d78a8 x86, MCE, AMD: Use macros to compute bank MSRs
Avoid open coded calculations for bank MSRs by hiding the index
of higher bank MSRs in well-defined macros.

No semantic changes.

Signed-off-by: Chen Yucong <slaoub@gmail.com>
Link: http://lkml.kernel.org/r/1411438561-24319-1-git-send-email-slaoub@gmail.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2014-10-21 22:07:24 +02:00
Chen-Yu Tsai
ac399a971d ARM: dts: sun9i: Add basic clocks and reset controls
Now that we have driver support for the basic clocks, add them to the
dtsi and update existing peripherals. Also add reset controls to match.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-21 21:50:39 +02:00
Dinh Nguyen
3a4356c0c0 arm: socfpga: fix fetching cpu1start_addr for SMP
When CPU1 is brought out of reset, it's MMU is not turned on yet, so it will
only be able to use physical addresses. For systems with that have the
MMU page configured for 0xC0000000, 0x80000000, or 0x40000000
"BIC 0x40000000" will work just fine, as it was just converting the
virtual address of &cpu1start_addr into a physical address, ie. 0xC0000000
became 0x80000000. So for systems where the SDRAM controller was able to do a
wrap-around access, this was working fine, as it was just dropping the MSB,
but for systems where out of bounds memory access is not allowed, this would
not allow CPU1 to correctly fetch &cpu1start_addr.

This patch fixes the secondary_trampoline code to correctly fetch the
physical address of cpu1start_addr directly. The patch will subtract the
correct PAGE_OFFSET from &cpu1start_addr. And since on this platform, the
physical memory will always start at 0x0, subtracting PAGE_OFFSET from
&cpu1start_addr will allow CPU1 to correctly fetch the value of cpu1start_addr.

While at it, change the name of cpu1start_addr to socfpga_cpu1start_addr
to avoid any future naming collisions for multiplatform image.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v4: Updated commit log to correctly lay out the usage of PAGE_OFFSET and
    add comments to the same effect.
v3: Used PAGE_OFFSET to get the physical address
v2: Correctly get the physical address instead of just a BIC hack.
2014-10-21 14:04:14 -05:00
Linus Torvalds
43d451f163 Merge branch 'mailbox-for-linus' of git://git.linaro.org/landing-teams/working/fujitsu/integration
Pull mailbox framework from Jassi Brar:
 "A framework for Mailbox controllers and clients have been cooking for
  more than a year now.

  Everybody in the CC list had been copied on patchset revisions and
  most of them have made sounds of approval, though just one concrete
  Reviewed-by.  The patchset has also been in linux-next for a couple of
  weeks now and no conflict has been reported.  The framework has the
  backing of at least 5 platforms, though I can't say if/when they
  upstream their drivers (some businesses have 'changed')"

(Further acked-by by Arnd Bergmann and Suman Anna in the pull request
thread)

* 'mailbox-for-linus' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  dt: mailbox: add generic bindings
  doc: add documentation for mailbox framework
  mailbox: Introduce framework for mailbox
  mailbox: rename pl320-ipc specific mailbox.h
2014-10-21 11:21:19 -07:00
Maxime Ripard
2c4791cdfa ARM: sun8i: q8h: Relicense the device tree under GPLv2/X11
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
2014-10-21 19:32:38 +02:00
Maxime Ripard
438989faa1 ARM: sun7i: i12: Relicense the device tree under GPLv2/X11
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Carlo Caione <carlo@caione.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-10-21 19:31:19 +02:00
Maxime Ripard
37ab5ab8ff ARM: sun6i: m9: Relicense the device tree under GPLv2/X11
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-10-21 19:30:03 +02:00
Maxime Ripard
527ebf02d0 ARM: sun6i: hummingbird: Relicense the device tree under GPLv2/X11
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-21 19:29:27 +02:00
Maxime Ripard
a38e422231 ARM: sun6i: colombus: Relicense the device tree under GPLv2/X11
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-21 19:28:54 +02:00
Maxime Ripard
e321f1a680 ARM: sun5i: olinuxino micro: Relicense the device tree under GPLv2/X11
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-10-21 19:28:22 +02:00
Maxime Ripard
6181a6072b ARM: sun5i: r7: Relicense the device tree under GPLv2/X11
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-10-21 19:26:09 +02:00
Maxime Ripard
bc4c63c320 ARM: sun5i: olinuxino micro: Relicense the device tree under GPLv2/X11
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-10-21 19:24:13 +02:00
Maxime Ripard
74e79cd5b3 ARM: sun4i: olinuxino lime: Relicense the device tree under GPLv2/X11
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Carlo Caione <carlo@caione.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-10-21 19:22:08 +02:00
Maxime Ripard
b0946ca329 ARM: sun4i: mini xplus: Relicense the device tree under GPLv2/X11
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Carlo Caione <carlo@caione.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-10-21 19:20:07 +02:00
Maxime Ripard
4684f7db57 ARM: sun4i: inet97fv2: Relicense the device tree under GPLv2/X11
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Carlo Caione <carlo@caione.org>
Acked-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-10-21 19:18:20 +02:00
Maxime Ripard
a762e59965 ARM: sun4i: hackberry: Relicense the device tree under GPLv2/X11
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Carlo Caione <carlo@caione.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-10-21 19:17:38 +02:00
Maxime Ripard
27f38a77c0 ARM: sun4i: ba10: Relicense the device tree under GPLv2/X11
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-10-21 19:17:20 +02:00
Maxime Ripard
12bfa2854f ARM: sunxi: regulators: Relicense the device tree under GPLv2/X11
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.

In order to make it easier for them to reuse our device trees, relicense our
device trees under a GPL/X11 dual-license.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-10-21 19:15:54 +02:00
Robert Richter
6f889d8ba1 dts, arm: Remove $(MACHINE) variable from dtbs make recipes
The machine description is not needed to build dtb files.

Signed-off-by: Robert Richter <rrichter@cavium.com>
2014-10-21 18:07:00 +02:00
Robert Richter
ca5b34100c dts, arm64: Move dts files to vendor subdirs
Moving dts files to vendor subdirs.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Robert Richter <rrichter@cavium.com>
2014-10-21 18:06:59 +02:00
Robert Richter
323a028d39 dts, kbuild: Implement support for dtb vendor subdirs
This patch adds support of vendor sub directories for dtb files.
Subdirectories can be specified in $(dts-dirs). Kbuild traverses over
all directories while building and installing dtb files. The directory
tree is also reflected in the install path.

Tested-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Robert Richter <rrichter@cavium.com>
2014-10-21 18:06:59 +02:00