The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense our
DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
The current GPL only licensing on the DTSI makes it very impractical for other
software components licensed under another license.
In order to make it easier for them to reuse our device trees, relicense our
DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Carlo Caione <carlo@caione.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Pull kvm fixes from Paolo Bonzini:
"A smattering of bug fixes across most architectures"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
powerpc/kvm/cma: Fix panic introduces by signed shift operation
KVM: s390/mm: Fix guest storage key corruption in ptep_set_access_flags
KVM: s390/mm: Fix storage key corruption during swapping
arm/arm64: KVM: Complete WFI/WFE instructions
ARM/ARM64: KVM: Nuke Hyp-mode tlbs before enabling MMU
KVM: s390/mm: try a cow on read only pages for key ops
KVM: s390: Fix user triggerable bug in dead code
Merge "single Integrator patch" from Linus Walleij:
This sets up the dynamically detected IM-PD1 GPIO lines
by way of GPIO descriptors, avoiding any use of the GPIO
global numberspace.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'integrator-for-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: integrator: add MMCI device to IM-PD1
Pull "First batch of AT91 defconfig update for 3.18" from Nicolas Ferre:
- a dependency needed for SPI flash
- enable sound on DT platforms
- cleanup of current defconfigs:
- addition of new PWM subsystem and related drivers
- addition of ADC/touchscreen, watchdog or USB depending on the SoC
- addition of power/reset drivers activated during this development cycle
- removal of obsolete config options
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'at91-defconfig' of git://github.com/at91linux/linux-at91:
ARM: at91: sama5: update defconfig
ARM: at91: at91sam9rl: update defconfig
ARM: at91: at91sam9g45: update defconfig
ARM: at91: at91sam9263: update defconfig
ARM: at91: at91sam9261_9g10: update defconfig
ARM: at91: at91sam9260_9g20: update defconfig
ARM: at91: at91_dt: update defconfig
ARM: at91/sama5_defconfig: enable sound support
ARM: at91/at91_dt_defconfig: enable sound support
ARM: at91: add MTD_SPI_NOR (new dependency for M25P80)
Merge "at91: fixes for 3.17 #1" from Nicols Ferre:
First AT91 fixes batch for 3.17:
- compatibility string precision
- clock registration and USB DT fix for at91rm9200
* tag 'at91-fixes' of git://github.com/at91linux/linux-at91:
ARM: at91/dt: rm9200: fix usb clock definition
ARM: at91: rm9200: fix clock registration
ARM: at91/dt: sam9g20: set at91sam9g20 pllb driver
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Pull "Second batch of AT91 DT patches for 3.18" from Nicolas Ferre:
- 2 little fixes for at91sam9x5 and at91sam9n12ek
- removal of a board specific hook for sama5d3xek about phy fixup
replaced with proper DT property definition.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'at91-dt2' of git://github.com/at91linux/linux-at91:
ARM: at91: remove phy fixup for sama5d3xek boards
ARM: at91/dt: describe rgmii ethernet phy connected to sama5d3xek boards
ARM: at91/dt: sam9n12ek: ohci: add port and vbus property
ARM: at91/dt: sam9x5: fix ADC compatible string
Merge "First batch of AT91 drivers for 3.18" from Nicolas Ferre:
- reset, poweroff and ram drivers are moved to their proper
location instead of being in mach-at91 directory. They now use
the appropriate frameworks.
- big amount of removal of these machine specific drivers and use
of the newly created drivers. This lead to an overhaul of the setup.c AT91
startup code.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'at91-drivers' of git://github.com/at91linux/linux-at91: (31 commits)
power: reset: at91-poweroff: fix wakeup status register index
ARM: at91/power/reset: fix Kconfig "depends on" directive
ARM: at91: fix ramc standby function registration
ARM: at91: Remove rstc and shdwc headers
ARM: at91: Remove rstc and shdwnc global base addresses
ARM: at91/pm: Remove show_reset_status function
ARM: at91: Remove poweroff code
ARM: at91: Register the poweroff driver
ARM: at91: Remove poweroff DT probing
ARM: at91: Remove reset code from the machine code
ARM: at91: Call at91_register_devices in the board files
ARM: at91: Probe the reset driver
ARM: at91/soc: Introduce register_devices callback
ARM: at91: Remove the old-style reset probing
ARM: at91: Rework ramc mapping code
ARM: at91: setup: Switch to pr_fmt
ARM: at91: remove old irq material
ARM: at91: make use of the new AIC driver for dt enabled boards
ARM: at91: enclose at91_aic_xx calls in IS_ENABLED(CONFIG_OLD_IRQ_AT91) blocks
ARM: at91: introduce OLD_IRQ_AT91 Kconfig option
...
Merge "First batch of AT91 DT material for 3.18" from Nicolas Ferre:
- RAM controller rework for multiple controller SoCs
- shutdown controller addtion
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'at91-dt' of git://github.com/at91linux/linux-at91:
ARM: at91/dt: sama5d3: Add shutdown controller
ARM: at91/dt: Declare a second ram controller when relevant
ARM: at91/dt: at91sam9: use ddrck in ramc
ARM: at91/dt: sama5d3: define mpddr clock and ramc clocks
Merge "at91: cleanup for 3.18" from Nicolas Ferre:
First batch of AT91 cleanup for 3.18:
Following the merge of AIC/AIC5 code as standard irqchip drivers during early
3.17 merge window, we can use these drivers for AT91 DT-enabled chips and
boards.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'at91-cleanup' of git://github.com/at91linux/linux-at91:
ARM: at91: remove old irq material
ARM: at91: make use of the new AIC driver for dt enabled boards
ARM: at91: enclose at91_aic_xx calls in IS_ENABLED(CONFIG_OLD_IRQ_AT91) blocks
ARM: at91: introduce OLD_IRQ_AT91 Kconfig option
With eBPF getting more extended and exposure to user space is on it's way,
hardening the memory range the interpreter uses to steer its command flow
seems appropriate. This patch moves the to be interpreted bytecode to
read-only pages.
In case we execute a corrupted BPF interpreter image for some reason e.g.
caused by an attacker which got past a verifier stage, it would not only
provide arbitrary read/write memory access but arbitrary function calls
as well. After setting up the BPF interpreter image, its contents do not
change until destruction time, thus we can setup the image on immutable
made pages in order to mitigate modifications to that code. The idea
is derived from commit 314beb9bca ("x86: bpf_jit_comp: secure bpf jit
against spraying attacks").
This is possible because bpf_prog is not part of sk_filter anymore.
After setup bpf_prog cannot be altered during its life-time. This prevents
any modifications to the entire bpf_prog structure (incl. function/JIT
image pointer).
Every eBPF program (including classic BPF that are migrated) have to call
bpf_prog_select_runtime() to select either interpreter or a JIT image
as a last setup step, and they all are being freed via bpf_prog_free(),
including non-JIT. Therefore, we can easily integrate this into the
eBPF life-time, plus since we directly allocate a bpf_prog, we have no
performance penalty.
Tested with seccomp and test_bpf testsuite in JIT/non-JIT mode and manual
inspection of kernel_page_tables. Brad Spengler proposed the same idea
via Twitter during development of this patch.
Joint work with Hannes Frederic Sowa.
Suggested-by: Brad Spengler <spender@grsecurity.net>
Signed-off-by: Daniel Borkmann <dborkman@redhat.com>
Signed-off-by: Hannes Frederic Sowa <hannes@stressinduktion.org>
Cc: Alexei Starovoitov <ast@plumgrid.com>
Cc: Kees Cook <keescook@chromium.org>
Acked-by: Alexei Starovoitov <ast@plumgrid.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The defined mechanism for programming the Tegra pinmux is to perform all
of the following at once in order, before using any I/O controller that
is affected by the pinmux:
- Set the CLAMP_INPUTS_WHEN_TRISTATED PMC register bit.
- Set up any GPIO pins to their "initial" state.
- Program all pinmux settings in one go.
Other methods such as:
- Not setting CLAMP_INPUTS_WHEN_TRISTATED.
- Not setting GPIOs to their "initial" state before programming the
pinmux settings of the related pin, in particular the mux function.
- Not programming the entire pinmux at once, in order to avoid
possible conflicting settings.
... are not qualified or supported by NVIDIA ASIC/syseng. They could
cause glitches or undesired output levels on some pins, or controller
malfunction.
While we've been getting away with doing something different on many
Tegra boards without issue, I believe we've just been getting lucky.
I'd like to switch all Tegra124 systems to the correct scheme now so
they provide the right example to follow, and require that any new
boards we support upstream work in the same fashion.
While it would be nice to update boards containing older SoCs for
consistency, I don't anticipate doing so. It's too much churn to change
at this time. At least with all Tegra124 boards converted, the most
recent boards provide the correct example.
Since the bootloader needs to reprogram the pinmux to access certain
peripherals, it must program the entire pinmux due to the supported
rules above. As such, there is no need to program any part of the pinmux
from the kernel, unless dynamic pinmuxing is used. Given this, we couuld
simply remove the pinmux "default" state from the DT entirely. However,
some bootloaders parse the DT to perform their initial pinmux setup, so
it's useful to keep the pinmux data in DT. To allow this while avoiding
redundant work in the kernel, rename the "default" state to "boot". The
kernel won't apply this, but bootloaders can still look for this state
name and apply it. Note however that the DT provides zero information
about the required initial GPIO setup, so bootloaders using this approach
are not likely to operate correctly without an additional GPIO
initialization table somewhere. Previous discussions on the DT mailing
list have rejected adding such a table to DT...
The following U-Boot commits fully initialize the pinmux:
Jetson TK1: 4ff213b8e478 ARM: tegra: clamp inputs on Jetson TK1
Venice2: 3365479ce78a ARM: tegra: Venice2 pinmux spreadsheet updates
Both are part of U-Boot v2014.07 and later.
Without those commits, the only fallout I see from this change is that
HDMI on Venice2 no longer works. Given the very small user-base of this
platform, I feel that requiring a bootloader update is reasonable.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The Acer Chromebook 13, codenamed Big, contains an NVIDIA tegra124
processor and is similar to the Venice2 reference platform.
The keyboard, USB 2, audio, sdcard and emmc have been tested
and work on the 1366x768 models. The Full HD models haven't been
tested yet.
WiFi does not yet work, it needs at least some PMIC changes to enable
the 32k clock.
The elan trackpad is not yet functional but hopefully will be soon as
there are patches under review.
There is also an issue on reboot because the TPM isn't reset. It will
cause the stock firmware to enter recovery mode. This can be worked
around by an EC-reset, press the refresh and power keys at the same
time.
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
These labels will be used by other boards in addition to Venice2, move
them to tegra124.dtsi so they are defined in a common place.
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Pull m68k updates from Geert Uytterhoeven:
"Wire up new syscalls getrandom and memfd_create"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k:
m68k: Wire up memfd_create
m68k: Wire up getrandom
Merge "Renesas ARM Based SoC DT Timers Updates for v3.18" from Simon Horman:
* Enable timers using DT when booting boards without Legacy-C code
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-dt-timers-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: genmai-reference: Enable MTU2 in device tree
ARM: shmobile: r7s72100: Add MTU2 device to DT
ARM: shmobile: marzen-reference: Enable TMU0 in device tree
ARM: shmobile: koelsch-reference: Enable CMT0 in device tree
ARM: shmobile: lager-reference: Enable CMT0 in device tree
ARM: shmobile: r8a7779: Add TMU devices to DT
ARM: shmobile: r8a7791: Add CMT devices to DT
ARM: shmobile: r8a7790: Add CMT devices to DT
Conflicts:
arch/arm/mach-shmobile/setup-r8a7779.c
Merge "Renesas ARM Based SoC R8a7740 CCF and Timers Updates for v3.18" from Simon Horman:
When booting using the r8a7740/armadillo800eva using dt-reference:
* Use CCF to initialise clocks via DT
* Initialise timers via DT
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-r8a7740-ccf-and-timers-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7740: Remove r8a7740_add_standard_devices_dt
ARM: shmobile: armadillo800eva-reference: Do not use r8a7740_add_standard_devices_dt()
ARM: shmobile: armadillo800eva-reference: Enable CMT1 in device tree
ARM: shmobile: r8a7740: Add CMT1 device to DT
ARM: shmobile: armadillo800eva-reference: add clock overrides to DTS
ARM: shmobile: r8a7740: add MSTP clock assignments to DT
ARM: shmobile: r8a7740: add SoC clocks to DTS
ARM: shmobile: r8a7740: clock register bits
The atmel,clk-divisors property is taking 4 divisors, if less are
provided, the clock registration will fail.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Actually register clocks from device tree when using the common clock
framework.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[nicolas.ferre@atmel.com: add at91 to function name]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Merge "Second Round Of Renesas ARM Based SoC Updates For v3.18" from Simon Horman:
* Move legacy INTC definitions from irqs.h to intc.h
* Remove duplicate CPUFreq bits on r8a73a0/ape6evm
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-soc2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Move legacy INTC definitions from irqs.h to intc.h
ARM: shmobile: ape6evm: Remove duplicate CPUFreq bits
ARM: shmobile: sh73a0: Remove duplicate CPUFreq bits
Merge "Renesas ARM Based SoC Init Delay Updates For v3.18" from Simon Horman:
* Use shmobile_init_delay across a wider range of SoCs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-init-delay-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: kzm9g: Use shmobile_init_delay()
ARM: shmobile: bockw: Use shmobile_init_delay()
ARM: shmobile: r8a7778: Use shmobile_init_delay()
ARM: shmobile: sh73a0: Use shmobile_init_delay()
ARM: shmobile: Remove shmobile_setup_delay()
ARM: shmobile: r8a73a4: Use shmobile_init_delay()
ARM: shmobile: sh7372: Use shmobile_init_delay()
ARM: shmobile: r8a7778: Update DTS to include CPU frequency
ARM: shmobile: sh73a0: Update DTS to include CPU frequency
ARM: shmobile: sh7372: Update DTS to include CPU frequency
ARM: shmobile: kzm9g-reference: Remove unneeded nr_irqs initialization
ARM: shmobile: kzm9g: Remove unneeded nr_irqs initialization
ARM: shmobile: marzen: Remove NR_IRQS_LEGACY
ARM: shmobile: ape6evm: Use shmobile_init_delay()
ARM: shmobile: ape6evm: Add shmobile_init_late()
ARM: shmobile: bockw: Add shmobile_init_late()
ARM: shmobile: marzen: Add shmobile_init_late()
ARM: shmobile: kzm9g: Add shmobile_init_late()
Merge "omap fixes against v3.17-rc3" from Tony Lindgren:
Few fixes for omaps mostly for various devices to get them working
properly on the new am437x and dra7 hardware for several devices
such as I2C, NAND, DDR3 and USB. There's also a clock fix for omap3.
And also included are two minor cosmetic fixes that are not
stictly fixes for the new hardware support added recently to
downgrade a GPMC warning into a debug statement, and fix the
confusing comments for dra7-evm spi1 mux.
Note that these are all .dts changes except for a GPMC change.
* tag 'omap-fixes-against-v3.17-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (255 commits)
ARM: dts: dra7-evm: Add vtt regulator support
ARM: dts: dra7-evm: Fix spi1 mux documentation
ARM: dts: am43x-epos-evm: Disable QSPI to prevent conflict with GPMC-NAND
ARM: OMAP2+: gpmc: Don't complain if wait pin is used without r/w monitoring
ARM: dts: am43xx-epos-evm: Don't use read/write wait monitoring
ARM: dts: am437x-gp-evm: Don't use read/write wait monitoring
ARM: dts: am437x-gp-evm: Use BCH16 ECC scheme instead of BCH8
ARM: dts: am43x-epos-evm: Use BCH16 ECC scheme instead of BCH8
ARM: dts: am4372: fix USB regs size
ARM: dts: am437x-gp: switch i2c0 to 100KHz
ARM: dts: dra7-evm: Fix 8th NAND partition's name
ARM: dts: dra7-evm: Fix i2c3 pinmux and frequency
Linux 3.17-rc3
...
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Pull "Renesas ARM Based SoC Defconfig Updates for v3.18" from Simon Horman:
Third Round of Renesas ARM Based SoC Defconfig Updates for v3.18
* Enable Armadillo 800 EVA board in multiplatform defconfig
Second Round Of Renesas ARM Based SoC Defconfig Updates For v3.18
* Do not disable SUSPEND in Bockw defconfig
- Suspend to ram is now supported
Renesas ARM Based SoC Defconfig Updates for v3.18
* Enable initrd in shmobile defconfig
* Enable missing hardware support in shmobile and several board defconfigs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-defconfig3-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Enable Armadillo 800 EVA board in multiplatform defconfig
ARM: shmobile: bockw: Do not disable SUSPEND in defconfig
ARM: shmobile: defconfig: enable initrd
ARM: shmobile: marzen_defconfig: Enable missing hardware support
ARM: shmobile: lager_defconfig: Enable missing hardware support
ARM: shmobile: kzm9g_defconfig: Enable missing hardware support
ARM: shmobile: koelsch_defconfig: Enable missing hardware support
ARM: shmobile: bockw_defconfig: Enable missing hardware support
ARM: shmobile: ape6evm_defconfig: Enable missing hardware support
ARM: shmobile: shmobile_defconfig: Enable missing hardware support
Pull "Renesas ARM Based SoC Kconfig Cleanups for v3.18" from Simon Horman:
* Update name of "R-Car M2-W" SoC (previously there was no "-W")
* Consolidate Legacy SH_CLK_CPG and CPU_V7 Kconfig
* Only select PM_RMOBILE for legacy case
* Cleanup pm-rcar.o and pm-rmobile.o build using Kconfig
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-kconfig-cleanups-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7791 is now called "R-Car M2-W"
ARM: shmobile: Consolidate Legacy SH_CLK_CPG Kconfig
ARM: shmobile: Consolidate Legacy CPU_V7 Kconfig
ARM: shmobile: Only select PM_RMOBILE for legacy case
ARM: shmobile: Cleanup pm-rmobile.o build using Kconfig
ARM: shmobile: Cleanup pm-rcar.o build using Kconfig
ARM: shmobile: Introduce a Kconfig entry for R-Car Gen2
ARM: shmobile: Introduce a Kconfig entry for R-Car Gen1
ARM: shmobile: Introduce a Kconfig entry for R-Mobile
Includes an update to 3.17-rc2 to avoid a dependency
Merge "Third Round of Renesas ARM Based SoC DT Updates for v3.18" from Simon Horman:
* Use tabs for indentation in kzm9g-reference and r8a7779 DTS(I) files
* Add platform device tree bindings documentation
* Add SoC-specific thermal compatible property to r8a73a4 and r8a7779
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-dt3-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: kzm9g-reference dts: Use tabs for indentation
ARM: shmobile: r8a7779 dtsi: Use tabs for indentation
ARM: shmobile: Add platform device tree bindings documentation
ARM: shmobile: r8a73a4 dtsi: Add SoC-specific thermal compatible property
ARM: shmobile: r8a7779 dtsi: Add SoC-specific thermal compatible property
The Kconfig symbol PLAT_SPEAR_SINGLE briefly appeared during the v3.10
development cycle. It was removed in a merge commit before v3.10. A few
references to it were left in the tree, probably because they didn't
generate merge conflicts. Whatever it was, they're useless now and can
safely be removed.
Reported-by: Martin Walch <walch.martin@web.de>
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Reviewed-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Cc: Rajeev Kumar <rajeev_kumar@mentor.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Currently, if a permission error happens during the translation of
the final GPA to HPA, walk_addr_generic returns 0 but does not fill
in walker->fault. To avoid this, add an x86_exception* argument
to the translate_gpa function, and let it fill in walker->fault.
The nested_page_fault field will be true, since the walk_mmu is the
nested_mmu and translate_gpu instead operates on the "outer" (NPT)
instance.
Reported-by: Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
If a nested page fault happens during emulation, we will inject a vmexit,
not a page fault. However because writeback happens after the injection,
we will write ctxt->eip from L2 into the L1 EIP. We do not write back
if an instruction caused an interception vmexit---do the same for page
faults.
Suggested-by: Gleb Natapov <gleb@kernel.org>
Reviewed-by: Gleb Natapov <gleb@kernel.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
The SAMA5 and SAM9x5 series both have drive strength
options for the PIOs. This patch adds the ability to set
one of three hardware options for drive strengths of low,
medium or high for the each pin. The actual current output
of the chip based on the setting is defined in the datasheets
and varies per pins separate from banks and with supply
voltage.
This patch adds three new dt-bindings that allow setting the
strength when configuring pins. By default, no change will
be made to the drive strength of a pin from its reset value.
Due to the difference between the register addresses of the
SAMA5 and SAM9x5 series, a new sama5d3-pinctrl id was added.
Signed-off-by: Marek Roszko <mark.roszko@gmail.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Branching takes two cycles on MPC8xx. Lets duplicate the two instructions
and avoid the branching.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
By XORing the upper part of the instruction code, we get a value that can
directly be verified with the second test and we can remove the first test.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
r10 and r3 are only used inside FixupDAR function. So lets save them inside
that function only.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Since commit 2321f33790, r10 is not used anymore
after FixupDAR. There is therefore no need to set it up with the value of DAR.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
SCRATCH0 and SCRATCH1 are only used in Exceptions prologs where no other
exception can happen. There is therefore no need to preserve them accross
TLB handlers, we can use them there as in other exceptions. One of the
advantages is that they do not suffer CPU6 errata unlike M_TW register.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Since commit 469d62be92, SPRG2 is used as a
scratch register just like SPRG0 and SPRG1. So Declare it as such and fix
the comment which is not valid anymore since that commit.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Allocate msis such that each time a new interrupt is requested,
the SRS (MSIR register select) to be used is allocated in a
round-robin fashion.
The end result is that the msi interrupts will be spread across
distinct MSIRs with the main benefit that now users can set
affinity to each msi int through the mpic irq backing up the
MSIR register.
This is achieved with the help of a newly introduced msi bitmap
api that allows specifying the starting point when searching
for a free msi interrupt.
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Mihai Caraman <mihai.caraman@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Rename the irq controller associated with a MSI
interrupt to fsl-msi-<V>, where <V> is the virq
of the cascade irq backing up this MSI interrupt.
This way, one can set the affinity of a MSI
through the cascade irq associated with said MSI
interrupt.
Given this example /proc/interrupts snippet:
CPU0 CPU1 CPU2 CPU3
16: 0 0 0 0 OpenPIC 16 Edge mpic-error-int
17: 0 4 0 0 fsl-msi-224 0 Edge eth0-rx-0
18: 0 5 0 0 fsl-msi-225 1 Edge eth0-tx-0
19: 0 2 0 0 fsl-msi-226 2 Edge eth0
[...]
224: 0 11 0 0 OpenPIC 224 Edge fsl-msi-cascade
225: 0 0 0 0 OpenPIC 225 Edge fsl-msi-cascade
226: 0 0 0 0 OpenPIC 226 Edge fsl-msi-cascade
[...]
To change the affinity of MSI interrupt 17
(having the irq controller named "fsl-msi-224")
instead of writing /proc/irq/17/smp_affinity, use
the associated MSI cascade irq, in this case,
interrupt 224, e.g.:
echo 6 > /proc/irq/224/smp_affinity
Note that a MSI cascade irq covers several MSI
interrupts, so changing the affinity on the
cascade will impact all of the associated MSI
interrupts.
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Mihai Caraman <mihai.caraman@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
