Merge "Second Round of Renesas ARM Based SoC CPUFreq Updates for v3.17" from
Simon Horman:
- Remove opps table check for cpufreq as this is already handled
by the driver
* tag 'renesas-cpufreq2-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Remove opps table check for cpufreq
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Ux500 core changes for v3.17 take 1" from Linus Walleij:
Some minor cleanups to the Ux500 core. DT-only probe path and
some constification from static code analysis.
* tag 'ux500-core-for-v3.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: remove pointless cache setup complexity
ARM: ux500: storage class should be before const qualifier
ARM: ux500: Staticize ab8505_regulators
ARM: ux500: Staticize local symbols in cpu-db8500.c
ARM: ux500: Staticise ux500_soc_attr
+ Linux 3.16-rc4
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Ux500 devicetree changes for v3.17" from Linus Walleij:
Ux500 device tree patches for v3.17:
- Add regulators to STMPE expanders
- Add proper DMA channels for all SD/MMC blocks
- Add sensors to the device tree
* tag 'ux500-devicetree-v3.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: add misc sensors to the device trees
ARM: ux500: add some DB8500 DMA channel info
ARM: ux500: add VCC and VIO regulators to STMPE IC
+ Linux 3.16-rc4
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Third Round of Renesas ARM Based SoC Updates for v3.17" from Simon
Horman:
- Correct build failure in APMU code in the case of !SUSPEND
* tag 'renesas-soc3-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: fix shmobile_smp_apmu_suspend_init build failure for !SUSPEND
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Samsung cleanup 2nd version for S5P SoCs for 3.17" from Kukjin Kim:
Cleanup S5P SoCs for 3.17
- removing s5p64x0 SoCs and s5pc100 SoC in mainline because
no more user and if it is required next time, it will be
supported with DT.
* tag 's5p-cleanup-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
video: fbdev: s3c-fb: remove s5pc100 related fimd and fb codes
mtd: onenand: remove s5pc100 related onenand codes
spi: s3c64xx: remove s5pc100 related spi codes
gpio: samsung: remov s5pc100 related gpio codes
ARM: S5PC100: no more support S5PC100 SoC
video: fbdev: s3c-fb: remove s5p64x0 related fimd codes
spi: s3c64xx: remove s5p64x0 related spi codes
gpio: samsung: remove s5p64x0 related gpio codes
ARM: S5P64X0: no more support S5P6440 and S5P6450 SoCs
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Samsung fixes-3 for 3.16" from Kukjin Kim:
Samsung fixes-3 for v3.16
- update the parent for Auudss clock because kernel will be hang
during late boot if the parent clock is disabled in bootloader.
- enable clk handing in power domain because while power domain
on/off, its regarding clock source will be reset and it causes
a problem so need to handle it.
- add mux clocks to be used by power domain for exynos5420-mfc
during power domain on/off and property in device tree also.
- register cpuidle only for exynos4210 and exynos5250 because a
system failure will be happened on other exynos SoCs.
* tag 'samsung-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Register cpuidle device only on exynos4210 and 5250
ARM: dts: Add clock property for mfc_pd in exynos5420
clk: exynos5420: Add IDs for clocks used in PD mfc
ARM: EXYNOS: Add support for clock handling in power domain
ARM: dts: Update the parent for Audss clocks in Exynos5420
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch removes supporting codes for s5pc100 because no more used
now.
[jason@lakedaemon.net: for drivers/irqchip/Kconfig]
Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
In order to remove the following ugly message:
BUG: mapping for 0x00000000 at 0xff000000 out of vmalloc space
the iotable mappings should be re-located inside the vmalloc
region. Such move was introduced at commit:
commit 0536bdf33f
Author: Nicolas Pitre <nicolas.pitre@linaro.org>
Date: Thu Aug 25 00:35:59 2011 -0400
ARM: move iotable mappings within the vmalloc region
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
[laurent.pinchart@ideasonboard.com: Hardcode the virtual address]
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
The IMEMC mapping not only has no user, but maps a reserved memory
space. It just wastes vmalloc space, remove it.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
The UNCACHED_PHYS_0 mapping is only needed on PXA25x and PXA27x
platforms. Move it to pxa25x.c and pxa27x.c to avoid wasting vmalloc
space on PXA3xx.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
The virtual address, physical address and size of all regions for which
we create static mappings are defined in PXA headers. Replaced the
hardcoded values with macros.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "pxa for v3.17 v2" from Haojian Zhuang:
* tag 'pxa-for-v3.17-2' of https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux:
ARM: pxa: fix typo 'CONFIG_SPI_PXA2XX_MASTER'
ARM: pxa: call debug_ll_io_init for earlyprintk
ARM: pxa: correct errata number for PXA270
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Second Round of Renesas ARM Based SoC Updates for v3.17" from Simon
Horman:
* Suspend on non-SMP update for r8a7790
* Move r8a7791.h out of mach directory.
This is part of a multi-stage effort to move headers
out of that directory.
* tag 'renesas-soc2-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Allow r8a7791 to build non-SMP APMU code
ARM: shmobile: Move r8a7791 reset code to pm-r8a7791.c
ARM: shmobile: Allow r8a7790 to build non-SMP APMU code
ARM: shmobile: Move r8a7790 reset code to pm-r8a7790.c
ARM: shmobile: Use __init for APMU suspend init function
ARM: shmobile: Adjust APMU code to build for non-SMP
ARM: shmobile: Allow use of boot code for non-SMP case
ARM: shmobile: Move r8a7791.h
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Second Round of Renesas ARM Based SoC soc-cleanup Updates for v3.17"
from Simon Horman:
* Move SOC-specific headers out of mach directory.
This is part of a multi-stage effort to move headers
out of that directory.
* tag 'renesas-soc-cleanup2-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Move sh7372.h
ARM: shmobile: Move sh73a0.h
ARM: shmobile: Move r8a7790.h
ARM: shmobile: Move r8a7778.h
ARM: shmobile: Move r8a7740.h
ARM: shmobile: Move r8a73a4.h
ARM: shmobile: Move r7s72100.h
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Second Round of Renesas ARM Based SoC r8a7779-multiplatform
Updates for v3.17" from Simon Horman:
- Move r8a7779.h out of mach directory.
This is part of a multi-stage effort to move headers
out of that directory.
* tag 'renesas-r8a7779-multiplatform2-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Move r8a7779.h
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Second Round of Renesas ARM Based SoC DT Updates for v3.17" from Simon
Horman:
- Extend hardware coverage
* Add DVC support for sound nodes on r8a7791 and r8a7790
* Enable internal PCI on r8a7790/lager
* tag 'renesas-dt2-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7791: add DVC support for sound node on DTSI
ARM: shmobile: r8a7790: add DVC support for sound node on DTSI
ARM: shmobile: lager: enable internal PCI
ARM: shmobile: r8a7790: add internal PCI bridge nodes
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Second Round of Renesas ARM Based SoC Defconfig Updates for v3.17" from
Simon Horman:
* Enable genmai board in multiplatform defconfig
* tag 'renesas-defconfig2-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Enable genmai board in multiplatform defconfig
Signed-off-by: Olof Johansson <olof@lixom.net>
This describes all of the SCIF hardware of the sh73a0.
Each node is disabled and may be enabled as necessary
by board DTS files.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This describes all of the SCIF hardware of the r8a7740.
Each node is disabled and may be enabled as necessary
by board DTS files.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This describes all of the SCIF hardware of the r8a73a4.
Each node is disabled and may be enabled as necessary
by board DTS files.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This describes all of the SCIF hardware of the r8a7778.
Each node is disabled and may be enabled as necessary
by board DTS files.
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This will be used when initialising SCI devices using DT
until common clock framework support is added.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
When initialising SCI devices their names will be .serial
not .sci.
This will be used when initialising SCI devices using DT
until common clock framework support is added.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This will be used when initialising SCI devices using DT
until common clock framework support is added.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
GPMC controller supports up to 8 memory devices connected to it.
Since there is one statically allocated "struct platform_device
gpmc_nand_device" it is not possible to configure the system to
use more than one NAND device connected to the GPMC. This
modification makes it possible to use up to 8 NAND devices
connected to the GPMC controller.
Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
Signed-off-by: Roger Quadros <rogerq@ti.com>
The PINCTRL_SUNXI configuration was kept only to deal with the introduction of
per-machine symbols and the various pintrl drivers through different tree.
Now that it's not useful anymore, we can just remove it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Pads for PB0-PB3, PC0-PC4, PE26-PE31 and PF24-PF31 does not exist on
the i.MX27 SOC. There is no reason to define them, the presence of
such definitions in the DTS files is a bug.
This patch removes these nonexistent pad definitions.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix code that handles KVM_SET_ONE_REG, KVM_GET_ONE_REG ioctls to work in BE
image. Before this fix get/set_one_reg functions worked correctly only in
LE case - reg_from_user was taking 'void *' kernel address that actually could
be target/source memory of either 4 bytes size or 8 bytes size, and code copied
from/to user memory that could hold either 4 bytes register, 8 byte register
or pair of 4 bytes registers.
In order to work in endian agnostic way reg_from_user to reg_to_user functions
should copy register value only to kernel variable with size that matches
register size. In few place where size mismatch existed fix issue on macro
caller side.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
In some cases the mcrr and mrrc instructions in combination with the ldrd
and strd instructions need to deal with 64bit value in memory. The ldrd
and strd instructions already handle endianness within word (register)
boundaries but to get effect of the whole 64bit value represented correctly,
rr_lo_hi macro is introduced and is used to swap registers positions when
the mcrr and mrrc instructions are used. That has the effect of swapping
two words.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The vgic h/w registers are little endian; when BE asm code
reads/writes from/to them, it needs to do byteswap after/before.
Byteswap code uses ARM_BE8 wrapper to add swap only if
CONFIG_CPU_BIG_ENDIAN is configured.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Move the GICv2 world switch code into its own file, and add the
necessary indirection to the arm64 switch code.
Also introduce a new type field to the vgic_params structure.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Brutally hack the innocent vgic code, and move the GICv2 specific code
to its own file, using vgic_ops and vgic_params as a way to pass
information between the two blocks.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
For correct guest suspend/resume behaviour we need to ensure we include
the generic timer registers for 64 bit guests. As CONFIG_KVM_ARM_TIMER is
always set for arm64 we don't need to worry about null implementations.
However I have re-jigged the kvm_arm_timer_set/get_reg declarations to
be in the common include/kvm/arm_arch_timer.h headers.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
A userspace process can map device MMIO memory via VFIO or /dev/mem,
e.g., for platform device passthrough support in QEMU.
During early development, we found the PAGE_S2 memory type being used
for MMIO mappings. This patch corrects that by using the more strongly
ordered memory type for device MMIO mappings: PAGE_S2_DEVICE.
Signed-off-by: Kim Phillips <kim.phillips@linaro.org>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
