A stray '0x' crept into a0f7e7496d ("ARM: shmobile: sh73a0: add CMT1
clock support for DT"). This patch removes it.
This change should not have any run-time affect at this time as
the clock in question is used by a SCIF device that is not enabled by
default.
Reported-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit adds the necessary code in the Marvell EBU PMSU driver to
support dynamic frequency scaling. In essence, what this new code does
is that it:
* registers the frequency operating points supported by the CPU;
* registers a clock notifier of the CPU clocks. The notifier function
listens to the newly introduced APPLY_RATE_CHANGE event, and uses
that to finalize the frequency transition by doing the part of the
procedure that involves the PMSU;
* registers a platform device for the cpufreq-generic driver, which
will take care of the CPU frequency transitions.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404920715-19834-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In the Armada XP SMP support code, we are reading the clock frequency
of the booting CPU, and use that to assign the same frequency to the
other CPUs, and we do this while the clocks are disabled.
However, the CPU clocks are in fact never prepared/enabled, and to
support cpufreq, we now have two code paths to change the frequency of
the CPU clocks in the CPU clock driver: one when the clock is enabled
(dynamic frequency scaling), one when the clock is disabled (adjusting
the CPU frequency before starting the CPU). In order for this to work,
the CPU clocks now have to be prepared and enabled after the initial
synchronization of the clock frequencies is done, so that all future
rate changes of the CPU clocks will trigger a dynamic frequency
scaling transition.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404920715-19834-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In order to support dynamic frequency scaling:
* the cpuclk Device Tree node needs to be updated to describe a
second set of registers describing the PMU DFS registers.
* the clock-latency property of the CPUs must be filled, otherwise
the ondemand and conservative cpufreq governors refuse to work. The
latency is high because the cost of a frequency transition is quite
high on those CPUs.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404920715-19834-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The CA9 MPcore SoC Control block is a set of registers that allows to
configure certain internal aspects of the core blocks of the SoC
(Cortex-A9, L2 cache controller, etc.). In most cases, the default
values are fine so they aren't many reasons to touch those registers,
but there is one exception: to support cpuidle on Armada 38x, we need
to modify the value of the CA9 MPcore Reset Control register.
Therefore, this commit adds a new Device Tree binding for this
hardware block, and uses this new binding for the Armada 38x Device
Tree file.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: devicetree@vger.kernel.org
Link: https://lkml.kernel.org/r/1404913221-17343-11-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This is a purge of all things <mach/gpio.h>, now I never
want to see it again.
- Remove the need for <mach/gpio.h> from S5P
- Kill CONFIG_NEED_MACH_GPIO_H
- Kill remnants of ARM_GPIOLIB_COMPLEX
* tag 'gpio-h-purge' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio:
ARM: delete old reference to ARM_GPIOLIB_COMPLEX
ARM: kill CONFIG_NEED_MACH_GPIO_H
ARM: mach-s5p: get rid of all <mach/gpio.h> headers
ARM: s5p: cut the custom ARCH_NR_GPIOS definition
Signed-off-by: Olof Johansson <olof@lixom.net>
Display domain is removed due to instability issues. Explaining
the problem below:
exynos_init_late triggers the pm_genpd_poweroff_unused which powers
off the unused power domains. This call hits before the trigger to
deferred probes.
DRM DP Panel defers the probe due to supply get failure. By the time,
deferred probe is scheduled again, Display Power Domain is powered
off by pm_genpd_poweroff_unused.
FIMD and DP drivers are accessing registers during Probe and Bind
callbacks. If display domain is enabled/disabled around register
accesses, display domain gets unstable and we are getting Power Domain
Disable fail notification. Increasing the Timeout also didn't help.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Instead, copy the used constants from the header file to the source file.
This allows the code to be migrated under drivers folder where we don't
have access to the OMAP specific header files.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Some of the machine specific header includes are no longer used, so remove
these from the source file. This allows migration of the file under clock
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Some of the machine specific header includes are no longer used, so remove
these from the source file. This allows migration of the file under clock
driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Helps to get rid of some runtime cpu_is_x checks. This also allows eventual
migration of the code under clock driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Currently DPLL code uses runtime cpu_is_343x checks to see if the DPLL
has freqsel fields in its control register or not. Instead, add a new
flag to the clk_features.flags and use this during runtime. Allows
eventual move of the DPLL code under clock driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
OMAP2 DPLL code for checking whether DPLL is in bypass mode now uses
clk_features data provided during boot. This avoids the need to use
cpu_is_X type checks runtime, and allows us to eventually move the
clock code under the clock driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Currently, same functionality is copy pasted in two locations. Instead,
add a private API for this and get rid of some duplicated code.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
These are SoC specific and get their init values based on the SoC type.
Previously the values were hard coded within the DPLL clock code, but
having them inside the clock features avoids runtime cpu_is_X type checks.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This shall be used to replace the cpu type checks around the clock code.
Actual bit values will be introduced in patches later.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Instead, copy the used bitfield definitions to the source file. Done in
preparation to migrate the clock implementation under clock driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
These are unnecessary, as the clock code is only used on OMAP4+ platforms
through clock registrations. This also allows to eventually migrate the
clock type implementation under clock driver.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add MAX98090 audio codec, I2S interface and the sound complex
nodes to enable audio on Odroid-X2/U3 boards.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
TFLASH (SDHCI2 controller) uses internal card detect line, but it looks
that the driver fails to operate it properly. Use GPIO interrupt on
SD_CDn line for detecting SD card state.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds support for simple GPIO-based button availabled on
Exynos4 based Odroid boards. All supported boards have POWER button,
which has been defined in exynos4412-odroid-common.dtsi. X/X2 boards
also have additional user-configurable button which has been mapped to
KEY_HOME. All defined keys have been marked as possible wakeup source.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
On Odroid U2/U3 BUCK8 is used for providing power to also to P3V3
source, which is also connected to LAN9730 chip's nRESET signal. To
reset lan chip on system reboot, the BUCK8 output should not be used in
'always on' mode. This change has no impact on X/X2 boards.
Signed-off-by: Kamil Debski <k.debski@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch moves some parts of exynos4412-odroidx.dts to common
exynos4412-odroid-common.dtsi file and adds support for Odroid X2 and
U2/U3 boards. X2 is same as X, but it has faster SoC module (1.7GHz
instead of 1.4GHz), while U2/U3 differs from X2 by different way of
routing signals to host USB hub. It also lacks some hw modules not yet
supported by those dts files (i.e. LCD & touch panel).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Last megabyte of RAM is used by secure firmware and should not be accessed
by Linux kernel, so correct available memory size in DTS file.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds basic support for USB modules (host and device) on
OdroidX board.
Signed-off-by: Kamil Debski <k.debski@samsung.com>
[removed incorrect port@2 node]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds support for common hardware modules available on all
Exynos4412-based Odroid boards, which already have complete support in
mainline kernel. This includes secure firmware calls, watchdog, g2d and
fimc (mem2mem) multimedia accelerators.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds port sub-nodes to exynos4 ehci and ohci modules, which
are required by recently merged new exynos4 usb2 phy support.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from
being reset across sleep/wake. If we don't set it to anything then
the TPM will be reset. U-Boot will detect this as invalid
and will reset the system on resume time. This GPIO can always be low
and not hurt anything. It will get pulled back high again during a
normal warm reset when it will default back to an input.
To properly preserve the TPM state across suspend/resume and to make
the chrome U-Boot happy, properly set the GPIO to mask the
reset to the TPM.
Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The mask-tpm-reset GPIO is used by the kernel to prevent the TPM from
being reset across sleep/wake. If we don't set it to anything then
the TPM will be reset. U-Boot will detect this as invalid
and will reset the system on resume time. This GPIO can always be low
and not hurt anything. It will get pulled back high again during a
normal warm reset when it will default back to an input.
To properly preserve the TPM state across suspend/resume and to make
the chrome U-Boot happy, properly set the GPIO to mask the
reset to the TPM.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The legacy-style definition of the hwmod addr space is no longer
required as AM33xx/AM43xx are DT-boot only, and the minimal mailbox
DT nodes have been added, so clean up this data.
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The legacy-style definition of the hwmod addr space is no longer
required after the addition of the OMAP4 mailbox DT node, so
clean up this data.
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <bcousson@baylibre.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
OMAP2 devices are devicetree boot only, and the legacy mode
of mailbox device creation should no longer be used, so remove
the mailbox attribute data and the hwmod addr space used for
creating mailboxes in legacy mode.
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The legacy platform device for mailbox should not be created for
a DT boot, so adjust the platform device initialization logic
appropriately.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add the hwmod data for the 13 instances of the system mailbox
IP in DRA7 SoC. The patch is needed for performing a soft-reset
while configuring the respective mailbox instance, otherwise is
a non-essential change for functionality. The modules are smart
idled on reset, and the IP module mode is hardware controlled.
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DRA7xx has 13 system mailboxes, and is present on both the
DRA72x and DRA74x family of SoCs. Add the DT nodes for all
these 13 mailboxes. Except for mailbox 1, all other mailboxes
do not have interrupts mapped into the MPU GIC by default.
All the mailboxes have been disabled and the interrupts
property information is left out intentionally for now,
because of the dependencies against the crossbar driver.
These mailboxes can be enabled when a usecase arises
and the crossbar driver dependencies are met.
NOTE: The mailbox 1 has different number of mailbox fifos
and IP interrupts compared to the remaining 12 mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The mailbox DT node for AM4372 is enabled and is corrected to
remove some properties that have crept in by mistake.
Fixes: 9e3269b (ARM: dts: AM4372: Add L2, EDMA, mailbox, MMC and SHAM nodes)
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The mailbox DT node data has been added for AM33xx device.
The mailbox IP in AM33xx is similar to the version found in
OMAP4+ devices.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The mailbox DT node data has been added for OMAP44xx
devices.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The number of mailbox fifos and users (IP interrupts) are added
to the Mailbox DT nodes on OMAP2420, OMAP2430, OMAP3, and OMAP5
family of SoCs through the DT properties "ti,mbox-num-fifos" and
"ti,mbox-num-users" properties. This data represents the same data
that used to be represented in hwmod attribute data through the
.num_fifos and .num_users fields previously.
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
