Merge "i.MX device tree changes for 3.15" from Shawn Guo:
- New SoC device tree support for imx35 and imx50
- A good number of new board support: imx25-eukrea, imx28-duckbill,
imx28-eukrea, Eukrea cpuimx35, imx50-evk, imx51-eukrea, imx53-voipac,
MCIMX53-START-R and Ka-Ro TX53.
- Quite some updates and tweaking on imx27 phycore and apf27dev boards
- Add pinfunc headers for imx25, imx27 and imx50
- Make pinctrl nodes board specific to avoid floating board specific
device tree blob with so many unused pinctrl data
- Use generic node name for fixed regulator
- Use clock defines in imx5 DTS files
- Use macros for interrupt and gpio flags
- A plenty of random updates on various SoC and board device tree
sources, adding pinctrl settings, device nodes, properties, aliases.
* tag 'imx-dt-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6: (89 commits)
ARM: dts: imx28-m28cu3: Remove 'reset-active-high'
ARM: dts: imx5: use imx51-ssi
ARM: dts: imx51: Add mmc aliases
ARM: dts: imx53: Add mmc aliases
ARM: dts: imx53: add support for Ka-Ro TX53 modules
ARM: dts: Add support for the cpuimx35 board from Eukrea and its baseboard.
ARM: dts: imx28-apf28dev: add user button
ARM: dts: i.MX51: Switch to use standard definitions for input subsystem
ARM: dts: i.MX53: add support for MCIMX53-START-R
ARM: dts: i.MX53: move common QSB nodes to new file
ARM: dts: imx53-evk: Remove board support
ARM: dts: vf610: use the interrupt macros
ARM: dts: imx53: Add gpio and input dt includes.
ARM: dts: i.MX27: Add SSI nodes
ARM: dts: mxs: add mxs phy controller id
ARM: dts: imx27-phytec-phycore-rdk: Add pinctrl definitions for WEIM
ARM: dts: imx27-phytec-phycore-rdk: Add pingrp for SDHC
ARM: dts: imx27-phytec-phycore-som: Add spi-cs-high property to PMIC
ARM: dts: imx27-phytec-phycore-rdk: Enable 1-Wire module
ARM: dts: imx27-phytec-phycore-som: Add NFC pin group
...
Merge "i.MX6 device tree changes for 3.15" from Shawn Guo:
- A good number of new i.MX6 boards support: cm-fx6, dmo-edmqmx6,
nitrogen6x, Gateworks Ventana gw5xxx family, DFI FS700-M60 and
Zealz GK802
- Update imx6q-sabrelite device tree and add Dual Lite/Solo support
- Move pins that are used by particular client device out of hog group
- Use GPIO_6 for FEC interrupt to workaround a hardware bug (ERR006687
ENET: Only the ENET wake-up interrupt request can wake the system
from Wait mode.)
- Make pinctrl nodes board specific to avoid floating board specific
device tree blob with so many unused pinctrl data
- Use generic node name for fixed regulator
- Update OPP table for cpufreq support
- Random updates on various board device tree sources, adding pinctrl
settings, device nodes, properties, etc.
* tag 'imx6-dt-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6: (62 commits)
ARM: dts: imx6q: Add support for Zealz GK802
ARM: dts: imx6: Add DFI FS700-M60 board support
ARM: dts: imx6: use imx51-ssi
ARM: dts: imx6qdl: Add mmc aliases
ARM: dts: imx6q: Add spi4 alias
ARM: dts: imx6qdl-sabreauto: Add LVDS support
ARM: dts: imx6sl: add keypad support for i.mx6sl-evk board.
ARM: dts: imx6sl: add ocram device support
ARM: dts: imx6qdl: enable dma for spi
ARM: dts: imx6qdl-sabresd: Add PFUZE100 support
ARM: dts: imx6: add mxs phy controller id
ARM: dts: imx6: add anatop phandle for usbphy
ARM: dts: imx6q-arm2: use GPIO_6 for FEC interrupt.
ARM: dts: imx6qdl-sabreauto: use GPIO_6 for FEC interrupt.
ARM: dts: imx6qdl-sabrelite: use GPIO_6 for FEC interrupt.
ARM: dts: imx6qdl: use interrupts-extended for fec
ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ
ARM: dts: imx6q-sabrelite: PHY reset is active-low
ARM: dts: imx6: Use 'vddarm' as the regulator name
ARM: dts: imx6qdl-sabresd: Add power key support
...
Merge "Renesas ARM Based SoC Updates for v3.15" from Simon Horman:
* r7s72100 SoC (RZ/A1H)
- Add i2c clocks (portion missing from previous patch due to miss-merge)
* r8a7791 (R-Car M2)
- Add SATA clocks
- Add ZS clock
- Wait for status on all MSTP clocks
-- Add I2C and VIN clocks
* r8a7790 (R-Car H2)
- Add PCI USB host clock support
- Add Audio DMAC, SATA and VIN clocks
- Add Audio DMAC support
* r8a7779 (R-Car H1)
- Wait for status on selected MSTP clocks
* tag 'renesas-soc-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7790: Add PCI USB host clock support
ARM: shmobile: r7s72100: really add i2c clocks
ARM: shmobile: r8a7791: Add SATA clocks
ARM: shmobile: r8a7791: Add ZS clock
ARM: shmobile: r8a7790: Add SATA clocks
ARM: shmobile: r8a7790: Add VIN clock support
ARM: shmobile: r8a7790: add Audio DMAC support
ARM: shmobile: r8a7790: add Audio DMAC clock
ARM: shmobile: r8a7791: Wait for status on all MSTP clocks
ARM: shmobile: r8a7791: Add VIN clocks
ARM: shmobile: r8a7791: Add I2C clocks
ARM: shmobile: r8a7790: Wait for status on all MSTP clocks
ARM: shmobile: r8a7779: Wait for status on selected MSTP clocks
ARM: shmobile: wait for MSTP clock status to toggle, when enabling it
Merge "Renesas ARM Based SoC DT Updates for v3.15" from Simon Horman:
* r8a7791 (R-Car M2) based Koelsch board
- Enable GPIO Keys, (1+1)GiB memory, SATA0 and serial ports
- Add VIN and thermal clocks
- Remove r8a7791-koelsch-reference.dts
* r8a7790 (R-Car H2) based Lager board
- Replace IRQ type numerical values with macros
- Enable SATA0 and serial ports
- Add VIN and thermal clocks
* tag 'renesas-dt-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7790: Replace IRQ type numerical values with macros
ARM: shmobile: r8a7790: Fix serial ports DT compatible strings
ARM: shmobile: lager: Enable SATA1 in r8a7790-lager.dts
ARM: shmobile: r8a7790: Add SATA nodes to r8a7790.dtsi
ARM: shmobile: koelsch: Enable SATA0 in r8a7791-koelsch.dts
ARM: shmobile: r8a7791: Add SATA nodes to r8a7791.dtsi
ARM: shmobile: r8a7791: Add SATA clocks to device tree
ARM: shmobile: r8a7790: Add SATA clocks to device tree
ARM: shmobile: r8a7791: Add VIN clocks to device tree
ARM: shmobile: r8a7790: Add VIN clocks to device tree
ARM: shmobile: r8a7790: Add serial ports to the device tree
ARM: shmobile: r8a7791: Add serial ports to the device tree
ARM: shmobile: r8a7790: Add thermal clock in device tree
ARM: shmobile: r8a7791: Add thermal clock in device tree
ARM: shmobile: koelsch: (1+1)GiB memory in DT
ARM: shmobile: Add GPIO keys to Koelsch DTS
ARM: shmobile: dts: Remove r8a7791-koelsch-reference.dts
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Renesas ARM based SoC Defconfig Updates for v3.15" from Simon Horman:
* Renesas ARM based SoC boards (Global)
enable CONFIG_DEVTMPFS in defconfig
* r8a7791 SoC (R-Car M2) based Koelsch board
- Enable SATA
* r8a7790 SoC (R-Car H2) based Lager board
- Enable SATA, VIN and ADV7180 decoder in defconfig
* tag 'renesas-defconfig-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: ape6evm: enable CONFIG_DEVTMPFS in defconfig
ARM: shmobile: armadillo: enable CONFIG_DEVTMPFS in defconfig
ARM: shmobile: bockw: enable CONFIG_DEVTMPFS in defconfig
ARM: shmobile: genmai: enable CONFIG_DEVTMPFS in defconfig
ARM: shmobile: kzm9d: enable CONFIG_DEVTMPFS in defconfig
ARM: shmobile: kzm9g: enable CONFIG_DEVTMPFS in defconfig
ARM: shmobile: lager: enable CONFIG_DEVTMPFS in defconfig
ARM: shmobile: mackerel: enable CONFIG_DEVTMPFS in defconfig
ARM: shmobile: marzen: enable CONFIG_DEVTMPFS in defconfig
ARM: shmobile: lager: Enable SATA in defconfig
ARM: shmobile: koelsch: Enable DEVTMPFS_MOUNT in defconfig
ARM: shmobile: koelsch: Enable SATA in defconfig
ARM: shmobile: lager: Enable VIN along with ADV7180 decoder in defconfig
Signed-off-by: Olof Johansson <olof@lixom.net>
On imx6sl-evk board the VGEN1 regulator powers up the NVCC_1P2V domain of the
imx6sl SoC, so we need to keep it always powered.
According to imx6sl datasheet the GPIO block has three supplies:
NVCC33_IO, NVCC18_IO and NVCC_1P2V and it states that:
"All digital I/O supplies (NVCC_xxxx) must be powered under normal conditions
whether the associated I/O pins are in use or not"
This problem has been observed by the fact that a GPIO connected to an LED could
not work when the PMIC driver was enabled.
Keeping VGEN1 regulator always enabled fixes the problem.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The D9 LED controlled by gpio on the imx6qdl-sabreauto
CPU board is a debug LED according to the board design.
This patch adds the relevant device tree nodes to the
imx6qdl-sabreauto device tree file to support this LED.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Guests can use AMBA bus devices such as the PL011 uart, so enable the
AMBA bus for mach-virt.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Russell King <linux@arm.linux.org.uk>
The mach code for mach-virt is no longer needed, so we can remove all of
mach-virt except the kconfig entry.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
The wm8750 is an ARM1176 which has all the V6K extensions except for SMP,
so V6K should be selected instead. Dropping the select will use the
default for ARCH_MULTI_V6 which is V6K.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Tony Prisk <linux@prisktech.co.nz>
The cns3xxx is an ARM11MPCore which has all the V6K extensions, so V6K
should be selected instead. Dropping the select will use the default for
ARCH_MULTI_V6 which is V6K.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Anton Vorontsov <anton@enomsg.org>
The bcm2835 is an ARM1176 which has all the V6K extensions except for SMP,
so V6K should be selected instead. Dropping the select will use
the default for ARCH_MULTI_V6 which is V6K.
Signed-off-by: Rob Herring <robh@kernel.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Many V6 and V7 platforms have an L2x0 cache, so make
CONFIG_MIGHT_HAVE_CACHE_L2X0 visible for V6 and V7 multi-platform
builds.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
All V7 platforms can run SMP kernels, so make CONFIG_SMP visible for V7
multi-platform builds.
Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
If CLK_SET_RATE_PARENT is set for a clkoutx2 clock, calling
clk_set_rate() on the clock "skips" the x2 multiplier as there are no
set_rate and round_rate functions defined for the clkoutx2.
This results in getting double the requested clock rates, breaking the
display on omap3430 based devices. This got broken when
d0f58bd3bb and related patches were merged
for v3.14, as omapdss driver now relies more on the clk-framework and
CLK_SET_RATE_PARENT.
This patch implements set_rate and round_rate for clkoutx2.
Tested on OMAP3430, OMAP3630, OMAP4460.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Commit 313a76e (ARM: OMAP2+: hwmod: Fix SOFTRESET logic) introduced
softreset bit cleaning right after set one. It is caused L3 error for
OMAP4 ISS because ISS register write occurs when ISS reset process is in
progress. Avoid this situation by cleaning softreset bit later, when reset
process is successfully finished.
Signed-off-by: Illia Smyrnov <illia.smyrnov@globallogic.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The spinlock module's SYSCONFIG register on DRA7xx does not
support smart wakeup, and also does not have the CLKACTIVITY
field. The sysc data for spinlock module has been appropriately
fixed up to reflect the same.
Cc: Ambresh K <ambresh@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Use the correct register offset for issuing the
reset command in OMAP5. Since dev_inst is set dynamically
OMAP4 should not be affected by this change.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@gmail.com>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Venice2 contains an SPI Flash chip, which contains the bootloader.
Add this to the DT, so the kernel can access it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Cardhu has a PCA9546 for I2C bus extension, which connects to 3
cameras. It's required for Tegra V4L2 soc camera driver and camera
sensor drivers.
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This cleanup series gets rid of <mach/timex.h> for platforms not using
ARCH_MULTIPLATFORM. (For multi-platform code it's already unused since
387798b (ARM: initial multiplatform support).)
To make this work some code out of arch/arm needed to be adapted. The
respective changes got acks by their maintainers to be taken via armsoc
(with Andrew Morton substituting for Alessandro Zummo as rtc maintainer).
Compared to the previous pull request there was another patch added that
fixes a (non-critical) regression on ixp4xx. Olof Johansson asked to not
squash this fix into the original commit to save him from the need to
reverify the series.
* tag 'dropmachtimexh-v2' of git://git.pengutronix.de/git/ukl/linux:
ARM: ixp4xx: fix timer latch calculation
ARM: drop <mach/timex.h> for !ARCH_MULTIPLATFORM, too
ARM: rpc: stop using <mach/timex.h>
ARM: ixp4xx: stop using <mach/timex.h>
input: ixp4xx-beeper: don't use symbols from <mach/timex.h>
ARM: at91: don't use <mach/timex.h>
ARM: ep93xx: stop using mach/timex.h
ARM: mmp: stop using mach/timex.h
ARM: netx: stop using mach/timex.h
ARM: sa1100: stop using mach/timex.h
clocksource: sirf/marco+prima2: drop usage of CLOCK_TICK_RATE
rtc: pxa: drop unused #define TIMER_FREQ
rtc: at91sam9: include <mach/hardware.h> explicitly
ARM/serial: at91: switch atmel serial to use gpiolib
Signed-off-by: Olof Johansson <olof@lixom.net>
Fix tegra_init_cache() to check whether the system has a PL310 cache
before touching the PL310 registers. This prevents access to non-existent
registers on Tegra114 and later.
Note for stable kernels:
In <= v3.12, the file to patch is arch/arm/mach-tegra/common.c.
Cc: <stable@vger.kernel.org> # v3.9+
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
The number of the head specifies the index of the display controller
unit and is required to properly configure outputs so that they receive
video data from the correct source.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
mvebu dt fixes for v3.14
- mvebu: add missing 'eth3' alias for mv78260
- dove: revert PMU interrupt controller node, wait for driver to land.
* tag 'mvebu-dt-fixes-3.14' of git://git.infradead.org/linux-mvebu:
ARM: dove: dt: revert PMU interrupt controller node
ARM: mvebu: dt: add missing alias 'eth3' on Armada XP mv78260
Signed-off-by: Olof Johansson <olof@lixom.net>
When building a kernel image with only CONFIG_CPU_IDLE but no CONFIG_PM,
we will get the following link error.
LD init/built-in.o
arch/arm/mach-imx/built-in.o: In function `imx6q_enter_wait':
platform-spi_imx.c:(.text+0x25c0): undefined reference to `imx6q_set_lpm'
platform-spi_imx.c:(.text+0x25d4): undefined reference to `imx6q_set_lpm'
arch/arm/mach-imx/built-in.o: In function `imx6q_cpuidle_init':
platform-spi_imx.c:(.init.text+0x75d4): undefined reference to `imx6q_set_chicken_bit'
make[1]: *** [vmlinux] Error 1
Since pm-imx6q.c has been a collection of library functions that access
CCM low-power registers used by not only suspend but also cpuidle and
other drivers, let's build pm-imx6q.c independently of CONFIG_PM to fix
above error.
Reported-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: stable@vger.kernel.org
Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
* pci/misc:
PCI: Enable INTx if BIOS left them disabled
ia64/PCI: Set IORESOURCE_ROM_SHADOW only for the default VGA device
x86/PCI: Set IORESOURCE_ROM_SHADOW only for the default VGA device
PCI: Update outdated comment for pcibios_bus_report_status()
PCI: Cleanup per-arch list of object files
PCI: cpqphp: Fix hex vs decimal typo in cpqhpc_probe()
x86/PCI: Fix function definition whitespace
x86/PCI: Reword comments
x86/PCI: Remove unnecessary local variable initialization
PCI: Remove unnecessary list_empty(&pci_pme_list) check
Fixes for omaps, mostly to deal with the 34xx vs 36xx SoC
configuration for overo boards.
* tag 'omap-for-v3.14/fixes-against-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
Documentation: dt: OMAP: Update Overo/Tobi
ARM: dts: Add support for both OMAP35xx and OMAP36xx Overo/Tobi
ARM: dts: omap3-tobi: Use the correct vendor prefix
ARM: dts: omap3-tobi: Fix boot with OMAP36xx-based Overo
ARM: OMAP2+: Remove legacy macros for zoom platforms
ARM: OMAP2+: Remove MACH_NOKIA_N800
ARM: dts: N900: add missing compatible property
ARM: dts: N9/N950: fix boot hang with 3.14-rc1
ARM: OMAP1: nokia770: enable tahvo-usb
ARM: OMAP2+: gpmc: fix: DT ONENAND child nodes not probed when MTD_ONENAND is built as module
ARM: OMAP2+: gpmc: fix: DT NAND child nodes not probed when MTD_NAND is built as module
ARM: dts: omap3-gta04: Fix mmc1 properties.
ARM: dts: omap3-gta04: Fix 'aux' gpio key flags.
ARM: OMAP2+: add missing ARCH_HAS_OPP
ARM: dts: am335x-evmsk: Fix mmc1 support
ARM: DTS: am335x-evmsk: Correct audio clock frequency
ARM: dts: omap3-gta04: Add EOC irq gpio line handling.
Signed-off-by: Olof Johansson <olof@lixom.net>
This alias entry was evidently cut/paste from a different board, and
not correctly updated to match Cardhu. Fix this.
Fixes: 553c0a200e ("ARM: tegra: set up /aliases entries for RTCs")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Pull ARM fixes from Russell King:
"A range of ARM fixes. Biggest change is the stage-2 attributes used
for for hyp mode which were wrong. I've killed some bits in a couple
of DT files which turned out not to be required, and a few other
fixes.
One fix touches code outside of arch/arm, which is related to sorting
out the DMA masks correctly. There is a long standing issue with the
conversion from PFNs to addresses where people assume that shifting an
unsigned long left by PAGE_SHIFT results in a correct address. This
is not the case with C: the integer promotion happens at assignment
after evaluation. This fixes the recently introduced dma_max_pfn()
function, but there's a number of other places where we try this
directly on an unsigned long in the mm code"
* 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
ARM: 7957/1: add DSB after icache flush in __flush_icache_all()
Fix uses of dma_max_pfn() when converting to a limiting address
ARM: 7955/1: spinlock: ensure we have a compiler barrier before sev
ARM: 7953/1: mm: ensure TLB invalidation is complete before enabling MMU
ARM: 7952/1: mm: Fix the memblock allocation for LPAE machines
ARM: 7950/1: mm: Fix stage-2 device memory attributes
ARM: dts: fix spdif pinmux configuration
The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
use the syscon driver to set sdmmc_clk's phase shift that is located in the
system manager.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
---
v9: none
v8: Use degrees in the clk-phase binding property
v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
prepare function to the gate clk that will toggle clock phase setting.
Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
set the phase shift settings.
v5: Use the "snps,dw-mshc" binding
v4: Use the sdmmc_clk prepare function to set the phase shift settings
v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
loaded after the clock driver.
v2: Use the syscon driver
The only thing that socfpga_init_clocks was doing is setting up the smp_twd clk.
Now that twd-timer's clock phandle is populated in the DTS, we can remove
this function.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
The clk manager's base address was being mapped in SOCFPGA's arch code and
being extern'ed out to the clock driver. This method is not correct, and the
arch code was not really doing anything with that clk manager anyways.
This patch moves the mapping of the clk manager's base address in the clock
driver itself. Cleans up CLK_OF_DECLARE() into a single registration of all
the clocks.
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
v2: Use a static declaration for the clk_mgr_base_addr. Clean up the
CLK_OF_DECLARE() as suggested by Arnd.
Attempt to invoke the prepare_idle() and do_idle() firmware calls
to power down a CPU so an underlying firmware gets informed of
the idle operation and performs it by itself if designed in such a way.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Support the prepare_idle() firmware call, which is necessary to properly
support CPU idling.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Some firmwares do not put the CPU into idle mode themselves, but still
need to be informed that the CPU is about to enter idle mode before this
happens. Add a prepare_idle() operation to the firmware_ops structure to
handle such cases.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
When Trusted Foundations is detected as present on the system, but
Trusted Foundations support is not built into the kernel, the kernel
used to issue a panic very early during boot, leaving little clue to the
user as to what is going wrong.
It turns out that even without TF support built-in, the kernel can boot
on a TF-enabled system provided that SMP and cpuidle are disabled. This
patch does this and continue booting on one CPU, leaving the user with a
usable (however degraded) system.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
