1d43e24b94
Writing/updating boot image in nand device is not straight forward in i.MX6 platform and it requires boot control block(BCB) to be configured. It becomes difficult to use uboot 'nand' command to write BCB since it requires platform specific attributes need to be taken care of. It is even difficult to use existing msx-nand.c driver by incorporating BCB attributes like mxs_dma_desc does because it requires change in mtd and nand command. So, cmd_nandbcb implemented in arch/arm/mach-imx BCB contains two data structures, Firmware Configuration Block(FCB) and Discovered Bad Block Table(DBBT). FCB has nand timings, DBBT search area, page address of firmware. On summary, nandbcb update will - erase the entire partition - create BCB by creating 2 FCB/DBBT block followed by 1 FW block based on partition size and erasesize. - fill FCB/DBBT structures - write FW/SPL on FW1 - write FCB/DBBT in first 2 blocks for nand boot, up on reset bootrom look for FCB structure in first block's if FCB found the nand timings are loaded for further reads. once FCB read done, DTTB will load and finally firmware will be loaded which is boot image. Refer section "NAND Boot" from doc/imx/common/imx6.txt for more usage information. Reviewed-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Sergey Kubushyn <ksi@koi8.net> Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
74 lines
2.2 KiB
C
74 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* NXP GPMI NAND flash driver
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*
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* Copyright (C) 2018 Toradex
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* Authors:
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* Stefan Agner <stefan.agner@toradex.com>
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*/
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#include <linux/mtd/mtd.h>
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#include <asm/cache.h>
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#include <nand.h>
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#include <asm/mach-imx/dma.h>
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/**
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* @gf_len: The length of Galois Field. (e.g., 13 or 14)
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* @ecc_strength: A number that describes the strength of the ECC
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* algorithm.
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* @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note
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* the first chunk in the page includes both data and
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* metadata, so it's a bit larger than this value.
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* @ecc_chunk_count: The number of ECC chunks in the page,
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* @block_mark_byte_offset: The byte offset in the ECC-based page view at
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* which the underlying physical block mark appears.
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* @block_mark_bit_offset: The bit offset into the ECC-based page view at
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* which the underlying physical block mark appears.
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*/
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struct bch_geometry {
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unsigned int gf_len;
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unsigned int ecc_strength;
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unsigned int ecc_chunk_size;
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unsigned int ecc_chunk_count;
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unsigned int block_mark_byte_offset;
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unsigned int block_mark_bit_offset;
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};
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struct mxs_nand_info {
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struct nand_chip chip;
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struct udevice *dev;
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unsigned int max_ecc_strength_supported;
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bool use_minimum_ecc;
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int cur_chip;
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uint32_t cmd_queue_len;
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uint32_t data_buf_size;
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struct bch_geometry bch_geometry;
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uint8_t *cmd_buf;
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uint8_t *data_buf;
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uint8_t *oob_buf;
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uint8_t marking_block_bad;
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uint8_t raw_oob_mode;
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struct mxs_gpmi_regs *gpmi_regs;
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struct mxs_bch_regs *bch_regs;
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/* Functions with altered behaviour */
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int (*hooked_read_oob)(struct mtd_info *mtd,
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loff_t from, struct mtd_oob_ops *ops);
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int (*hooked_write_oob)(struct mtd_info *mtd,
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loff_t to, struct mtd_oob_ops *ops);
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int (*hooked_block_markbad)(struct mtd_info *mtd,
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loff_t ofs);
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/* DMA descriptors */
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struct mxs_dma_desc **desc;
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uint32_t desc_index;
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};
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int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info);
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int mxs_nand_init_spl(struct nand_chip *nand);
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int mxs_nand_setup_ecc(struct mtd_info *mtd);
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