fdd15b6a86
While IECTRL is disabled, input signals are pulled-down internally.
If pin-muxing is set up first, glitch signals (Low to High transition)
might be input to hardware blocks.
Bad case scenario:
[1] The hardware block is already running before pinctrl is handled.
(the reset is de-asserted by default or by a firmware, for example)
[2] The pin-muxing is set up. The input signals to hardware block
are pulled-down by the chip-internal biasing.
[3] The pins are input-enabled. The signals from the board reach the
hardware block.
Actually, one invalid character is input to the UART blocks for such
SoCs as PH1-LD4, PH1-sLD8, where UART devices start to run at the
power on reset.
To avoid such problems, pins should be input-enabled before muxing.
[ ported from Linux commit bac7f4c1bf5e7c6ccd5bb71edc015b26c77f7460 ]
Fixes:
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.. | ||
Kconfig | ||
Makefile | ||
pinctrl-ph1-ld4.c | ||
pinctrl-ph1-ld6b.c | ||
pinctrl-ph1-pro4.c | ||
pinctrl-ph1-pro5.c | ||
pinctrl-ph1-sld8.c | ||
pinctrl-proxstream2.c | ||
pinctrl-uniphier-core.c | ||
pinctrl-uniphier.h |