61 lines
2.0 KiB
Plaintext
61 lines
2.0 KiB
Plaintext
-----------------------------
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NAND boot on PPC440 platforms
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-----------------------------
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This document describes the U-Boot NAND boot feature as it
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is implemented for the AMCC Sequoia (PPC440EPx) board.
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The PPC440EP(x)/GR(x) cpu's can boot directly from NAND FLASH,
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completely without NOR FLASH. This can be done by using the NAND
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boot feature of the 440 NAND flash controller (NDFC).
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Here a short desciption of the different boot stages:
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a) IPL (Initial Program Loader, integrated inside CPU)
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------------------------------------------------------
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Will load first 4k from NAND (SPL) into cache and execute it from there.
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b) SPL (Secondary Program Loader)
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---------------------------------
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Will load special U-Boot version (NUB) from NAND and execute it. This SPL
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has to fit into 4kByte. It sets up the CPU and configures the SDRAM
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controller and the NAND controller so that the special U-Boot image can be
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loaded from NAND to SDRAM.
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This special image is build in the directory "nand_spl".
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c) NUB (NAND U-Boot)
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--------------------
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This NAND U-Boot (NUB) is a special U-Boot version which can be started
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from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
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On 440EPx the SPL is copied to internal SRAM before the NAND controller
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is set up. While still running from cache, I experienced problems accessing
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the NAND controller.
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Example: Build and install NAND boot image for Sequoia (440EPx):
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a) Configure for sequoia with NAND boot support:
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# make sequoia_nand_config
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b) Build image(s)
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# make
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This will generate the SPL image in the "nand_spl" directory:
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nand_spl/u-boot-spl.bin
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Also another image is created spanning a whole NAND block (16kBytes):
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nand_spl/u-boot-spl-16k.bin
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The main NAND U-Boot image is generated in the toplevel directory:
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u-boot.bin
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A combined image of u-boot-spl-16k.bin and u-boot.bin is also created:
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u-boot-nand.bin
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This image should be programmed at offset 0 in the NAND flash:
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# tftp 100000 /tftpboot/sequoia/u-boot-nand.bin
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# nand erase 0 60000
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# nand write 100000 0 60000
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September 07 2006, Stefan Roese <sr@denx.de>
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