85b8c5c4bf
Conflicts: arch/arm/cpu/arm926ejs/mxs/Makefile board/compulab/cm_t35/Makefile board/corscience/tricorder/Makefile board/ppcag/bg0900/Makefile drivers/bootcount/Makefile include/configs/omap4_common.h include/configs/pdnb3.h Makefile conflicts are due to additions/removals of object files on the ARM branch vs KBuild introduction on the main branch. Resolution consists in adjusting the list of object files in the main branch version. This also applies to two files which are not listed as conflicting but had to be modified: board/compulab/common/Makefile board/udoo/Makefile include/configs/omap4_common.h conflicts are due to the OMAP4 conversion to ti_armv7_common.h on the ARM side, and CONFIG_SYS_HZ removal on the main side. Resolution is to convert as this icludes removal of CONFIG_SYS_HZ. include/configs/pdnb3.h is due to a removal on ARM side. Trivial resolution is to remove the file. Note: 'git show' will also list two files just because they are new: include/configs/am335x_igep0033.h include/configs/omap3_igep00x0.h
158 lines
4.2 KiB
C
158 lines
4.2 KiB
C
/*
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* (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org>
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*
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* Configuation settings for the AFEB9260 board.
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* Based on configuration for AT91SAM9260-EK
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91SAM9260 /* Atmel AT91SAM9260 SoC*/
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#include <asm/arch/hardware.h>
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#define CONFIG_SYS_TEXT_BASE 0x21f00000
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_AFEB9260 /* AFEB9260 Board */
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/*
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* Hardware drivers
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*/
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#define CONFIG_ATMEL_LEGACY
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#define CONFIG_AT91_GPIO
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#define CONFIG_AT91_PULLUP 1
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_SYS
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#define CONFIG_USART3 /* USART 3 is DBGU */
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#define CONFIG_BOOTDELAY 3
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE 1
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#define CONFIG_BOOTP_BOOTPATH 1
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#define CONFIG_BOOTP_GATEWAY 1
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#define CONFIG_BOOTP_HOSTNAME 1
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_BDI
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_IMI
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_SOURCE
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_USB
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
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/* DataFlash */
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#define CONFIG_ATMEL_DATAFLASH_SPI
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#define CONFIG_HAS_DATAFLASH
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#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
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#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
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#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
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#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */
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#define AT91_SPI_CLK 15000000
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#define DATAFLASH_TCSS (0x1a << 16)
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#define DATAFLASH_TCHS (0x1 << 24)
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
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#define CONFIG_SYS_NAND_DBW_8
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
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#endif
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/* NOR flash - no real flash on this board */
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#define CONFIG_SYS_NO_FLASH
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/* Ethernet */
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#define CONFIG_MACB
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#define CONFIG_RESET_PHY_R
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#define CONFIG_NET_RETRY_COUNT 20
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/* USB */
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#define CONFIG_USB_ATMEL
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#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_DOS_PARTITION
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
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#define CONFIG_USB_STORAGE
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#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* load address */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END 0x21e00000
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#define CONFIG_SYS_USE_DATAFLASH_CS1
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#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 -\
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GENERATED_GBL_DATA_SIZE)
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/* bootstrap + u-boot + env + linux in dataflash on CS1 */
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#define CONFIG_ENV_IS_IN_DATAFLASH
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
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#define CONFIG_ENV_OFFSET 0x4200
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#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
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#define CONFIG_ENV_SIZE 0x4200
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#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xa0000 0x200000; bootm"
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#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
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"root=/dev/mtdblock2 " \
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"rw rootfstype=jffs2 panic=20"
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_PROMPT "U-Boot> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
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#endif
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