573 lines
16 KiB
C
573 lines
16 KiB
C
/*
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* File: scc.c
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* Description:
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* Basic ET HW initialization and packet RX/TX routines
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*
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* NOTE <<<IMPORTANT: PLEASE READ>>>:
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* Do not cache Rx/Tx buffers!
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*/
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/*
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* MPC823 <-> MC68160 Connections:
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*
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* Setup MPC823 to work with MC68160 Enhanced Ethernet
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* Serial Tranceiver as follows:
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*
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* MPC823 Signal MC68160 Comments
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* ------ ------ ------- --------
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* PA-12 ETHTX --------> TX Eth. Port Transmit Data
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* PB-18 E_TENA --------> TENA Eth. Transmit Port Enable
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* PA-5 ETHTCK <-------- TCLK Eth. Port Transmit Clock
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* PA-13 ETHRX <-------- RX Eth. Port Receive Data
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* PC-8 E_RENA <-------- RENA Eth. Receive Enable
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* PA-6 ETHRCK <-------- RCLK Eth. Port Receive Clock
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* PC-9 E_CLSN <-------- CLSN Eth. Port Collision Indication
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*
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* FADS Board Signal MC68160 Comments
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* ----------------- ------- --------
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* (BCSR1) ETHEN* --------> CS2 Eth. Port Enable
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* (BSCR4) TPSQEL* --------> TPSQEL Twisted Pair Signal Quality Error Test Enable
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* (BCSR4) TPFLDL* --------> TPFLDL Twisted Pair Full-Duplex
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* (BCSR4) ETHLOOP --------> LOOP Eth. Port Diagnostic Loop-Back
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*
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*/
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#include <common.h>
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#include <malloc.h>
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#include <commproc.h>
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#include <net.h>
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#include <command.h>
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#if defined(CONFIG_CMD_NET) && defined(SCC_ENET)
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/* Ethernet Transmit and Receive Buffers */
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#define DBUF_LENGTH 1520
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#define TX_BUF_CNT 2
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#define TOUT_LOOP 10000 /* 10 ms to have a packet sent */
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static char txbuf[DBUF_LENGTH];
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static uint rxIdx; /* index of the current RX buffer */
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static uint txIdx; /* index of the current TX buffer */
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/*
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* SCC Ethernet Tx and Rx buffer descriptors allocated at the
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* immr->udata_bd address on Dual-Port RAM
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* Provide for Double Buffering
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*/
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typedef volatile struct CommonBufferDescriptor {
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cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
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cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
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} RTXBD;
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static RTXBD *rtx;
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static int scc_send(struct eth_device* dev, volatile void *packet, int length);
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static int scc_recv(struct eth_device* dev);
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static int scc_init (struct eth_device* dev, bd_t * bd);
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static void scc_halt(struct eth_device* dev);
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int scc_initialize(bd_t *bis)
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{
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struct eth_device* dev;
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dev = (struct eth_device*) malloc(sizeof *dev);
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memset(dev, 0, sizeof *dev);
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sprintf(dev->name, "SCC ETHERNET");
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dev->iobase = 0;
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dev->priv = 0;
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dev->init = scc_init;
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dev->halt = scc_halt;
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dev->send = scc_send;
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dev->recv = scc_recv;
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eth_register(dev);
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return 1;
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}
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static int scc_send(struct eth_device* dev, volatile void *packet, int length)
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{
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int i, j=0;
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#if 0
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volatile char *in, *out;
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#endif
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/* section 16.9.23.3
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* Wait for ready
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*/
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#if 0
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while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY);
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out = (char *)(rtx->txbd[txIdx].cbd_bufaddr);
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in = packet;
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for(i = 0; i < length; i++) {
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*out++ = *in++;
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}
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rtx->txbd[txIdx].cbd_datlen = length;
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rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST);
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while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++;
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#ifdef ET_DEBUG
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printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
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#endif
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i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
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/* wrap around buffer index when necessary */
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if (txIdx >= TX_BUF_CNT) txIdx = 0;
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#endif
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while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
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udelay (1); /* will also trigger Wd if needed */
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j++;
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}
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if (j>=TOUT_LOOP) printf("TX not ready\n");
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rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
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rtx->txbd[txIdx].cbd_datlen = length;
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rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP);
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while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
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udelay (1); /* will also trigger Wd if needed */
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j++;
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}
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if (j>=TOUT_LOOP) printf("TX timeout\n");
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#ifdef ET_DEBUG
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printf("cycles: %d status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
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#endif
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i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
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return i;
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}
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static int scc_recv (struct eth_device *dev)
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{
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int length;
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for (;;) {
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/* section 16.9.23.2 */
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if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
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length = -1;
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break; /* nothing received - leave for() loop */
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}
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length = rtx->rxbd[rxIdx].cbd_datlen;
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if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
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#ifdef ET_DEBUG
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printf ("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
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#endif
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} else {
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/* Pass the packet up to the protocol layers. */
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NetReceive (NetRxPackets[rxIdx], length - 4);
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}
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/* Give the buffer back to the SCC. */
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rtx->rxbd[rxIdx].cbd_datlen = 0;
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/* wrap around buffer index when necessary */
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if ((rxIdx + 1) >= PKTBUFSRX) {
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rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
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(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
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rxIdx = 0;
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} else {
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rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
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rxIdx++;
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}
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}
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return length;
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}
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/**************************************************************
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*
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* SCC Ethernet Initialization Routine
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*
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*************************************************************/
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static int scc_init (struct eth_device *dev, bd_t * bis)
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{
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int i;
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scc_enet_t *pram_ptr;
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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#if defined(CONFIG_LWMON)
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reset_phy();
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#endif
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#ifdef CONFIG_FADS
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#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC860T)
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/* The MPC86xADS/FADS860T don't use the MODEM_EN or DATA_VOICE signals. */
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*((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
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*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
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*((uint *) BCSR1) &= ~BCSR1_ETHEN;
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#else
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*((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
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*((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
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*((uint *) BCSR1) &= ~BCSR1_ETHEN;
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#endif
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#endif
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pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[PROFF_ENET]);
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rxIdx = 0;
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txIdx = 0;
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if (!rtx) {
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#ifdef CONFIG_SYS_ALLOC_DPRAM
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rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
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dpram_alloc_align (sizeof (RTXBD), 8));
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#else
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rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
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#endif
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}
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#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
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/* Configure port A pins for Txd and Rxd.
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*/
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immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
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immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
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immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
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#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
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/* Configure port B pins for Txd and Rxd.
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*/
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immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
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immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
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immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
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#else
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#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
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#endif
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#if defined(PC_ENET_LBK)
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/* Configure port C pins to disable External Loopback
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*/
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immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
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immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
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immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
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immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
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#endif /* PC_ENET_LBK */
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/* Configure port C pins to enable CLSN and RENA.
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*/
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immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
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immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
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immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
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/* Configure port A for TCLK and RCLK.
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*/
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immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
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immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
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/*
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* Configure Serial Interface clock routing -- see section 16.7.5.3
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* First, clear all SCC bits to zero, then set the ones we want.
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*/
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immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
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immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
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/*
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* Initialize SDCR -- see section 16.9.23.7
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* SDMA configuration register
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*/
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immr->im_siu_conf.sc_sdcr = 0x01;
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/*
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* Setup SCC Ethernet Parameter RAM
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*/
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pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
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pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
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pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
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pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
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pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
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/*
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* Setup Receiver Buffer Descriptors (13.14.24.18)
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* Settings:
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* Empty, Wrap
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*/
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for (i = 0; i < PKTBUFSRX; i++) {
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rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
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rtx->rxbd[i].cbd_datlen = 0; /* Reset */
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rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
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}
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rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
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/*
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* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
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* Settings:
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* Add PADs to Short FRAMES, Wrap, Last, Tx CRC
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*/
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for (i = 0; i < TX_BUF_CNT; i++) {
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rtx->txbd[i].cbd_sc =
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(BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
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rtx->txbd[i].cbd_datlen = 0; /* Reset */
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rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
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}
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rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
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/*
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* Enter Command: Initialize Rx Params for SCC
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*/
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do { /* Spin until ready to issue command */
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__asm__ ("eieio");
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} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
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/* Issue command */
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immr->im_cpm.cp_cpcr =
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((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
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do { /* Spin until command processed */
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__asm__ ("eieio");
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} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
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/*
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* Ethernet Specific Parameter RAM
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* see table 13-16, pg. 660,
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* pg. 681 (example with suggested settings)
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*/
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pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
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pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
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pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
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pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
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pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
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pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
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pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
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pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
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pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
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pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
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pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
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pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
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pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
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pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
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pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
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#define ea eth_get_dev()->enetaddr
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pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
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pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
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pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
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#undef ea
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pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
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pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
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pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
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pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
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pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
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pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
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pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
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pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
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/*
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* Enter Command: Initialize Tx Params for SCC
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*/
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do { /* Spin until ready to issue command */
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__asm__ ("eieio");
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} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
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/* Issue command */
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immr->im_cpm.cp_cpcr =
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((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
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do { /* Spin until command processed */
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__asm__ ("eieio");
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} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
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/*
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* Mask all Events in SCCM - we use polling mode
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*/
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immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0;
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/*
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* Clear Events in SCCE -- Clear bits by writing 1's
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*/
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immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);
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/*
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* Initialize GSMR High 32-Bits
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* Settings: Normal Mode
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*/
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immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;
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/*
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* Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
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* Settings:
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* TCI = Invert
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* TPL = 48 bits
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* TPP = Repeating 10's
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* MODE = Ethernet
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*/
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immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (SCC_GSMRL_TCI |
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SCC_GSMRL_TPL_48 |
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SCC_GSMRL_TPP_10 |
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SCC_GSMRL_MODE_ENET);
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/*
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* Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
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*/
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immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555;
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/*
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* Initialize the PSMR
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* Settings:
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* CRC = 32-Bit CCITT
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* NIB = Begin searching for SFD 22 bits after RENA
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* FDE = Full Duplex Enable
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* LPB = Loopback Enable (Needed when FDE is set)
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* BRO = Reject broadcast packets
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* PROMISCOUS = Catch all packets regardless of dest. MAC adress
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*/
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immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = SCC_PSMR_ENCRC |
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SCC_PSMR_NIB22 |
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#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
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SCC_PSMR_FDE | SCC_PSMR_LPB |
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#endif
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#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
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SCC_PSMR_BRO |
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#endif
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#if defined(CONFIG_SCC_ENET_PROMISCOUS)
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SCC_PSMR_PRO |
|
|
#endif
|
|
0;
|
|
|
|
/*
|
|
* Configure Ethernet TENA Signal
|
|
*/
|
|
|
|
#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
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|
immr->im_ioport.iop_pcpar |= PC_ENET_TENA;
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|
immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
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|
#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
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|
immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
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|
immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
|
|
#else
|
|
#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
|
|
#endif
|
|
|
|
#if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
|
|
/*
|
|
* Port C is used to control the PHY,MC68160.
|
|
*/
|
|
immr->im_ioport.iop_pcdir |=
|
|
(PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
|
|
|
|
immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
|
|
immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
|
|
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
|
|
#endif /* MPC860ADS */
|
|
|
|
#if defined(CONFIG_AMX860)
|
|
/*
|
|
* Port B is used to control the PHY,MC68160.
|
|
*/
|
|
immr->im_cpm.cp_pbdir |=
|
|
(PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
|
|
|
|
immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
|
|
immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
|
|
|
|
immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
|
|
immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
|
|
#endif /* AMX860 */
|
|
|
|
#ifdef CONFIG_RPXCLASSIC
|
|
*((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
|
|
*((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
|
|
#endif
|
|
|
|
#ifdef CONFIG_RPXLITE
|
|
*((uchar *) BCSR0) |= BCSR0_ETHEN;
|
|
#endif
|
|
|
|
#if defined(CONFIG_QS860T)
|
|
/*
|
|
* PB27=FDE-, set output low for full duplex
|
|
* PB26=Link Test Enable, normally high output
|
|
*/
|
|
immr->im_cpm.cp_pbdir |= 0x00000030;
|
|
immr->im_cpm.cp_pbdat |= 0x00000020;
|
|
immr->im_cpm.cp_pbdat &= ~0x00000010;
|
|
#endif /* QS860T */
|
|
|
|
#ifdef CONFIG_MBX
|
|
board_ether_init ();
|
|
#endif
|
|
|
|
#if defined(CONFIG_NETVIA)
|
|
#if defined(PA_ENET_PDN)
|
|
immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
|
|
immr->im_ioport.iop_padir |= PA_ENET_PDN;
|
|
immr->im_ioport.iop_padat |= PA_ENET_PDN;
|
|
#elif defined(PB_ENET_PDN)
|
|
immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
|
|
immr->im_cpm.cp_pbdir |= PB_ENET_PDN;
|
|
immr->im_cpm.cp_pbdat |= PB_ENET_PDN;
|
|
#elif defined(PC_ENET_PDN)
|
|
immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN;
|
|
immr->im_ioport.iop_pcdir |= PC_ENET_PDN;
|
|
immr->im_ioport.iop_pcdat |= PC_ENET_PDN;
|
|
#elif defined(PD_ENET_PDN)
|
|
immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN;
|
|
immr->im_ioport.iop_pddir |= PD_ENET_PDN;
|
|
immr->im_ioport.iop_pddat |= PD_ENET_PDN;
|
|
#endif
|
|
#endif
|
|
|
|
/*
|
|
* Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
|
|
*/
|
|
|
|
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
|
|
(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
|
|
|
/*
|
|
* Work around transmit problem with first eth packet
|
|
*/
|
|
#if defined (CONFIG_FADS)
|
|
udelay (10000); /* wait 10 ms */
|
|
#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
|
|
udelay (100000); /* wait 100 ms */
|
|
#endif
|
|
|
|
return 1;
|
|
}
|
|
|
|
|
|
static void scc_halt (struct eth_device *dev)
|
|
{
|
|
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
|
|
|
|
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &=
|
|
~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
|
|
|
immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA);
|
|
}
|
|
|
|
#if 0
|
|
void restart (void)
|
|
{
|
|
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
|
|
|
|
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |=
|
|
(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
|
|
}
|
|
#endif
|
|
#endif
|