b3d9a8b185
Following the example of most other SoCs in arch/$(ARCH)/cpu/$(CPU)/$(SOC)
move the lpc32xx code from arch/arm/cpu/arm926ejs/lpc32xx to
arch/arm/mach-lpc32xx.
Following the checklist from
commit 01f1445630 ("ARM: prepare for moving SoC sources into mach-*"):
[1] move files from arch/arm/cpu/arm926ejs/lpc32xx to arch/arm/mach-lpx32xx
[2] add machine entry to arch/arm/Makefile
[3] remove "obj-y += ..." from arch/arm/cpu/arm926ejs/Makefile
[4] fix the Kconfig file path in arch/arm/Kconfig
[5] (no MAINTAINERS update)
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
139 lines
2.7 KiB
C
139 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <div64.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clk.h>
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#include <asm/io.h>
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static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
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unsigned int get_sys_clk_rate(void)
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{
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if (readl(&clk->sysclk_ctrl) & CLK_SYSCLK_PLL397)
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return RTC_CLK_FREQUENCY * 397;
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else
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return OSC_CLK_FREQUENCY;
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}
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unsigned int get_hclk_pll_rate(void)
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{
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unsigned long long fin, fref, fcco, fout;
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u32 val, m_div, n_div, p_div;
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/*
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* Valid frequency ranges:
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* 1 * 10^6 <= Fin <= 20 * 10^6
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* 1 * 10^6 <= Fref <= 27 * 10^6
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* 156 * 10^6 <= Fcco <= 320 * 10^6
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*/
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fref = fin = get_sys_clk_rate();
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if (fin > 20000000ULL || fin < 1000000ULL)
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return 0;
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val = readl(&clk->hclkpll_ctrl);
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m_div = ((val & CLK_HCLK_PLL_FEEDBACK_DIV_MASK) >> 1) + 1;
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n_div = ((val & CLK_HCLK_PLL_PREDIV_MASK) >> 9) + 1;
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if (val & CLK_HCLK_PLL_DIRECT)
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p_div = 0;
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else
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p_div = ((val & CLK_HCLK_PLL_POSTDIV_MASK) >> 11) + 1;
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p_div = 1 << p_div;
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if (val & CLK_HCLK_PLL_BYPASS) {
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do_div(fin, p_div);
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return fin;
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}
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do_div(fref, n_div);
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if (fref > 27000000ULL || fref < 1000000ULL)
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return 0;
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fcco = fref * m_div;
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fout = fcco;
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if (val & CLK_HCLK_PLL_FEEDBACK)
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fcco *= p_div;
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else
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do_div(fout, p_div);
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if (fcco > 320000000ULL || fcco < 156000000ULL)
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return 0;
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return fout;
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}
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unsigned int get_hclk_clk_div(void)
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{
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u32 val;
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val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK;
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return 1 << val;
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}
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unsigned int get_hclk_clk_rate(void)
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{
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return get_hclk_pll_rate() / get_hclk_clk_div();
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}
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unsigned int get_periph_clk_div(void)
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{
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u32 val;
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val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK;
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return (val >> 2) + 1;
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}
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unsigned int get_periph_clk_rate(void)
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{
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if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
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return get_sys_clk_rate();
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return get_hclk_pll_rate() / get_periph_clk_div();
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}
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unsigned int get_sdram_clk_rate(void)
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{
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unsigned int src_clk;
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if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
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return get_sys_clk_rate();
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src_clk = get_hclk_pll_rate();
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if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) {
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/* using DDR */
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switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) {
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case CLK_HCLK_DDRAM_HALF:
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return src_clk/2;
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case CLK_HCLK_DDRAM_NOMINAL:
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return src_clk;
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default:
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return 0;
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}
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} else {
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/* using SDR */
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switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) {
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case CLK_HCLK_ARM_PLL_DIV_4:
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return src_clk/4;
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case CLK_HCLK_ARM_PLL_DIV_2:
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return src_clk/2;
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case CLK_HCLK_ARM_PLL_DIV_1:
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return src_clk;
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default:
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return 0;
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}
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}
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}
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int get_serial_clock(void)
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{
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return get_periph_clk_rate();
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}
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