308520b8f2
This removes the following unreferenced CONFIG symbols: CONFIG_FDTADDR CONFIG_FDTFILE CONFIG_FLASH_SECTOR_SIZE CONFIG_FSL_CPLD CONFIG_HDMI_ENCODER_I2C_ADDR CONFIG_I2C_MVTWSI CONFIG_I2C_RTC_ADDR CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE CONFIG_L1_INIT_RAM CONFIG_MACB_SEARCH_PHY CONFIG_MIU_2BIT_21_7_INTERLEAVED CONFIG_MTD_NAND_VERIFY_WRITE CONFIG_MVGBE_PORTS CONFIG_NETDEV CONFIG_NUM_DSP_CPUS CONFIG_PHY_BASE_ADR CONFIG_PHY_INTERFACE_MODE CONFIG_PSRAM_SCFG CONFIG_RAMBOOT_SPIFLASH CONFIG_RAMBOOT_TEXT_BASE CONFIG_RD_LVL CONFIG_ROCKCHIP_SDHCI_MAX_FREQ CONFIG_SETUP_INITRD_TAG CONFIG_SH_QSPI_BASE CONFIG_SMDK5420 CONFIG_SOCRATES CONFIG_SPI_ADDR CONFIG_SPI_FLASH_QUAD CONFIG_SPI_FLASH_SIZE CONFIG_SPI_HALF_DUPLEX CONFIG_SPI_N25Q256A_RESET CONFIG_TEGRA_SLINK_CTRLS CONFIG_TPM_TIS_BASE_ADDRESS CONFIG_UBOOT_SECTOR_COUNT CONFIG_UBOOT_SECTOR_START CONFIG_VAR_SIZE_SPL CONFIG_VERY_BIG_RAM And also: BL1_SIZE PHY_NO RESERVE_BLOCK_SIZE Signed-off-by: Tom Rini <trini@konsulko.com>
102 lines
2.7 KiB
C
102 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2019-2020 NXP
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*/
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#ifndef __LS1046AFRWY_H__
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#define __LS1046AFRWY_H__
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#include "ls1046a_common.h"
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#define CFG_SYS_UBOOT_BASE 0x40100000
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/*
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* NAND Flash Definitions
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*/
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#define CFG_SYS_NAND_BASE 0x7e800000
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#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
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#define CFG_SYS_NAND_CSPR_EXT (0x0)
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#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_NAND \
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| CSPR_V)
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#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
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#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
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| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
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| CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
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| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
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#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x7) | \
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FTIM0_NAND_TWH(0xa))
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#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0xe) | \
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FTIM1_NAND_TRP(0x18))
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#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
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FTIM2_NAND_TREH(0xa) | \
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FTIM2_NAND_TWHRE(0x1e))
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#define CFG_SYS_NAND_FTIM3 0x0
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#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
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/* IFC Timing Params */
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#define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
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#define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
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#define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
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#define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
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#define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
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#define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
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#define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
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#define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
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/* EEPROM */
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#define I2C_RETIMER_ADDR 0x18
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/* I2C bus multiplexer */
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#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
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#define I2C_MUX_CH_DEFAULT 0x1 /* Channel 0*/
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#define I2C_MUX_CH_RTC 0x1 /* Channel 0*/
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/* RTC */
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#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/
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#define CFG_SYS_RTC_BUS_NUM 0
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/*
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* Environment
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*/
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#define CFG_SYS_FSL_QSPI_BASE 0x40000000
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#undef BOOT_TARGET_DEVICES
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(USB, usb, 0) \
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func(DHCP, dhcp, na)
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/* FMan */
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#ifdef CONFIG_SYS_DPAA_FMAN
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#define QSGMII_PORT1_PHY_ADDR 0x1c
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#define QSGMII_PORT2_PHY_ADDR 0x1d
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#define QSGMII_PORT3_PHY_ADDR 0x1e
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#define QSGMII_PORT4_PHY_ADDR 0x1f
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#define FDT_SEQ_MACADDR_FROM_ENV
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#endif
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#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
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"env exists secureboot && esbc_halt;;"
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#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
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"env exists secureboot && esbc_halt;"
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#include <asm/fsl_secure_boot.h>
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#endif /* __LS1046AFRWY_H__ */
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