Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large usb writes Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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.. | ||
cpu | ||
include/asm | ||
lib | ||
config.mk | ||
Kconfig |
Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large usb writes Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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---|---|---|
.. | ||
cpu | ||
include/asm | ||
lib | ||
config.mk | ||
Kconfig |