f060054dad
Make it so we keep track of which LAWs have allocated and provide a function (set_next_law) which can allocate a LAW for us if one is free. In the future we will move to doing more "dynamic" LAW allocation since the majority of users dont really care about what LAW number they are at. Also, add CONFIG_MPC8540 or CONFIG_MPC8560 to those boards which needed them Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
396 lines
12 KiB
C
396 lines
12 KiB
C
/*
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* (C) Copyright 2003 Embedded Edge, LLC
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* Dan Malek <dan@embeddededge.com>
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* Copied from ADS85xx.
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* Updates for Silicon Tx GP3 8560 board.
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*
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* (C) Copyright 2002,2003 Motorola,Inc.
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* Xianghua Xiao <X.Xiao@motorola.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* mpc8560ads board configuration file */
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/* please refer to doc/README.mpc85xx for more info */
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/* make sure you change the MAC address and other network params first,
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* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
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#define CONFIG_CPM2 1 /* has CPM2 */
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#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
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#define CONFIG_MPC8560 1
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#undef CONFIG_PCI /* pci ethernet support */
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#define CONFIG_TSEC_ENET /* tsec ethernet support*/
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#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
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#undef CONFIG_DDR_ECC /* only for ECC DDR module */
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#define CONFIG_DDR_DLL /* possible DLL fix needed */
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#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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/* sysclk for MPC85xx
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*/
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#define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */
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/* Blinkin' LEDs for Robert :-)
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*/
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#define CONFIG_SHOW_ACTIVITY 1
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#undef CFG_DRAM_TEST /* memory test, takes time */
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#define CFG_MEMTEST_START 0x00200000 /* memtest region */
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#define CFG_MEMTEST_END 0x00400000
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/* Localbus SDRAM is an option, not all boards have it.
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* This address, however, is used to configure a 256M local bus
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* window that includes the Config latch below.
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*/
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#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
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#define CFG_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */
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#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
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#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
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#define CFG_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_MAX_FLASH_SECT 136 /* sectors per device */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/* The configuration latch is Chip Select 1.
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* It's an 8-bit latch in the lower 8 bits of the word.
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*/
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#define CFG_BR1_PRELIM 0xfc001801 /* 32-bit port */
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#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
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#define CFG_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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#define CFG_RAMBOOT
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#else
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#undef CFG_RAMBOOT
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#endif
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#ifdef CFG_RAMBOOT
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#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
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#else
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#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#endif
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#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
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#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
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#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
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/*
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* DDR Setup
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*/
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
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#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
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#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
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#undef CONFIG_CLOCKS_IN_MHZ
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/* local bus definitions */
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#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
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#define CFG_OR2_PRELIM 0xfc006901
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#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
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#define CFG_LBC_LBCR 0x00000000
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#define CFG_LBC_LSRT 0x20000000
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#define CFG_LBC_MRTPR 0x20000000
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#define CFG_LBC_LSDMR_1 0x2861b723
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#define CFG_LBC_LSDMR_2 0x0861b723
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#define CFG_LBC_LSDMR_3 0x0861b723
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#define CFG_LBC_LSDMR_4 0x1861b723
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#define CFG_LBC_LSDMR_5 0x4061b723
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#define CONFIG_L1_INIT_RAM
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#define CFG_INIT_RAM_LOCK 1
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#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
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#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/* Serial Port */
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#define CONFIG_CONS_ON_SCC /* define if console on SCC */
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#undef CONFIG_CONS_NONE /* define if console on something else */
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#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
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#define CONFIG_BAUDRATE 38400
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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/* Use the HUSH parser */
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#define CFG_HUSH_PARSER
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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/*
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* I2C
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*/
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#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
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#define CONFIG_HARD_I2C /* I2C with hardware support*/
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#if 0
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#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
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#else
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/* I did the 'if 0' so we could keep the syntax above if ever needed. */
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#undef CFG_I2C_NOPROBES
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#endif
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#define CFG_I2C_OFFSET 0x3000
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/* RapdIO Map configuration, mapped 1:1.
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*/
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#define CFG_RIO_MEM_BASE 0xc0000000
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#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
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#define CFG_RIO_MEM_SIZE 0x200000000 /* 512 M */
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/* Standard 8560 PCI addressing, mapped 1:1.
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*/
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#define CFG_PCI1_MEM_BASE 0x80000000
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#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
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#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
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#define CFG_PCI1_IO_BASE 0xe2000000
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#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
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#define CFG_PCI1_IO_SIZE 0x01000000 /* 16 M */
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#if defined(CONFIG_PCI) /* PCI Ethernet card */
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#undef CONFIG_EEPRO100
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#undef CONFIG_TULIP
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#if !defined(CONFIG_PCI_PNP)
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#define PCI_ENET0_IOADDR 0xe0000000
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#define PCI_ENET0_MEMADDR 0xe0000000
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#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
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#endif
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#undef CONFIG_PCI_SCAN_SHOW
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#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_TSEC_ENET)
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI 1
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#endif
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 4
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC2_FLAGS TSEC_GIGABIT
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#define CONFIG_ETHPRIME "TSEC0"
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#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
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#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
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#undef CONFIG_ETHER_NONE /* define if ether on something else */
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#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
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#if (CONFIG_ETHER_INDEX == 2)
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/*
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* - Rx-CLK is CLK13
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* - Tx-CLK is CLK14
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* - Select bus for bd/buffers
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* - Full duplex
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*/
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#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
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#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
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#define CFG_CPMFCR_RAMTYPE 0
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#if 0
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#define CFG_FCC_PSMR (FCC_PSMR_FDE)
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#else
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#define CFG_FCC_PSMR 0
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#endif
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#define FETH2_RST 0x01
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#elif (CONFIG_ETHER_INDEX == 3)
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/* need more definitions here for FE3 */
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#define FETH3_RST 0x80
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#endif /* CONFIG_ETHER_INDEX */
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/* MDIO is done through the TSEC0 control.
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*/
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#define CONFIG_MII /* MII PHY management */
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#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
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#endif
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/* Environment */
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/* We use the top boot sector flash, so we have some 16K sectors for env
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*/
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#ifndef CFG_RAMBOOT
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000)
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#define CFG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */
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#define CFG_ENV_SIZE 0x2000
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#else
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#define CFG_NO_FLASH 1 /* Flash is not usable now */
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#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
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#define CFG_ENV_SIZE 0x2000
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#endif
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#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
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#define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000"
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#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_I2C
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#if defined(CFG_RAMBOOT)
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#undef CONFIG_CMD_ENV
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#undef CONFIG_CMD_LOADS
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#else
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#define CONFIG_CMD_ELF
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#endif
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
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#define CONFIG_CMD_MII
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "GPPP=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_LOAD_ADDR 0x1000000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*Note: change below for your network setting!!! */
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#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
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#define CONFIG_HAS_ETH0
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#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
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#define CONFIG_HAS_ETH1
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#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
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#define CONFIG_HAS_ETH2
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#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
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#endif
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#define CONFIG_SERVERIP 192.168.85.1
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#define CONFIG_IPADDR 192.168.85.60
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#define CONFIG_GATEWAYIP 192.168.85.1
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_HOSTNAME STX_GP3
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#define CONFIG_ROOTPATH /gppproot
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#define CONFIG_BOOTFILE uImage
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#define CONFIG_LOADADDR 0x1000000
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#endif /* __CONFIG_H */
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