1b387ef55c
The SPDX License List version 1.19 now contains an official entry for the IBM-pibs license. However, instead of our suggestion "ibm-pibs", the SPDX License List uses "IBM-pibs", with the following rationale: "The reason being that all other SPDX License List short identifiers tend towards using capital letters unless spelling a word. I'd prefer to be consistent to this end". Change the license IDs to use the official name. Signed-off-by: Wolfgang Denk <wd@denx.de>
76 lines
2.8 KiB
ArmAsm
76 lines
2.8 KiB
ArmAsm
/*
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* SPDX-License-Identifier: GPL-2.0 IBM-pibs
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*/
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/*------------------------------------------------------------------------- */
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/* Function: ext_bus_cntlr_init */
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/* Description: Initializes the External Bus Controller for the external */
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/* peripherals. IMPORTANT: For pass1 this code must run from */
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/* cache since you can not reliably change a peripheral banks */
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/* timing register (pbxap) while running code from that bank. */
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/* For ex., since we are running from ROM on bank 0, we can NOT */
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/* execute the code that modifies bank 0 timings from ROM, so */
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/* we run it from cache. */
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/* */
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/* */
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/* The layout for the PEI JSE board: */
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/* Bank 0 - Flash and SRAM */
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/* Bank 1 - SystemACE */
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/* Bank 2 - not used */
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/* Bank 3 - not used */
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/* Bank 4 - not used */
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/* Bank 5 - not used */
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/* Bank 6 - not used */
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/* Bank 7 - not used */
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/*------------------------------------------------------------------------- */
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#include <asm/ppc4xx.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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.globl ext_bus_cntlr_init
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ext_bus_cntlr_init:
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mflr r4 /* save link register */
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bl ..getAddr
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..getAddr:
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mflr r3 /* get address of ..getAddr */
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mtlr r4 /* restore link register */
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addi r4,0,14 /* set ctr to 10; used to prefetch */
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mtctr r4 /* 10 cache lines to fit this function */
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/* in cache (gives us 8x10=80 instrctns) */
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..ebcloop:
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icbt r0,r3 /* prefetch cache line for addr in r3 */
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addi r3,r3,32 /* move to next cache line */
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bdnz ..ebcloop /* continue for 10 cache lines */
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/*----------------------------------------------------------------- */
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/* Delay to ensure all accesses to ROM are complete before changing */
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/* bank 0 timings. 200usec should be enough. */
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/* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
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/*----------------------------------------------------------------- */
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addis r3,0,0x0
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ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
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mtctr r3
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..spinlp:
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bdnz ..spinlp /* spin loop */
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/*----------------------------------------------------------------- */
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/* Memory Bank 0 (Flash) initialization */
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/*----------------------------------------------------------------- */
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addi r4,0,PB1AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0x9B01
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ori r4,r4,0x5480
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB0CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
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ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
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mtdcr EBC0_CFGDATA,r4
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blr
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