389 lines
15 KiB
C
389 lines
15 KiB
C
/*
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* (C) Copyright 2000
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* Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#if defined(CONFIG_8xx)
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#include <mpc8xx.h>
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#elif defined (CONFIG_405GP) || defined(CONFIG_405EP)
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#include <asm/processor.h>
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#elif defined (CONFIG_5xx)
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#include <mpc5xx.h>
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#elif defined (CONFIG_MPC5200)
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#include <mpc5xxx.h>
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#elif defined (CONFIG_MPC86xx)
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extern void mpc86xx_reginfo(void);
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#endif
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int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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#if defined(CONFIG_8xx)
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
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volatile sit8xx_t *timers = &immap->im_sit;
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/* Hopefully more PowerPC knowledgable people will add code to display
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* other useful registers
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*/
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printf ("\nSystem Configuration registers\n"
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"\tIMMR\t0x%08X\n", get_immr(0));
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printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
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printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
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printf("\tSWT\t0x%08X", sysconf->sc_swt);
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printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
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printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
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sysconf->sc_sipend, sysconf->sc_simask);
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printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
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sysconf->sc_siel, sysconf->sc_sivec);
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printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
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sysconf->sc_tesr, sysconf->sc_sdcr);
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printf ("Memory Controller Registers\n"
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"\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
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printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
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printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
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printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
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printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
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printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
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printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
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printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
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printf ("\n"
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"\tmamr\t0x%08X\tmbmr\t0x%08X \n",
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memctl->memc_mamr, memctl->memc_mbmr );
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printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
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memctl->memc_mstat, memctl->memc_mptpr );
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printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
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printf ("\nSystem Integration Timers\n"
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"\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
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timers->sit_tbscr, timers->sit_rtcsc);
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printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
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/*
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* May be some CPM info here?
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*/
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#elif defined (CONFIG_405GP)
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printf ("\n405GP registers; MSR=%08x\n",mfmsr());
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printf ("\nUniversal Interrupt Controller Regs\n"
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"uicsr uicsrs uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
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"\n"
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"%08x %08x %08x %08x %08x %08x %08x %08x %08x\n",
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mfdcr(uicsr),
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mfdcr(uicsrs),
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mfdcr(uicer),
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mfdcr(uiccr),
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mfdcr(uicpr),
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mfdcr(uictr),
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mfdcr(uicmsr),
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mfdcr(uicvr),
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mfdcr(uicvcr));
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puts ("\nMemory (SDRAM) Configuration\n"
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"besra besrsa besrb besrsb bear mcopt1 rtr pmit\n");
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mtdcr(memcfga,mem_besra); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_besrsa); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_besrb); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_besrsb); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_bear); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd));
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puts ("\n"
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"mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n");
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mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_mb2cf); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_mb3cf); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_ecccf); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_eccerr); printf ("%08x ", mfdcr(memcfgd));
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printf ("\n\n"
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"DMA Channels\n"
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"dmasr dmasgc dmaadr\n"
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"%08x %08x %08x\n"
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"dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n"
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"%08x %08x %08x %08x %08x\n"
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"dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n"
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"%08x %08x %08x %08x %08x\n",
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mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr),
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mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
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mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));
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printf (
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"dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
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"dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
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mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
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mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
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puts ("\n"
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"External Bus\n"
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"pbear pbesr0 pbesr1 epcr\n");
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mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd));
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puts ("\n"
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"pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n");
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mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd));
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puts ("\n"
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"pb4cr pb4ap pb5cr bp5ap pb6cr pb6ap pb7cr pb7ap\n");
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mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb5cr); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb5ap); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb6cr); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb6ap); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb7cr); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb7ap); printf ("%08x ", mfdcr(ebccfgd));
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puts ("\n\n");
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#elif defined(CONFIG_405EP)
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printf ("\n405EP registers; MSR=%08x\n",mfmsr());
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printf ("\nUniversal Interrupt Controller Regs\n"
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"uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
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"\n"
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"%08x %08x %08x %08x %08x %08x %08x %08x\n",
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mfdcr(uicsr),
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mfdcr(uicer),
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mfdcr(uiccr),
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mfdcr(uicpr),
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mfdcr(uictr),
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mfdcr(uicmsr),
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mfdcr(uicvr),
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mfdcr(uicvcr));
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puts ("\nMemory (SDRAM) Configuration\n"
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"mcopt1 rtr pmit mb0cf mb1cf sdtr1\n");
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mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd));
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mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd));
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printf ("\n\n"
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"DMA Channels\n"
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"dmasr dmasgc dmaadr\n" "%08x %08x %08x\n"
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"dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n"
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"dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n",
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mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr),
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mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
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mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));
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printf (
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"dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
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"dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
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mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
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mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
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puts ("\n"
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"External Bus\n"
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"pbear pbesr0 pbesr1 epcr\n");
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mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd));
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puts ("\n"
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"pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n");
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mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd));
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puts ("\n"
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"pb4cr pb4ap\n");
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mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd));
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mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd));
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puts ("\n\n");
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#elif defined(CONFIG_5xx)
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl5xx_t *memctl = &immap->im_memctl;
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volatile sysconf5xx_t *sysconf = &immap->im_siu_conf;
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volatile sit5xx_t *timers = &immap->im_sit;
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volatile car5xx_t *car = &immap->im_clkrst;
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volatile uimb5xx_t *uimb = &immap->im_uimb;
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puts ("\nSystem Configuration registers\n");
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printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
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printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
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printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
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printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
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printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
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puts ("\nMemory Controller Registers\n");
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printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
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printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
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printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
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printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
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printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
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printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
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puts ("\nSystem Integration Timers\n");
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printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
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printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
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puts ("\nClocks and Reset\n");
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printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
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puts ("\nU-Bus to IMB3 Bus Interface\n");
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printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
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puts ("\n\n");
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#elif defined(CONFIG_MPC5200)
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puts ("\nMPC5200 registers\n");
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printf ("MBAR=%08x\n", CFG_MBAR);
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puts ("Memory map registers\n");
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printf ("\tCS0: start %08X\tstop %08X\tconfig %08X\ten %d\n",
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*(volatile ulong*)MPC5XXX_CS0_START,
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*(volatile ulong*)MPC5XXX_CS0_STOP,
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*(volatile ulong*)MPC5XXX_CS0_CFG,
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(*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
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printf ("\tCS1: start %08X\tstop %08X\tconfig %08X\ten %d\n",
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*(volatile ulong*)MPC5XXX_CS1_START,
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*(volatile ulong*)MPC5XXX_CS1_STOP,
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*(volatile ulong*)MPC5XXX_CS1_CFG,
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(*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
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printf ("\tCS2: start %08X\tstop %08X\tconfig %08X\ten %d\n",
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*(volatile ulong*)MPC5XXX_CS2_START,
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*(volatile ulong*)MPC5XXX_CS2_STOP,
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*(volatile ulong*)MPC5XXX_CS2_CFG,
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(*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
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printf ("\tCS3: start %08X\tstop %08X\tconfig %08X\ten %d\n",
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*(volatile ulong*)MPC5XXX_CS3_START,
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*(volatile ulong*)MPC5XXX_CS3_STOP,
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*(volatile ulong*)MPC5XXX_CS3_CFG,
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(*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
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printf ("\tCS4: start %08X\tstop %08X\tconfig %08X\ten %d\n",
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*(volatile ulong*)MPC5XXX_CS4_START,
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*(volatile ulong*)MPC5XXX_CS4_STOP,
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*(volatile ulong*)MPC5XXX_CS4_CFG,
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(*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
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printf ("\tCS5: start %08X\tstop %08X\tconfig %08X\ten %d\n",
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*(volatile ulong*)MPC5XXX_CS5_START,
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*(volatile ulong*)MPC5XXX_CS5_STOP,
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*(volatile ulong*)MPC5XXX_CS5_CFG,
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(*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
|
|
printf ("\tCS6: start %08X\tstop %08X\tconfig %08X\ten %d\n",
|
|
*(volatile ulong*)MPC5XXX_CS6_START,
|
|
*(volatile ulong*)MPC5XXX_CS6_STOP,
|
|
*(volatile ulong*)MPC5XXX_CS6_CFG,
|
|
(*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
|
|
printf ("\tCS7: start %08X\tstop %08X\tconfig %08X\ten %d\n",
|
|
*(volatile ulong*)MPC5XXX_CS7_START,
|
|
*(volatile ulong*)MPC5XXX_CS7_STOP,
|
|
*(volatile ulong*)MPC5XXX_CS7_CFG,
|
|
(*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
|
|
printf ("\tBOOTCS: start %08X\tstop %08X\tconfig %08X\ten %d\n",
|
|
*(volatile ulong*)MPC5XXX_BOOTCS_START,
|
|
*(volatile ulong*)MPC5XXX_BOOTCS_STOP,
|
|
*(volatile ulong*)MPC5XXX_BOOTCS_CFG,
|
|
(*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
|
|
printf ("\tSDRAMCS0: %08X\n",
|
|
*(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
|
|
printf ("\tSDRAMCS1: %08X\n",
|
|
*(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
|
|
#elif defined(CONFIG_MPC86xx)
|
|
mpc86xx_reginfo();
|
|
|
|
#elif defined(CONFIG_BLACKFIN)
|
|
puts("\nSystem Configuration registers\n");
|
|
|
|
puts("\nPLL Registers\n");
|
|
printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n",
|
|
bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
|
|
printf("\tPLL_STAT: 0x%04x PLL_LOCKCNT: 0x%04x\n",
|
|
bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
|
|
printf("\tVR_CTL: 0x%04x\n", bfin_read_VR_CTL());
|
|
|
|
puts("\nEBIU AMC Registers\n");
|
|
printf("\tEBIU_AMGCTL: 0x%04x\n", bfin_read_EBIU_AMGCTL());
|
|
printf("\tEBIU_AMBCTL0: 0x%08x EBIU_AMBCTL1: 0x%08x\n",
|
|
bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
|
|
# ifdef EBIU_MODE
|
|
printf("\tEBIU_MBSCTL: 0x%08x EBIU_ARBSTAT: 0x%08x\n",
|
|
bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
|
|
printf("\tEBIU_MODE: 0x%08x EBIU_FCTL: 0x%08x\n",
|
|
bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
|
|
# endif
|
|
|
|
# ifdef EBIU_RSTCTL
|
|
puts("\nEBIU DDR Registers\n");
|
|
printf("\tEBIU_DDRCTL0: 0x%08x EBIU_DDRCTL1: 0x%08x\n",
|
|
bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
|
|
printf("\tEBIU_DDRCTL2: 0x%08x EBIU_DDRCTL3: 0x%08x\n",
|
|
bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
|
|
printf("\tEBIU_DDRQUE: 0x%08x EBIU_RSTCTL 0x%04x\n",
|
|
bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
|
|
printf("\tEBIU_ERRADD: 0x%08x EBIU_ERRMST: 0x%04x\n",
|
|
bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
|
|
# else
|
|
puts("\nEBIU SDC Registers\n");
|
|
printf("\tEBIU_SDRRC: 0x%04x EBIU_SDBCTL: 0x%04x\n",
|
|
bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
|
|
printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n",
|
|
bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
|
|
# endif
|
|
|
|
#endif /* CONFIG_BLACKFIN */
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**************************************************/
|
|
|
|
#if defined(CONFIG_CMD_REGINFO)
|
|
U_BOOT_CMD(
|
|
reginfo, 2, 1, do_reginfo,
|
|
"reginfo - print register information\n",
|
|
);
|
|
#endif
|