34e026f9b1
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>
19 lines
367 B
C
19 lines
367 B
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_DDRC_VER_H
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#define __FSL_DDRC_VER_H
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/*
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* Only the versions with distinct features or registers are listed here.
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*/
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#define FSL_DDR_VER_4_4 44
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#define FSL_DDR_VER_4_6 46
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#define FSL_DDR_VER_4_7 47
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#define FSL_DDR_VER_5_0 50
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#endif /* __FSL_DDRC_VER_H */
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