Bin Meng ea53f1c742 riscv: Add CSR numbers ... The standard RISC-V ISA sets aside a 12-bit encoding space for up to 4096 CSRs. This adds all known CSR numbers as defined in the RISC-V Privileged Architecture Version 1.10. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>		2018-12-18 09:56:27 +08:00
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cpu	riscv: Remove non-DM version of print_cpuinfo()	2018-12-18 09:56:27 +08:00
dts	riscv: dts: Add ae350_32.dts for RV32I	2018-11-26 13:57:55 +08:00
include/asm	riscv: Add CSR numbers	2018-12-18 09:56:27 +08:00
lib	riscv: Implement riscv_get_time() API using rdtime instruction	2018-12-18 09:56:27 +08:00
config.mk	riscv: enable -fdata-sections	2018-11-26 13:57:29 +08:00
Kconfig	riscv: Enlarge the default SYS_MALLOC_F_LEN	2018-12-18 09:56:27 +08:00
Makefile	riscv: add Kconfig entries for the code model	2018-12-18 09:56:26 +08:00