bf3a08bec8
This board file supports standard features of Odroid X2 and U3 boards: - Exynos4412 core clock set to 1000MHz and MPLL peripherial clock set to 800MHz, - MAX77686 power regulator, - USB PHY, - enable XCL205 - power for board peripherials - check board type: U3 or X2. - enable Odroid U3 FAN cooler Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
256 lines
8.7 KiB
C
256 lines
8.7 KiB
C
/*
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* Copyright (C) 2014 Samsung Electronics
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* Przemyslaw Marczak <p.marczak@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ODROIDU3_SETUP__
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#define __ODROIDU3_SETUP__
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/* A/M PLL_CON0 */
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#define SDIV(x) ((x) & 0x7)
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#define PDIV(x) (((x) & 0x3f) << 8)
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#define MDIV(x) (((x) & 0x3ff) << 16)
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#define FSEL(x) (((x) & 0x1) << 27)
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#define PLL_LOCKED_BIT (0x1 << 29)
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#define PLL_ENABLE(x) (((x) & 0x1) << 31)
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/* CLK_SRC_CPU */
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#define MUX_APLL_SEL(x) ((x) & 0x1)
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#define MUX_CORE_SEL(x) (((x) & 0x1) << 16)
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#define MUX_HPM_SEL(x) (((x) & 0x1) << 20)
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#define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24)
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#define MUX_STAT_CHANGING 0x100
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/* CLK_MUX_STAT_CPU */
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#define APLL_SEL(x) ((x) & 0x7)
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#define CORE_SEL(x) (((x) & 0x7) << 16)
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#define HPM_SEL(x) (((x) & 0x7) << 20)
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#define MPLL_USER_SEL_C(x) (((x) & 0x7) << 24)
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#define MUX_STAT_CPU_CHANGING (APLL_SEL(MUX_STAT_CHANGING) | \
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CORE_SEL(MUX_STAT_CHANGING) | \
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HPM_SEL(MUX_STAT_CHANGING) | \
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MPLL_USER_SEL_C(MUX_STAT_CHANGING))
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/* CLK_DIV_CPU0 */
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#define CORE_RATIO(x) ((x) & 0x7)
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#define COREM0_RATIO(x) (((x) & 0x7) << 4)
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#define COREM1_RATIO(x) (((x) & 0x7) << 8)
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#define PERIPH_RATIO(x) (((x) & 0x7) << 12)
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#define ATB_RATIO(x) (((x) & 0x7) << 16)
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#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20)
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#define APLL_RATIO(x) (((x) & 0x7) << 24)
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#define CORE2_RATIO(x) (((x) & 0x7) << 28)
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/* CLK_DIV_STAT_CPU0 */
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#define DIV_CORE(x) ((x) & 0x1)
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#define DIV_COREM0(x) (((x) & 0x1) << 4)
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#define DIV_COREM1(x) (((x) & 0x1) << 8)
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#define DIV_PERIPH(x) (((x) & 0x1) << 12)
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#define DIV_ATB(x) (((x) & 0x1) << 16)
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#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20)
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#define DIV_APLL(x) (((x) & 0x1) << 24)
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#define DIV_CORE2(x) (((x) & 0x1) << 28)
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#define DIV_STAT_CHANGING 0x1
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#define DIV_STAT_CPU0_CHANGING (DIV_CORE(DIV_STAT_CHANGING) | \
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DIV_COREM0(DIV_STAT_CHANGING) | \
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DIV_COREM1(DIV_STAT_CHANGING) | \
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DIV_PERIPH(DIV_STAT_CHANGING) | \
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DIV_ATB(DIV_STAT_CHANGING) | \
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DIV_PCLK_DBG(DIV_STAT_CHANGING) | \
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DIV_APLL(DIV_STAT_CHANGING) | \
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DIV_CORE2(DIV_STAT_CHANGING))
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/* CLK_DIV_CPU1 */
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#define COPY_RATIO(x) ((x) & 0x7)
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#define HPM_RATIO(x) (((x) & 0x7) << 4)
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#define CORES_RATIO(x) (((x) & 0x7) << 8)
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/* CLK_DIV_STAT_CPU1 */
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#define DIV_COPY(x) ((x) & 0x7)
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#define DIV_HPM(x) (((x) & 0x1) << 4)
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#define DIV_CORES(x) (((x) & 0x1) << 8)
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#define DIV_STAT_CPU1_CHANGING (DIV_COPY(DIV_STAT_CHANGING) | \
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DIV_HPM(DIV_STAT_CHANGING) | \
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DIV_CORES(DIV_STAT_CHANGING))
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/* CLK_SRC_DMC */
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#define MUX_C2C_SEL(x) ((x) & 0x1)
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#define MUX_DMC_BUS_SEL(x) (((x) & 0x1) << 4)
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#define MUX_DPHY_SEL(x) (((x) & 0x1) << 8)
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#define MUX_MPLL_SEL(x) (((x) & 0x1) << 12)
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#define MUX_PWI_SEL(x) (((x) & 0xf) << 16)
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#define MUX_G2D_ACP0_SEL(x) (((x) & 0x1) << 20)
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#define MUX_G2D_ACP1_SEL(x) (((x) & 0x1) << 24)
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#define MUX_G2D_ACP_SEL(x) (((x) & 0x1) << 28)
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/* CLK_MUX_STAT_DMC */
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#define C2C_SEL(x) (((x)) & 0x7)
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#define DMC_BUS_SEL(x) (((x) & 0x7) << 4)
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#define DPHY_SEL(x) (((x) & 0x7) << 8)
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#define MPLL_SEL(x) (((x) & 0x7) << 12)
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/* #define PWI_SEL(x) (((x) & 0xf) << 16) - Reserved */
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#define G2D_ACP0_SEL(x) (((x) & 0x7) << 20)
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#define G2D_ACP1_SEL(x) (((x) & 0x7) << 24)
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#define G2D_ACP_SEL(x) (((x) & 0x7) << 28)
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#define MUX_STAT_DMC_CHANGING (C2C_SEL(MUX_STAT_CHANGING) | \
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DMC_BUS_SEL(MUX_STAT_CHANGING) | \
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DPHY_SEL(MUX_STAT_CHANGING) | \
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MPLL_SEL(MUX_STAT_CHANGING) |\
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G2D_ACP0_SEL(MUX_STAT_CHANGING) | \
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G2D_ACP1_SEL(MUX_STAT_CHANGING) | \
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G2D_ACP_SEL(MUX_STAT_CHANGING))
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/* CLK_DIV_DMC0 */
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#define ACP_RATIO(x) ((x) & 0x7)
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#define ACP_PCLK_RATIO(x) (((x) & 0x7) << 4)
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#define DPHY_RATIO(x) (((x) & 0x7) << 8)
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#define DMC_RATIO(x) (((x) & 0x7) << 12)
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#define DMCD_RATIO(x) (((x) & 0x7) << 16)
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#define DMCP_RATIO(x) (((x) & 0x7) << 20)
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/* CLK_DIV_STAT_DMC0 */
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#define DIV_ACP(x) ((x) & 0x1)
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#define DIV_ACP_PCLK(x) (((x) & 0x1) << 4)
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#define DIV_DPHY(x) (((x) & 0x1) << 8)
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#define DIV_DMC(x) (((x) & 0x1) << 12)
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#define DIV_DMCD(x) (((x) & 0x1) << 16)
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#define DIV_DMCP(x) (((x) & 0x1) << 20)
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#define DIV_STAT_DMC0_CHANGING (DIV_ACP(DIV_STAT_CHANGING) | \
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DIV_ACP_PCLK(DIV_STAT_CHANGING) | \
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DIV_DPHY(DIV_STAT_CHANGING) | \
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DIV_DMC(DIV_STAT_CHANGING) | \
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DIV_DMCD(DIV_STAT_CHANGING) | \
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DIV_DMCP(DIV_STAT_CHANGING))
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/* CLK_DIV_DMC1 */
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#define G2D_ACP_RATIO(x) ((x) & 0xf)
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#define C2C_RATIO(x) (((x) & 0x7) << 4)
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#define PWI_RATIO(x) (((x) & 0xf) << 8)
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#define C2C_ACLK_RATIO(x) (((x) & 0x7) << 12)
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#define DVSEM_RATIO(x) (((x) & 0x7f) << 16)
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#define DPM_RATIO(x) (((x) & 0x7f) << 24)
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/* CLK_DIV_STAT_DMC1 */
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#define DIV_G2D_ACP(x) ((x) & 0x1)
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#define DIV_C2C(x) (((x) & 0x1) << 4)
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#define DIV_PWI(x) (((x) & 0x1) << 8)
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#define DIV_C2C_ACLK(x) (((x) & 0x1) << 12)
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#define DIV_DVSEM(x) (((x) & 0x1) << 16)
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#define DIV_DPM(x) (((x) & 0x1) << 24)
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#define DIV_STAT_DMC1_CHANGING (DIV_G2D_ACP(DIV_STAT_CHANGING) | \
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DIV_C2C(DIV_STAT_CHANGING) | \
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DIV_PWI(DIV_STAT_CHANGING) | \
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DIV_C2C_ACLK(DIV_STAT_CHANGING) | \
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DIV_DVSEM(DIV_STAT_CHANGING) | \
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DIV_DPM(DIV_STAT_CHANGING))
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/* Set CLK_SRC_PERIL0 */
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#define UART4_SEL(x) (((x) & 0xf) << 16)
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#define UART3_SEL(x) (((x) & 0xf) << 12)
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#define UART2_SEL(x) (((x) & 0xf) << 8)
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#define UART1_SEL(x) (((x) & 0xf) << 4)
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#define UART0_SEL(x) ((x) & 0xf)
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/* Set CLK_DIV_PERIL0 */
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#define UART4_RATIO(x) (((x) & 0xf) << 16)
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#define UART3_RATIO(x) (((x) & 0xf) << 12)
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#define UART2_RATIO(x) (((x) & 0xf) << 8)
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#define UART1_RATIO(x) (((x) & 0xf) << 4)
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#define UART0_RATIO(x) ((x) & 0xf)
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/* Set CLK_DIV_STAT_PERIL0 */
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#define DIV_UART4(x) (((x) & 0x1) << 16)
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#define DIV_UART3(x) (((x) & 0x1) << 12)
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#define DIV_UART2(x) (((x) & 0x1) << 8)
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#define DIV_UART1(x) (((x) & 0x1) << 4)
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#define DIV_UART0(x) ((x) & 0x1)
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#define DIV_STAT_PERIL0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \
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DIV_UART3(DIV_STAT_CHANGING) | \
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DIV_UART2(DIV_STAT_CHANGING) | \
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DIV_UART1(DIV_STAT_CHANGING) | \
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DIV_UART0(DIV_STAT_CHANGING))
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/* CLK_DIV_FSYS1 */
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#define MMC0_RATIO(x) ((x) & 0xf)
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#define MMC0_PRE_RATIO(x) (((x) & 0xff) << 8)
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#define MMC1_RATIO(x) (((x) & 0xf) << 16)
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#define MMC1_PRE_RATIO(x) (((x) & 0xff) << 24)
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/* CLK_DIV_STAT_FSYS1 */
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#define DIV_MMC0(x) ((x) & 1)
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#define DIV_MMC0_PRE(x) (((x) & 1) << 8)
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#define DIV_MMC1(x) (((x) & 1) << 16)
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#define DIV_MMC1_PRE(x) (((x) & 1) << 24)
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#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \
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DIV_MMC0_PRE(DIV_STAT_CHANGING) | \
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DIV_MMC1(DIV_STAT_CHANGING) | \
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DIV_MMC1_PRE(DIV_STAT_CHANGING))
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/* CLK_DIV_FSYS2 */
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#define MMC2_RATIO(x) ((x) & 0xf)
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#define MMC2_PRE_RATIO(x) (((x) & 0xff) << 8)
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#define MMC3_RATIO(x) (((x) & 0xf) << 16)
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#define MMC3_PRE_RATIO(x) (((x) & 0xff) << 24)
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/* CLK_DIV_STAT_FSYS2 */
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#define DIV_MMC2(x) ((x) & 0x1)
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#define DIV_MMC2_PRE(x) (((x) & 0x1) << 8)
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#define DIV_MMC3(x) (((x) & 0x1) << 16)
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#define DIV_MMC3_PRE(x) (((x) & 0x1) << 24)
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#define DIV_STAT_FSYS2_CHANGING (DIV_MMC2(DIV_STAT_CHANGING) | \
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DIV_MMC2_PRE(DIV_STAT_CHANGING) | \
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DIV_MMC3(DIV_STAT_CHANGING) | \
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DIV_MMC3_PRE(DIV_STAT_CHANGING))
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/* CLK_DIV_FSYS3 */
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#define MMC4_RATIO(x) ((x) & 0x7)
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#define MMC4_PRE_RATIO(x) (((x) & 0xff) << 8)
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/* CLK_DIV_STAT_FSYS3 */
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#define DIV_MMC4(x) ((x) & 0x1)
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#define DIV_MMC4_PRE(x) (((x) & 0x1) << 8)
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#define DIV_STAT_FSYS3_CHANGING (DIV_MMC4(DIV_STAT_CHANGING) | \
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DIV_MMC4_PRE(DIV_STAT_CHANGING))
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/* XCL205 GPIO config - Odroid U3 */
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#define XCL205_GPIO_BASE EXYNOS4X12_GPIO_PART1_BASE
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#define XCL205_EN_GPIO_OFFSET 0x20 /* GPA1 */
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#define XCL205_EN_GPIO_PIN 1
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#define XCL205_EN_GPIO_CON (XCL205_GPIO_BASE + \
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XCL205_EN_GPIO_OFFSET)
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#define XCL205_EN_GPIO_CON_CFG (S5P_GPIO_OUTPUT << \
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4 * XCL205_EN_GPIO_PIN)
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#define XCL205_EN_GPIO_DAT_CFG (0x1 << XCL205_EN_GPIO_PIN)
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#define XCL205_EN_GPIO_PUD_CFG (S5P_GPIO_PULL_UP << \
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2 * XCL205_EN_GPIO_PIN)
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#define XCL205_EN_GPIO_DRV_CFG (S5P_GPIO_DRV_4X << \
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2 * XCL205_EN_GPIO_PIN)
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#define XCL205_STATE_GPIO_OFFSET 0x80 /* GPC1 */
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#define XCL205_STATE_GPIO_PIN 2
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#define XCL205_STATE_GPIO_CON (XCL205_GPIO_BASE + \
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XCL205_STATE_GPIO_OFFSET)
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#define XCL205_STATE_GPIO_DAT XCL205_STATE_GPIO_CON + 0x4
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#define XCL205_STATE_GPIO_CON_CFG (S5P_GPIO_INPUT << \
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4 * XCL205_STATE_GPIO_PIN)
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#define XCL205_STATE_GPIO_PUD_CFG (S5P_GPIO_PULL_NONE << \
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2 * XCL205_STATE_GPIO_PIN)
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#ifdef CONFIG_BOARD_TYPES
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extern void sdelay(unsigned long);
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#endif
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#endif /*__ODROIDU3_SETUP__ */
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