e6e2c15d48
This patch adds device tree control of U-Boot to nios2 boards. The example dts is taken from Linux kernel. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
154 lines
3.5 KiB
Plaintext
154 lines
3.5 KiB
Plaintext
/*
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* Copyright (C) 2013 Altera Corporation
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*
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* This file is generated by sopc2dts.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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/ {
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model = "altr,qsys_ghrd_3c120";
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compatible = "altr,qsys_ghrd_3c120";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu: cpu@0x0 {
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device_type = "cpu";
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compatible = "altr,nios2-1.0";
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reg = <0x00000000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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clock-frequency = <125000000>;
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dcache-line-size = <32>;
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icache-line-size = <32>;
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dcache-size = <32768>;
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icache-size = <32768>;
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altr,implementation = "fast";
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altr,pid-num-bits = <8>;
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altr,tlb-num-ways = <16>;
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altr,tlb-num-entries = <128>;
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altr,tlb-ptr-sz = <7>;
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altr,has-div = <1>;
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altr,has-mul = <1>;
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altr,reset-addr = <0xc2800000>;
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altr,fast-tlb-miss-addr = <0xc7fff400>;
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altr,exception-addr = <0xd0000020>;
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altr,has-initda = <1>;
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altr,has-mmu = <1>;
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};
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};
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memory@0 {
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device_type = "memory";
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reg = <0x10000000 0x08000000>,
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<0x07fff400 0x00000400>;
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};
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sopc@0 {
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device_type = "soc";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "altr,avalon", "simple-bus";
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bus-frequency = <125000000>;
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pb_cpu_to_io: bridge@0x8000000 {
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compatible = "simple-bus";
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reg = <0x08000000 0x00800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00002000 0x08002000 0x00002000>,
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<0x00004000 0x08004000 0x00000400>,
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<0x00004400 0x08004400 0x00000040>,
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<0x00004800 0x08004800 0x00000040>,
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<0x00004c80 0x08004c80 0x00000020>,
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<0x00004d50 0x08004d50 0x00000008>,
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<0x00008000 0x08008000 0x00000020>,
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<0x00400000 0x08400000 0x00000020>;
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timer_1ms: timer@0x400000 {
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compatible = "altr,timer-1.0";
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reg = <0x00400000 0x00000020>;
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interrupt-parent = <&cpu>;
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interrupts = <11>;
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clock-frequency = <125000000>;
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};
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timer_0: timer@0x8000 {
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compatible = "altr,timer-1.0";
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reg = < 0x00008000 0x00000020 >;
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interrupt-parent = < &cpu >;
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interrupts = < 5 >;
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clock-frequency = < 125000000 >;
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};
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jtag_uart: serial@0x4d50 {
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compatible = "altr,juart-1.0";
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reg = <0x00004d50 0x00000008>;
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interrupt-parent = <&cpu>;
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interrupts = <1>;
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};
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tse_mac: ethernet@0x4000 {
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compatible = "altr,tse-1.0";
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reg = <0x00004000 0x00000400>,
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<0x00004400 0x00000040>,
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<0x00004800 0x00000040>,
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<0x00002000 0x00002000>;
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reg-names = "control_port", "rx_csr", "tx_csr", "s1";
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interrupt-parent = <&cpu>;
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interrupts = <2 3>;
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interrupt-names = "rx_irq", "tx_irq";
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rx-fifo-depth = <8192>;
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tx-fifo-depth = <8192>;
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max-frame-size = <1518>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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phy-mode = "rgmii-id";
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phy-handle = <&phy0>;
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tse_mac_mdio: mdio {
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compatible = "altr,tse-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@18 {
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reg = <18>;
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device_type = "ethernet-phy";
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};
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};
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};
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uart: serial@0x4c80 {
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compatible = "altr,uart-1.0";
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reg = <0x00004c80 0x00000020>;
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interrupt-parent = <&cpu>;
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interrupts = <10>;
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current-speed = <115200>;
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clock-frequency = <62500000>;
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};
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};
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cfi_flash_64m: flash@0x0 {
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compatible = "cfi-flash";
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reg = <0x00000000 0x04000000>;
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bank-width = <2>;
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device-width = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@800000 {
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reg = <0x00800000 0x01e00000>;
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label = "JFFS2 Filesystem";
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};
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};
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};
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chosen {
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bootargs = "debug console=ttyJ0,115200";
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};
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};
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