e39eed8f47
The MIO clock is enabled by default, and the STDMAC clock is enabled by the clk driver. The ad-hoc way to enable the clock is no longer needed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
95 lines
3.3 KiB
C
95 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* UniPhier SC (System Control) block registers
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*
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* Copyright (C) 2011-2015 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#ifndef ARCH_SC_REGS_H
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#define ARCH_SC_REGS_H
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#define SC_BASE_ADDR 0x61840000
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#define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110)
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#define SC_DPLLOSCCTRL_DPLLST (0x1 << 1)
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#define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0)
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#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
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#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
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#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
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#define SC_DPLLCTRL_SSC_RATE (0x1 << 15)
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#define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204)
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#define SC_DPLLCTRL2_NRSTDS (0x1 << 28)
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#define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208)
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#define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31)
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#define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31)
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#define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210)
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#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270)
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#define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274)
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#define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278)
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#define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290)
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#define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294)
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#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298)
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#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
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#define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */
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#define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */
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#define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
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#define SC_RSTCTRL_NRST_GIO (0x1 << 6)
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/* Pro4 or older */
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#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
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#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
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#define SC_RSTCTRL_NRST_NAND (0x1 << 2)
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#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004)
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#define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */
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#define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */
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#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
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/* Pro5 or newer */
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#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
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#define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */
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#define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */
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#define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */
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#define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */
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#define SC_RSTCTRL4_NRST_UMC32 (0x1 << 6) /* UMC ch2 */
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#define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */
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#define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */
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#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010)
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#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014)
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#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
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#define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */
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#define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */
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#define SC_CLKCTRL_CEN_ETHER (0x1 << 12)
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#define SC_CLKCTRL_CEN_GIO (0x1 << 6)
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/* Pro4 or older */
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#define SC_CLKCTRL_CEN_UMC (0x1 << 4)
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#define SC_CLKCTRL_CEN_NAND (0x1 << 2)
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#define SC_CLKCTRL_CEN_SBC (0x1 << 1)
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#define SC_CLKCTRL_CEN_PERI (0x1 << 0)
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/* Pro5 or newer */
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#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
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#define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */
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#define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */
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#define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */
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#define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */
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/* System reset control register */
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#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
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#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)
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#define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014)
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#endif /* ARCH_SC_REGS_H */
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