Haiying Wang 1f293b417a Add debug information for DDR controller registers ... Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>		2008-10-18 21:54:05 +02:00
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common_timing_params.h	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	2008-08-27 02:05:58 +02:00
ctrl_regs.c	Add debug information for DDR controller registers	2008-10-18 21:54:05 +02:00
ddr1_dimm_params.c	FSL DDR: Add DDR1 DIMM paramter support	2008-08-27 02:05:59 +02:00
ddr2_dimm_params.c	FSL DDR: Add DDR2 DIMM paramter support	2008-08-27 02:06:00 +02:00
ddr.h	Pass dimm parameters to populate populate controller options	2008-10-18 21:54:04 +02:00
lc_common_dimm_params.c	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	2008-08-27 02:05:58 +02:00
main.c	Check DDR interleaving mode	2008-10-18 21:54:05 +02:00
Makefile	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	2008-08-27 02:05:58 +02:00
options.c	Check DDR interleaving mode	2008-10-18 21:54:05 +02:00
util.c	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	2008-08-27 02:05:58 +02:00