5bd97e8073
Some DWC2 ip variant doesn't use 16 hardware endpoint as hardcoded in the driver. Bits INEps [29:26] of HWCFG4 register allows to get this information. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
96 lines
2.2 KiB
C
96 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Designware DWC2 on-chip full/high speed USB device controllers
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* Copyright (C) 2005 for Samsung Electronics
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*/
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#ifndef __DWC2_UDC_OTG_PRIV__
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#define __DWC2_UDC_OTG_PRIV__
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#include <linux/errno.h>
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#include <linux/sizes.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/list.h>
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#include <usb/dwc2_udc.h>
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/*-------------------------------------------------------------------------*/
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/* DMA bounce buffer size, 16K is enough even for mass storage */
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#define DMA_BUFFER_SIZE (16*SZ_1K)
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#define EP0_FIFO_SIZE 64
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#define EP_FIFO_SIZE 512
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#define EP_FIFO_SIZE2 1024
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/* ep0-control, ep1in-bulk, ep2out-bulk, ep3in-int */
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#define DWC2_MAX_ENDPOINTS 4
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#define WAIT_FOR_SETUP 0
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#define DATA_STATE_XMIT 1
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#define DATA_STATE_NEED_ZLP 2
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#define WAIT_FOR_OUT_STATUS 3
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#define DATA_STATE_RECV 4
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#define WAIT_FOR_COMPLETE 5
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#define WAIT_FOR_OUT_COMPLETE 6
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#define WAIT_FOR_IN_COMPLETE 7
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#define WAIT_FOR_NULL_COMPLETE 8
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#define TEST_J_SEL 0x1
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#define TEST_K_SEL 0x2
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#define TEST_SE0_NAK_SEL 0x3
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#define TEST_PACKET_SEL 0x4
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#define TEST_FORCE_ENABLE_SEL 0x5
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/* ************************************************************************* */
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/* IO
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*/
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enum ep_type {
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ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
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};
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struct dwc2_ep {
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struct usb_ep ep;
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struct dwc2_udc *dev;
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const struct usb_endpoint_descriptor *desc;
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struct list_head queue;
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unsigned long pio_irqs;
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int len;
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void *dma_buf;
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u8 stopped;
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u8 bEndpointAddress;
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u8 bmAttributes;
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enum ep_type ep_type;
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int fifo_num;
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};
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struct dwc2_request {
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struct usb_request req;
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struct list_head queue;
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};
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struct dwc2_udc {
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struct usb_gadget gadget;
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struct usb_gadget_driver *driver;
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struct dwc2_plat_otg_data *pdata;
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int ep0state;
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struct dwc2_ep ep[DWC2_MAX_ENDPOINTS];
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unsigned char usb_address;
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unsigned req_pending:1, req_std:1;
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};
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#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN) == USB_DIR_IN)
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#define ep_index(EP) ((EP)->bEndpointAddress&0xF)
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#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
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void otg_phy_init(struct dwc2_udc *dev);
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void otg_phy_off(struct dwc2_udc *dev);
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#endif /* __DWC2_UDC_OTG_PRIV__ */
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