9f7c58dc0d
Remove the unnecessary nodes for TFABOOT and keep the mandatory part
in SOC dtsi, only the DDRCTRL and DDRPHY addresses.
This patch allows to manage the DDR configuration setting in U-Boot
device tree only if it is needed, when CONFIG_SPL is defined.
With TFABOOT, the DDR configuration is done in TF-A BL2 and the DDR size
is dynamically computed in U-Boot since commit d72e7bbe7c ("ram:
stm32mp1: compute DDR size from DDRCTL registers").
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
57 lines
972 B
Plaintext
57 lines
972 B
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright : STMicroelectronics 2022
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*/
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include "stm32mp15-scmi-u-boot.dtsi"
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/ {
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aliases {
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i2c3 = &i2c4;
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usb0 = &usbotg_hs;
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};
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config {
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u-boot,boot-led = "heartbeat";
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u-boot,error-led = "error";
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u-boot,mmc-env-partition = "u-boot-env";
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st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
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st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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};
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led {
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red {
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label = "error";
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gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
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default-state = "off";
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status = "okay";
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};
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};
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};
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&adc {
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status = "okay";
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};
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&uart4 {
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u-boot,dm-pre-reloc;
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};
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&uart4_pins_a {
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u-boot,dm-pre-reloc;
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pins1 {
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u-boot,dm-pre-reloc;
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};
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pins2 {
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u-boot,dm-pre-reloc;
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/* pull-up on rx to avoid floating level */
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bias-pull-up;
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};
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};
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&usbotg_hs {
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u-boot,force-b-session-valid;
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};
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