8208e9a914
Add device tree for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <lftan.linux@gmail.com>
64 lines
1.0 KiB
Plaintext
64 lines
1.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* U-Boot additions
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*
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* Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
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*/
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#include "socfpga_n5x-u-boot.dtsi"
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/{
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aliases {
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spi0 = &qspi;
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i2c0 = &i2c1;
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};
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memory {
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/*
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* Memory type: DDR4 (non-interleaving mode)
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* 16GB
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* <0 0x00000000 0 0x80000000>,
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* <4 0x80000000 3 0x80000000>;
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*
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* 8GB
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* <0 0x00000000 0 0x80000000>,
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* <2 0x80000000 1 0x80000000>;
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*
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* 4GB
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* <0 0x00000000 0 0x80000000>,
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* <1 0x80000000 0 0x80000000>;
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*
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* Memory type: LPDDR4 (non-interleaving mode)
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* Total memory size 3GB, usable = 2.5GB, 0.5GB trade off for secure
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* region.
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*/
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reg = <0 0x00000000 0 0x60000000>,
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<0x10 0x00100000 0 0x40000000>;
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};
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};
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&flash0 {
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compatible = "jedec,spi-nor";
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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u-boot,dm-pre-reloc;
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};
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&i2c1 {
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status = "okay";
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};
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&mmc {
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drvsel = <3>;
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smplsel = <0>;
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u-boot,dm-pre-reloc;
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};
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&qspi {
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status = "okay";
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};
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&watchdog0 {
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u-boot,dm-pre-reloc;
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};
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