dee4d752be
So far there is only one PCI host controller in the sandbox test configuration. This is normally the case for x86, but it can be common on other architectures like ARM/PPC to have more than one PCI host controller in the system. This updates the case to cover such scenario. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
105 lines
2.9 KiB
C
105 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2015 Google, Inc
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <dm.h>
|
|
#include <asm/io.h>
|
|
#include <dm/test.h>
|
|
#include <test/ut.h>
|
|
|
|
/* Test that sandbox PCI works correctly */
|
|
static int dm_test_pci_base(struct unit_test_state *uts)
|
|
{
|
|
struct udevice *bus;
|
|
|
|
ut_assertok(uclass_get_device(UCLASS_PCI, 0, &bus));
|
|
|
|
return 0;
|
|
}
|
|
DM_TEST(dm_test_pci_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
|
|
|
|
/* Test that sandbox PCI bus numbering and device works correctly */
|
|
static int dm_test_pci_busdev(struct unit_test_state *uts)
|
|
{
|
|
struct udevice *bus;
|
|
struct udevice *emul, *swap;
|
|
|
|
/* Test bus#0 and its devices */
|
|
ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 0, &bus));
|
|
|
|
ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 0, &emul));
|
|
ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x00, 0), &swap));
|
|
ut_assert(device_active(swap));
|
|
ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 1, &emul));
|
|
ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap));
|
|
ut_assert(device_active(swap));
|
|
|
|
/* Test bus#1 and its devices */
|
|
ut_assertok(uclass_get_device_by_seq(UCLASS_PCI, 1, &bus));
|
|
|
|
ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 2, &emul));
|
|
ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &swap));
|
|
ut_assert(device_active(swap));
|
|
ut_assertok(uclass_get_device(UCLASS_PCI_EMUL, 3, &emul));
|
|
ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x0c, 0), &swap));
|
|
ut_assert(device_active(swap));
|
|
|
|
return 0;
|
|
}
|
|
DM_TEST(dm_test_pci_busdev, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
|
|
|
|
/* Test that we can use the swapcase device correctly */
|
|
static int dm_test_pci_swapcase(struct unit_test_state *uts)
|
|
{
|
|
struct udevice *swap;
|
|
ulong io_addr, mem_addr;
|
|
char *ptr;
|
|
|
|
/* Check that asking for the device 0 automatically fires up PCI */
|
|
ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x00, 0), &swap));
|
|
|
|
/* First test I/O */
|
|
io_addr = dm_pci_read_bar32(swap, 0);
|
|
outb(2, io_addr);
|
|
ut_asserteq(2, inb(io_addr));
|
|
|
|
/*
|
|
* Now test memory mapping - note we must unmap and remap to cause
|
|
* the swapcase emulation to see our data and response.
|
|
*/
|
|
mem_addr = dm_pci_read_bar32(swap, 1);
|
|
ptr = map_sysmem(mem_addr, 20);
|
|
strcpy(ptr, "This is a TesT");
|
|
unmap_sysmem(ptr);
|
|
|
|
ptr = map_sysmem(mem_addr, 20);
|
|
ut_asserteq_str("tHIS IS A tESt", ptr);
|
|
unmap_sysmem(ptr);
|
|
|
|
/* Check that asking for the device 1 automatically fires up PCI */
|
|
ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(0, 0x1f, 0), &swap));
|
|
|
|
/* First test I/O */
|
|
io_addr = dm_pci_read_bar32(swap, 0);
|
|
outb(2, io_addr);
|
|
ut_asserteq(2, inb(io_addr));
|
|
|
|
/*
|
|
* Now test memory mapping - note we must unmap and remap to cause
|
|
* the swapcase emulation to see our data and response.
|
|
*/
|
|
mem_addr = dm_pci_read_bar32(swap, 1);
|
|
ptr = map_sysmem(mem_addr, 20);
|
|
strcpy(ptr, "This is a TesT");
|
|
unmap_sysmem(ptr);
|
|
|
|
ptr = map_sysmem(mem_addr, 20);
|
|
ut_asserteq_str("tHIS IS A tESt", ptr);
|
|
unmap_sysmem(ptr);
|
|
|
|
return 0;
|
|
}
|
|
DM_TEST(dm_test_pci_swapcase, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
|